disp: msm: dsi: rename dsi_clk mux as dsiclk_sel to match with HPG

Rename dsi_clk mux as dsiclk_sel to match the naming convention
with HPG.

Change-Id: I50671a78fccdd10d74d43fdf8ef4ede0c55fd09b
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>

msm/dsi/dsi_pll_4nm.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/kernel.h>
@@ -123,23 +123,23 @@ static inline int dsi_pll_get_phy_post_div(struct dsi_pll_resource *pll)
 }
 
 
-static inline void dsi_pll_set_dsi_clk(struct dsi_pll_resource *pll, u32 dsi_clk)
+static inline void dsi_pll_set_dsiclk_sel(struct dsi_pll_resource *pll, u32 dsiclk_sel)
 {
 	u32 reg_val = 0;
 
 	reg_val = DSI_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG1);
 	reg_val &= ~0x3;
-	reg_val |= dsi_clk;
+	reg_val |= dsiclk_sel;
 	DSI_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG1, reg_val);
 	if (pll->slave) {
 		reg_val = DSI_PLL_REG_R(pll->slave->phy_base, PHY_CMN_CLK_CFG1);
 		reg_val &= ~0x3;
-		reg_val |= dsi_clk;
+		reg_val |= dsiclk_sel;
 		DSI_PLL_REG_W(pll->slave->phy_base, PHY_CMN_CLK_CFG1, reg_val);
 	}
 }
 
-static inline int dsi_pll_get_dsi_clk(struct dsi_pll_resource *pll)
+static inline int dsi_pll_get_dsiclk_sel(struct dsi_pll_resource *pll)
 {
 	u32 reg_val;
 
@@ -1081,7 +1081,7 @@ static int dsi_pll_calc_cphy_pclk_div(struct dsi_pll_resource *pll)
 static int dsi_pll_4nm_set_pclk_div(struct dsi_pll_resource *pll, bool commit)
 {
 
-	int dsi_clk = 0, pclk_div = 0;
+	int dsiclk_sel = 0, pclk_div = 0;
 	u64 pclk_src_rate;
 	u32 pll_post_div;
 	u32 phy_post_div;
@@ -1089,13 +1089,13 @@ static int dsi_pll_4nm_set_pclk_div(struct dsi_pll_resource *pll, bool commit)
 	pll_post_div = dsi_pll_get_pll_post_div(pll);
 	pclk_src_rate = div_u64(pll->vco_rate, pll_post_div);
 	if (pll->type == DSI_PHY_TYPE_DPHY) {
-		dsi_clk = 0x1;
+		dsiclk_sel = 0x1;
 		phy_post_div = dsi_pll_get_phy_post_div(pll);
 		pclk_src_rate = div_u64(pclk_src_rate, phy_post_div);
 		pclk_src_rate = div_u64(pclk_src_rate, 2);
 		pclk_div = dsi_pll_calc_dphy_pclk_div(pll);
 	} else {
-		dsi_clk = 0x3;
+		dsiclk_sel = 0x3;
 		pclk_src_rate *= 2;
 		pclk_src_rate = div_u64(pclk_src_rate, 7);
 		pclk_div = dsi_pll_calc_cphy_pclk_div(pll);
@@ -1103,11 +1103,11 @@ static int dsi_pll_4nm_set_pclk_div(struct dsi_pll_resource *pll, bool commit)
 
 	pll->pclk_rate = div_u64(pclk_src_rate, pclk_div);
 
-	DSI_PLL_DBG(pll, "pclk rate: %llu, dsi_clk: %d, pclk_div: %d\n",
-			pll->pclk_rate, dsi_clk, pclk_div);
+	DSI_PLL_DBG(pll, "pclk rate: %llu, dsiclk_sel: %d, pclk_div: %d\n",
+			pll->pclk_rate, dsiclk_sel, pclk_div);
 
 	if (commit) {
-		dsi_pll_set_dsi_clk(pll, dsi_clk);
+		dsi_pll_set_dsiclk_sel(pll, dsiclk_sel);
 		dsi_pll_set_pclk_div(pll, pclk_div);
 	}
 

msm/dsi/dsi_pll_5nm.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/kernel.h>
@@ -128,24 +128,24 @@ static inline int dsi_pll_get_phy_post_div(struct dsi_pll_resource *pll)
 }
 
 
-static inline void dsi_pll_set_dsi_clk(struct dsi_pll_resource *pll, u32
-		dsi_clk)
+static inline void dsi_pll_set_dsiclk_sel(struct dsi_pll_resource *pll, u32
+		dsiclk_sel)
 {
 	u32 reg_val = 0;
 
 	reg_val = DSI_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG1);
 	reg_val &= ~0x3;
-	reg_val |= dsi_clk;
+	reg_val |= dsiclk_sel;
 	DSI_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG1, reg_val);
 	if (pll->slave) {
 		reg_val = DSI_PLL_REG_R(pll->slave->phy_base, PHY_CMN_CLK_CFG1);
 		reg_val &= ~0x3;
-		reg_val |= dsi_clk;
+		reg_val |= dsiclk_sel;
 		DSI_PLL_REG_W(pll->slave->phy_base, PHY_CMN_CLK_CFG1, reg_val);
 	}
 }
 
-static inline int dsi_pll_get_dsi_clk(struct dsi_pll_resource *pll)
+static inline int dsi_pll_get_dsiclk_sel(struct dsi_pll_resource *pll)
 {
 	u32 reg_val;
 
@@ -1151,7 +1151,7 @@ static int dsi_pll_calc_cphy_pclk_div(struct dsi_pll_resource *pll)
 static int dsi_pll_5nm_set_pclk_div(struct dsi_pll_resource *pll, bool commit)
 {
 
-	int dsi_clk = 0, pclk_div = 0;
+	int dsiclk_sel = 0, pclk_div = 0;
 	u64 pclk_src_rate;
 	u32 pll_post_div;
 	u32 phy_post_div;
@@ -1159,13 +1159,13 @@ static int dsi_pll_5nm_set_pclk_div(struct dsi_pll_resource *pll, bool commit)
 	pll_post_div = dsi_pll_get_pll_post_div(pll);
 	pclk_src_rate = div_u64(pll->vco_rate, pll_post_div);
 	if (pll->type == DSI_PHY_TYPE_DPHY) {
-		dsi_clk = 0x1;
+		dsiclk_sel = 0x1;
 		phy_post_div = dsi_pll_get_phy_post_div(pll);
 		pclk_src_rate = div_u64(pclk_src_rate, phy_post_div);
 		pclk_src_rate = div_u64(pclk_src_rate, 2);
 		pclk_div = dsi_pll_calc_dphy_pclk_div(pll);
 	} else {
-		dsi_clk = 0x3;
+		dsiclk_sel = 0x3;
 		pclk_src_rate *= 2;
 		pclk_src_rate = div_u64(pclk_src_rate, 7);
 		pclk_div = dsi_pll_calc_cphy_pclk_div(pll);
@@ -1173,11 +1173,11 @@ static int dsi_pll_5nm_set_pclk_div(struct dsi_pll_resource *pll, bool commit)
 
 	pll->pclk_rate = div_u64(pclk_src_rate, pclk_div);
 
-	DSI_PLL_DBG(pll, "pclk rate: %llu, dsi_clk: %d, pclk_div: %d\n",
-			pll->pclk_rate, dsi_clk, pclk_div);
+	DSI_PLL_DBG(pll, "pclk rate: %llu, dsiclk_sel: %d, pclk_div: %d\n",
+			pll->pclk_rate, dsiclk_sel, pclk_div);
 
 	if (commit) {
-		dsi_pll_set_dsi_clk(pll, dsi_clk);
+		dsi_pll_set_dsiclk_sel(pll, dsiclk_sel);
 		dsi_pll_set_pclk_div(pll, pclk_div);
 	}