Merge "ASoC: AQT1000: add codec entry for AQT1000 codec"
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b51bf58343
805
asoc/codecs/aqt1000/aqt1000-clsh.c
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805
asoc/codecs/aqt1000/aqt1000-clsh.c
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@@ -0,0 +1,805 @@
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <sound/soc.h>
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#include "aqt1000-registers.h"
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#include "aqt1000-clsh.h"
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#define AQT_USLEEP_RANGE 50
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#define MAX_IMPED_PARAMS 6
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enum aqt_vref_dac_sel {
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VREF_N1P9V = 0,
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VREF_N1P86V,
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VREF_N181V,
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VREF_N1P74V,
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VREF_N1P7V,
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VREF_N0P9V,
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VREF_N1P576V,
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VREF_N1P827V,
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};
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enum aqt_vref_ctl {
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CONTROLLER = 0,
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I2C,
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};
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enum aqt_hd2_res_div_ctl {
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DISCONNECT = 0,
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P5_0P35,
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P75_0P68,
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P82_0P77,
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P9_0P87,
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};
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enum aqt_curr_bias_err_amp {
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I_0P25UA = 0,
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I_0P5UA,
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I_0P75UA,
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I_1UA,
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I_1P25UA,
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I_1P5UA,
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I_1P75UA,
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I_2UA,
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};
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static const struct aqt_reg_mask_val imped_table_aqt[][MAX_IMPED_PARAMS] = {
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{
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{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xf2},
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{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xf2},
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{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x00},
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{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xf2},
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{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xf2},
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{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x00},
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},
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{
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{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xf4},
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{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xf4},
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{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x00},
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{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xf4},
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{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xf4},
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{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x00},
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},
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{
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{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xf7},
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{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xf7},
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{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x01},
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{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xf7},
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{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xf7},
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{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x01},
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},
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{
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{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xf9},
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{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xf9},
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{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x00},
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{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xf9},
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{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xf9},
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{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x00},
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},
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{
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{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xfa},
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{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xfa},
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{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x00},
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{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xfa},
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{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xfa},
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{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x00},
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},
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{
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{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xfb},
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{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xfb},
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{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x00},
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{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xfb},
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{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xfb},
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{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x00},
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},
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{
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{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xfc},
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{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xfc},
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{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x00},
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{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xfc},
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{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xfc},
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{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x00},
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},
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{
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{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xfd},
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{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xfd},
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{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x00},
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{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xfd},
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{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xfd},
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{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x00},
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},
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{
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{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xfd},
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{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xfd},
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{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x01},
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{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xfd},
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{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xfd},
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{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x01},
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},
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};
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static const struct aqt_imped_val imped_index[] = {
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{4, 0},
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{5, 1},
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{6, 2},
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{7, 3},
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{8, 4},
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{9, 5},
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{10, 6},
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{11, 7},
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{12, 8},
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{13, 9},
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};
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static void (*clsh_state_fp[NUM_CLSH_STATES])(struct snd_soc_codec *,
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struct aqt_clsh_cdc_data *,
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u8 req_state, bool en, int mode);
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static int get_impedance_index(int imped)
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{
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int i = 0;
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if (imped < imped_index[i].imped_val) {
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pr_debug("%s, detected impedance is less than 4 Ohm\n",
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__func__);
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i = 0;
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goto ret;
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}
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if (imped >= imped_index[ARRAY_SIZE(imped_index) - 1].imped_val) {
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pr_debug("%s, detected impedance is greater than 12 Ohm\n",
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__func__);
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i = ARRAY_SIZE(imped_index) - 1;
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goto ret;
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}
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for (i = 0; i < ARRAY_SIZE(imped_index) - 1; i++) {
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if (imped >= imped_index[i].imped_val &&
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imped < imped_index[i + 1].imped_val)
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break;
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}
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ret:
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pr_debug("%s: selected impedance index = %d\n",
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__func__, imped_index[i].index);
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return imped_index[i].index;
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}
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/*
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* Function: aqt_clsh_imped_config
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* Params: codec, imped, reset
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* Description:
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* This function updates HPHL and HPHR gain settings
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* according to the impedance value.
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*/
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void aqt_clsh_imped_config(struct snd_soc_codec *codec, int imped, bool reset)
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{
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int i;
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int index = 0;
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int table_size;
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static const struct aqt_reg_mask_val
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(*imped_table_ptr)[MAX_IMPED_PARAMS];
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table_size = ARRAY_SIZE(imped_table_aqt);
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imped_table_ptr = imped_table_aqt;
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/* reset = 1, which means request is to reset the register values */
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if (reset) {
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for (i = 0; i < MAX_IMPED_PARAMS; i++)
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snd_soc_update_bits(codec,
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imped_table_ptr[index][i].reg,
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imped_table_ptr[index][i].mask, 0);
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return;
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}
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index = get_impedance_index(imped);
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if (index >= (ARRAY_SIZE(imped_index) - 1)) {
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pr_debug("%s, impedance not in range = %d\n", __func__, imped);
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return;
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}
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if (index >= table_size) {
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pr_debug("%s, impedance index not in range = %d\n", __func__,
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index);
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return;
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}
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for (i = 0; i < MAX_IMPED_PARAMS; i++)
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snd_soc_update_bits(codec,
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imped_table_ptr[index][i].reg,
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imped_table_ptr[index][i].mask,
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imped_table_ptr[index][i].val);
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}
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EXPORT_SYMBOL(aqt_clsh_imped_config);
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static const char *mode_to_str(int mode)
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{
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switch (mode) {
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case CLS_H_NORMAL:
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return "CLS_H_NORMAL";
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case CLS_H_HIFI:
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return "CLS_H_HIFI";
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case CLS_H_LOHIFI:
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return "CLS_H_LOHIFI";
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case CLS_H_LP:
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return "CLS_H_LP";
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case CLS_H_ULP:
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return "CLS_H_ULP";
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case CLS_AB:
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return "CLS_AB";
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case CLS_AB_HIFI:
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return "CLS_AB_HIFI";
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default:
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return "CLS_H_INVALID";
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};
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}
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static const char *const state_to_str[] = {
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[AQT_CLSH_STATE_IDLE] = "STATE_IDLE",
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[AQT_CLSH_STATE_HPHL] = "STATE_HPH_L",
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[AQT_CLSH_STATE_HPHR] = "STATE_HPH_R",
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[AQT_CLSH_STATE_HPH_ST] = "STATE_HPH_ST",
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};
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static inline void
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aqt_enable_clsh_block(struct snd_soc_codec *codec,
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struct aqt_clsh_cdc_data *clsh_d, bool enable)
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{
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if ((enable && ++clsh_d->clsh_users == 1) ||
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(!enable && --clsh_d->clsh_users == 0))
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snd_soc_update_bits(codec, AQT1000_CDC_CLSH_CRC, 0x01,
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(u8) enable);
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if (clsh_d->clsh_users < 0)
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clsh_d->clsh_users = 0;
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dev_dbg(codec->dev, "%s: clsh_users %d, enable %d", __func__,
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clsh_d->clsh_users, enable);
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|
}
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|
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static inline bool aqt_clsh_enable_status(struct snd_soc_codec *codec)
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|
{
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return snd_soc_read(codec, AQT1000_CDC_CLSH_CRC) & 0x01;
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|
}
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|
|
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static inline int aqt_clsh_get_int_mode(struct aqt_clsh_cdc_data *clsh_d,
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int clsh_state)
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|
{
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||||||
|
int mode;
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|
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||||||
|
if ((clsh_state != AQT_CLSH_STATE_HPHL) &&
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|
(clsh_state != AQT_CLSH_STATE_HPHR))
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mode = CLS_NONE;
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|
else
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mode = clsh_d->interpolator_modes[ffs(clsh_state)];
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|
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||||||
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return mode;
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|
}
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|
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static inline void aqt_clsh_set_int_mode(struct aqt_clsh_cdc_data *clsh_d,
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|
int clsh_state, int mode)
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||||||
|
{
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||||||
|
if ((clsh_state != AQT_CLSH_STATE_HPHL) &&
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||||||
|
(clsh_state != AQT_CLSH_STATE_HPHR))
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|
return;
|
||||||
|
|
||||||
|
clsh_d->interpolator_modes[ffs(clsh_state)] = mode;
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||||||
|
}
|
||||||
|
|
||||||
|
static inline void aqt_clsh_set_buck_mode(struct snd_soc_codec *codec,
|
||||||
|
int mode)
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||||||
|
{
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||||||
|
if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
|
||||||
|
mode == CLS_AB_HIFI || mode == CLS_AB)
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||||||
|
snd_soc_update_bits(codec, AQT1000_ANA_RX_SUPPLIES,
|
||||||
|
0x08, 0x08); /* set to HIFI */
|
||||||
|
else
|
||||||
|
snd_soc_update_bits(codec, AQT1000_ANA_RX_SUPPLIES,
|
||||||
|
0x08, 0x00); /* set to default */
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||||||
|
}
|
||||||
|
|
||||||
|
static inline void aqt_clsh_set_flyback_mode(struct snd_soc_codec *codec,
|
||||||
|
int mode)
|
||||||
|
{
|
||||||
|
if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
|
||||||
|
mode == CLS_AB_HIFI || mode == CLS_AB)
|
||||||
|
snd_soc_update_bits(codec, AQT1000_ANA_RX_SUPPLIES,
|
||||||
|
0x04, 0x04); /* set to HIFI */
|
||||||
|
else
|
||||||
|
snd_soc_update_bits(codec, AQT1000_ANA_RX_SUPPLIES,
|
||||||
|
0x04, 0x00); /* set to Default */
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void aqt_clsh_gm3_boost_disable(struct snd_soc_codec *codec,
|
||||||
|
int mode)
|
||||||
|
{
|
||||||
|
if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
|
||||||
|
mode == CLS_AB_HIFI || mode == CLS_AB) {
|
||||||
|
snd_soc_update_bits(codec, AQT1000_HPH_CNP_WG_CTL,
|
||||||
|
0x80, 0x0); /* disable GM3 Boost */
|
||||||
|
snd_soc_update_bits(codec, AQT1000_FLYBACK_VNEG_CTRL_4,
|
||||||
|
0xF0, 0x80);
|
||||||
|
} else {
|
||||||
|
snd_soc_update_bits(codec, AQT1000_HPH_CNP_WG_CTL,
|
||||||
|
0x80, 0x80); /* set to Default */
|
||||||
|
snd_soc_update_bits(codec, AQT1000_FLYBACK_VNEG_CTRL_4,
|
||||||
|
0xF0, 0x70);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void aqt_clsh_flyback_dac_ctl(struct snd_soc_codec *codec,
|
||||||
|
int vref)
|
||||||
|
{
|
||||||
|
snd_soc_update_bits(codec, AQT1000_FLYBACK_VNEGDAC_CTRL_2,
|
||||||
|
0xE0, (vref << 5));
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void aqt_clsh_mode_vref_ctl(struct snd_soc_codec *codec,
|
||||||
|
int vref_ctl)
|
||||||
|
{
|
||||||
|
if (vref_ctl == I2C) {
|
||||||
|
snd_soc_update_bits(codec, AQT1000_CLASSH_MODE_3, 0x02, 0x02);
|
||||||
|
snd_soc_update_bits(codec, AQT1000_CLASSH_MODE_2, 0xFF, 0x1C);
|
||||||
|
} else {
|
||||||
|
snd_soc_update_bits(codec, AQT1000_CLASSH_MODE_2, 0xFF, 0x3A);
|
||||||
|
snd_soc_update_bits(codec, AQT1000_CLASSH_MODE_3, 0x02, 0x00);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void aqt_clsh_buck_current_bias_ctl(struct snd_soc_codec *codec,
|
||||||
|
bool enable)
|
||||||
|
{
|
||||||
|
if (enable) {
|
||||||
|
snd_soc_update_bits(codec, AQT1000_BUCK_5V_IBIAS_CTL_4,
|
||||||
|
0x70, (I_2UA << 4));
|
||||||
|
snd_soc_update_bits(codec, AQT1000_BUCK_5V_IBIAS_CTL_4,
|
||||||
|
0x07, I_0P25UA);
|
||||||
|
snd_soc_update_bits(codec, AQT1000_BUCK_5V_CTRL_CCL_2,
|
||||||
|
0x3F, 0x3F);
|
||||||
|
} else {
|
||||||
|
snd_soc_update_bits(codec, AQT1000_BUCK_5V_IBIAS_CTL_4,
|
||||||
|
0x70, (I_1UA << 4));
|
||||||
|
snd_soc_update_bits(codec, AQT1000_BUCK_5V_IBIAS_CTL_4,
|
||||||
|
0x07, I_1UA);
|
||||||
|
snd_soc_update_bits(codec, AQT1000_BUCK_5V_CTRL_CCL_2,
|
||||||
|
0x3F, 0x20);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void aqt_clsh_rdac_hd2_ctl(struct snd_soc_codec *codec,
|
||||||
|
u8 hd2_div_ctl, u8 state)
|
||||||
|
{
|
||||||
|
u16 reg = 0;
|
||||||
|
|
||||||
|
if (state == AQT_CLSH_STATE_HPHL)
|
||||||
|
reg = AQT1000_HPH_NEW_INT_RDAC_HD2_CTL_L;
|
||||||
|
else if (state == AQT_CLSH_STATE_HPHR)
|
||||||
|
reg = AQT1000_HPH_NEW_INT_RDAC_HD2_CTL_R;
|
||||||
|
else
|
||||||
|
dev_err(codec->dev, "%s: Invalid state: %d\n",
|
||||||
|
__func__, state);
|
||||||
|
if (!reg)
|
||||||
|
snd_soc_update_bits(codec, reg, 0x0F, hd2_div_ctl);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void aqt_clsh_force_iq_ctl(struct snd_soc_codec *codec,
|
||||||
|
int mode)
|
||||||
|
{
|
||||||
|
if (mode == CLS_H_LOHIFI || mode == CLS_AB) {
|
||||||
|
snd_soc_update_bits(codec, AQT1000_HPH_NEW_INT_PA_MISC2,
|
||||||
|
0x20, 0x20);
|
||||||
|
snd_soc_update_bits(codec, AQT1000_RX_BIAS_HPH_LOWPOWER,
|
||||||
|
0xF0, 0xC0);
|
||||||
|
snd_soc_update_bits(codec, AQT1000_HPH_PA_CTL1,
|
||||||
|
0x0E, 0x02);
|
||||||
|
} else {
|
||||||
|
|
||||||
|
snd_soc_update_bits(codec, AQT1000_HPH_NEW_INT_PA_MISC2,
|
||||||
|
0x20, 0x0);
|
||||||
|
snd_soc_update_bits(codec, AQT1000_RX_BIAS_HPH_LOWPOWER,
|
||||||
|
0xF0, 0x80);
|
||||||
|
snd_soc_update_bits(codec, AQT1000_HPH_PA_CTL1,
|
||||||
|
0x0E, 0x06);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void aqt_clsh_buck_ctrl(struct snd_soc_codec *codec,
|
||||||
|
struct aqt_clsh_cdc_data *clsh_d,
|
||||||
|
int mode,
|
||||||
|
bool enable)
|
||||||
|
{
|
||||||
|
/* enable/disable buck */
|
||||||
|
if ((enable && (++clsh_d->buck_users == 1)) ||
|
||||||
|
(!enable && (--clsh_d->buck_users == 0)))
|
||||||
|
snd_soc_update_bits(codec, AQT1000_ANA_RX_SUPPLIES,
|
||||||
|
(1 << 7), (enable << 7));
|
||||||
|
dev_dbg(codec->dev, "%s: buck_users %d, enable %d, mode: %s",
|
||||||
|
__func__, clsh_d->buck_users, enable, mode_to_str(mode));
|
||||||
|
/*
|
||||||
|
* 500us sleep is required after buck enable/disable
|
||||||
|
* as per HW requirement
|
||||||
|
*/
|
||||||
|
usleep_range(500, 500 + AQT_USLEEP_RANGE);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void aqt_clsh_flyback_ctrl(struct snd_soc_codec *codec,
|
||||||
|
struct aqt_clsh_cdc_data *clsh_d,
|
||||||
|
int mode,
|
||||||
|
bool enable)
|
||||||
|
{
|
||||||
|
/* enable/disable flyback */
|
||||||
|
if ((enable && (++clsh_d->flyback_users == 1)) ||
|
||||||
|
(!enable && (--clsh_d->flyback_users == 0))) {
|
||||||
|
snd_soc_update_bits(codec, AQT1000_ANA_RX_SUPPLIES,
|
||||||
|
(1 << 6), (enable << 6));
|
||||||
|
/* 100usec delay is needed as per HW requirement */
|
||||||
|
usleep_range(100, 110);
|
||||||
|
}
|
||||||
|
dev_dbg(codec->dev, "%s: flyback_users %d, enable %d, mode: %s",
|
||||||
|
__func__, clsh_d->flyback_users, enable, mode_to_str(mode));
|
||||||
|
/*
|
||||||
|
* 500us sleep is required after flyback enable/disable
|
||||||
|
* as per HW requirement
|
||||||
|
*/
|
||||||
|
usleep_range(500, 500 + AQT_USLEEP_RANGE);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void aqt_clsh_set_hph_mode(struct snd_soc_codec *codec,
|
||||||
|
int mode)
|
||||||
|
{
|
||||||
|
u8 val = 0;
|
||||||
|
u8 gain = 0;
|
||||||
|
u8 res_val = VREF_FILT_R_0OHM;
|
||||||
|
u8 ipeak = DELTA_I_50MA;
|
||||||
|
|
||||||
|
switch (mode) {
|
||||||
|
case CLS_H_NORMAL:
|
||||||
|
res_val = VREF_FILT_R_50KOHM;
|
||||||
|
val = 0x00;
|
||||||
|
gain = DAC_GAIN_0DB;
|
||||||
|
ipeak = DELTA_I_50MA;
|
||||||
|
break;
|
||||||
|
case CLS_AB:
|
||||||
|
val = 0x00;
|
||||||
|
gain = DAC_GAIN_0DB;
|
||||||
|
ipeak = DELTA_I_50MA;
|
||||||
|
break;
|
||||||
|
case CLS_AB_HIFI:
|
||||||
|
val = 0x08;
|
||||||
|
break;
|
||||||
|
case CLS_H_HIFI:
|
||||||
|
val = 0x08;
|
||||||
|
gain = DAC_GAIN_M0P2DB;
|
||||||
|
ipeak = DELTA_I_50MA;
|
||||||
|
break;
|
||||||
|
case CLS_H_LOHIFI:
|
||||||
|
val = 0x00;
|
||||||
|
break;
|
||||||
|
case CLS_H_ULP:
|
||||||
|
val = 0x0C;
|
||||||
|
break;
|
||||||
|
case CLS_H_LP:
|
||||||
|
val = 0x04;
|
||||||
|
ipeak = DELTA_I_30MA;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
return;
|
||||||
|
};
|
||||||
|
|
||||||
|
if (mode == CLS_H_LOHIFI || mode == CLS_AB)
|
||||||
|
val = 0x04;
|
||||||
|
|
||||||
|
snd_soc_update_bits(codec, AQT1000_ANA_HPH, 0x0C, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void aqt_clsh_set_buck_regulator_mode(struct snd_soc_codec *codec,
|
||||||
|
int mode)
|
||||||
|
{
|
||||||
|
snd_soc_update_bits(codec, AQT1000_ANA_RX_SUPPLIES,
|
||||||
|
0x02, 0x00);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void aqt_clsh_state_hph_st(struct snd_soc_codec *codec,
|
||||||
|
struct aqt_clsh_cdc_data *clsh_d,
|
||||||
|
u8 req_state, bool is_enable, int mode)
|
||||||
|
{
|
||||||
|
dev_dbg(codec->dev, "%s: mode: %s, %s\n", __func__, mode_to_str(mode),
|
||||||
|
is_enable ? "enable" : "disable");
|
||||||
|
|
||||||
|
if (mode == CLS_AB || mode == CLS_AB_HIFI)
|
||||||
|
return;
|
||||||
|
|
||||||
|
if (is_enable) {
|
||||||
|
if (req_state == AQT_CLSH_STATE_HPHL)
|
||||||
|
snd_soc_update_bits(codec,
|
||||||
|
AQT1000_CDC_RX1_RX_PATH_CFG0,
|
||||||
|
0x40, 0x40);
|
||||||
|
if (req_state == AQT_CLSH_STATE_HPHR)
|
||||||
|
snd_soc_update_bits(codec,
|
||||||
|
AQT1000_CDC_RX2_RX_PATH_CFG0,
|
||||||
|
0x40, 0x40);
|
||||||
|
} else {
|
||||||
|
if (req_state == AQT_CLSH_STATE_HPHL)
|
||||||
|
snd_soc_update_bits(codec,
|
||||||
|
AQT1000_CDC_RX1_RX_PATH_CFG0,
|
||||||
|
0x40, 0x00);
|
||||||
|
if (req_state == AQT_CLSH_STATE_HPHR)
|
||||||
|
snd_soc_update_bits(codec,
|
||||||
|
AQT1000_CDC_RX2_RX_PATH_CFG0,
|
||||||
|
0x40, 0x00);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void aqt_clsh_state_hph_r(struct snd_soc_codec *codec,
|
||||||
|
struct aqt_clsh_cdc_data *clsh_d,
|
||||||
|
u8 req_state, bool is_enable, int mode)
|
||||||
|
{
|
||||||
|
dev_dbg(codec->dev, "%s: mode: %s, %s\n", __func__, mode_to_str(mode),
|
||||||
|
is_enable ? "enable" : "disable");
|
||||||
|
|
||||||
|
if (mode == CLS_H_NORMAL) {
|
||||||
|
dev_err(codec->dev, "%s: Normal mode not applicable for hph_r\n",
|
||||||
|
__func__);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (is_enable) {
|
||||||
|
if (mode != CLS_AB && mode != CLS_AB_HIFI) {
|
||||||
|
aqt_enable_clsh_block(codec, clsh_d, true);
|
||||||
|
/*
|
||||||
|
* These K1 values depend on the Headphone Impedance
|
||||||
|
* For now it is assumed to be 16 ohm
|
||||||
|
*/
|
||||||
|
snd_soc_update_bits(codec, AQT1000_CDC_CLSH_K1_MSB,
|
||||||
|
0x0F, 0x00);
|
||||||
|
snd_soc_update_bits(codec, AQT1000_CDC_CLSH_K1_LSB,
|
||||||
|
0xFF, 0xC0);
|
||||||
|
snd_soc_update_bits(codec,
|
||||||
|
AQT1000_CDC_RX2_RX_PATH_CFG0,
|
||||||
|
0x40, 0x40);
|
||||||
|
}
|
||||||
|
aqt_clsh_set_buck_regulator_mode(codec, mode);
|
||||||
|
aqt_clsh_set_flyback_mode(codec, mode);
|
||||||
|
aqt_clsh_gm3_boost_disable(codec, mode);
|
||||||
|
aqt_clsh_flyback_dac_ctl(codec, VREF_N0P9V);
|
||||||
|
aqt_clsh_mode_vref_ctl(codec, I2C);
|
||||||
|
aqt_clsh_force_iq_ctl(codec, mode);
|
||||||
|
aqt_clsh_rdac_hd2_ctl(codec, P82_0P77, req_state);
|
||||||
|
aqt_clsh_flyback_ctrl(codec, clsh_d, mode, true);
|
||||||
|
aqt_clsh_flyback_dac_ctl(codec, VREF_N1P827V);
|
||||||
|
aqt_clsh_set_buck_mode(codec, mode);
|
||||||
|
aqt_clsh_buck_ctrl(codec, clsh_d, mode, true);
|
||||||
|
aqt_clsh_mode_vref_ctl(codec, CONTROLLER);
|
||||||
|
aqt_clsh_buck_current_bias_ctl(codec, true);
|
||||||
|
aqt_clsh_set_hph_mode(codec, mode);
|
||||||
|
} else {
|
||||||
|
aqt_clsh_set_hph_mode(codec, CLS_H_NORMAL);
|
||||||
|
aqt_clsh_buck_current_bias_ctl(codec, false);
|
||||||
|
|
||||||
|
if (mode != CLS_AB && mode != CLS_AB_HIFI) {
|
||||||
|
snd_soc_update_bits(codec,
|
||||||
|
AQT1000_CDC_RX2_RX_PATH_CFG0,
|
||||||
|
0x40, 0x00);
|
||||||
|
aqt_enable_clsh_block(codec, clsh_d, false);
|
||||||
|
}
|
||||||
|
/* buck and flyback set to default mode and disable */
|
||||||
|
aqt_clsh_buck_ctrl(codec, clsh_d, CLS_H_NORMAL, false);
|
||||||
|
aqt_clsh_flyback_ctrl(codec, clsh_d, CLS_H_NORMAL, false);
|
||||||
|
aqt_clsh_rdac_hd2_ctl(codec, P5_0P35, req_state);
|
||||||
|
aqt_clsh_force_iq_ctl(codec, CLS_H_NORMAL);
|
||||||
|
aqt_clsh_gm3_boost_disable(codec, CLS_H_NORMAL);
|
||||||
|
aqt_clsh_set_flyback_mode(codec, CLS_H_NORMAL);
|
||||||
|
aqt_clsh_set_buck_mode(codec, CLS_H_NORMAL);
|
||||||
|
aqt_clsh_set_buck_regulator_mode(codec, CLS_H_NORMAL);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void aqt_clsh_state_hph_l(struct snd_soc_codec *codec,
|
||||||
|
struct aqt_clsh_cdc_data *clsh_d,
|
||||||
|
u8 req_state, bool is_enable, int mode)
|
||||||
|
{
|
||||||
|
dev_dbg(codec->dev, "%s: mode: %s, %s\n", __func__, mode_to_str(mode),
|
||||||
|
is_enable ? "enable" : "disable");
|
||||||
|
|
||||||
|
if (mode == CLS_H_NORMAL) {
|
||||||
|
dev_err(codec->dev, "%s: Normal mode not applicable for hph_l\n",
|
||||||
|
__func__);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (is_enable) {
|
||||||
|
if (mode != CLS_AB && mode != CLS_AB_HIFI) {
|
||||||
|
aqt_enable_clsh_block(codec, clsh_d, true);
|
||||||
|
/*
|
||||||
|
* These K1 values depend on the Headphone Impedance
|
||||||
|
* For now it is assumed to be 16 ohm
|
||||||
|
*/
|
||||||
|
snd_soc_update_bits(codec, AQT1000_CDC_CLSH_K1_MSB,
|
||||||
|
0x0F, 0x00);
|
||||||
|
snd_soc_update_bits(codec, AQT1000_CDC_CLSH_K1_LSB,
|
||||||
|
0xFF, 0xC0);
|
||||||
|
snd_soc_update_bits(codec,
|
||||||
|
AQT1000_CDC_RX1_RX_PATH_CFG0,
|
||||||
|
0x40, 0x40);
|
||||||
|
}
|
||||||
|
aqt_clsh_set_buck_regulator_mode(codec, mode);
|
||||||
|
aqt_clsh_set_flyback_mode(codec, mode);
|
||||||
|
aqt_clsh_gm3_boost_disable(codec, mode);
|
||||||
|
aqt_clsh_flyback_dac_ctl(codec, VREF_N0P9V);
|
||||||
|
aqt_clsh_mode_vref_ctl(codec, I2C);
|
||||||
|
aqt_clsh_force_iq_ctl(codec, mode);
|
||||||
|
aqt_clsh_rdac_hd2_ctl(codec, P82_0P77, req_state);
|
||||||
|
aqt_clsh_flyback_ctrl(codec, clsh_d, mode, true);
|
||||||
|
aqt_clsh_flyback_dac_ctl(codec, VREF_N1P827V);
|
||||||
|
aqt_clsh_set_buck_mode(codec, mode);
|
||||||
|
aqt_clsh_buck_ctrl(codec, clsh_d, mode, true);
|
||||||
|
aqt_clsh_mode_vref_ctl(codec, CONTROLLER);
|
||||||
|
aqt_clsh_buck_current_bias_ctl(codec, true);
|
||||||
|
aqt_clsh_set_hph_mode(codec, mode);
|
||||||
|
} else {
|
||||||
|
aqt_clsh_set_hph_mode(codec, CLS_H_NORMAL);
|
||||||
|
aqt_clsh_buck_current_bias_ctl(codec, false);
|
||||||
|
|
||||||
|
if (mode != CLS_AB && mode != CLS_AB_HIFI) {
|
||||||
|
snd_soc_update_bits(codec,
|
||||||
|
AQT1000_CDC_RX1_RX_PATH_CFG0,
|
||||||
|
0x40, 0x00);
|
||||||
|
aqt_enable_clsh_block(codec, clsh_d, false);
|
||||||
|
}
|
||||||
|
/* set buck and flyback to Default Mode */
|
||||||
|
aqt_clsh_buck_ctrl(codec, clsh_d, CLS_H_NORMAL, false);
|
||||||
|
aqt_clsh_flyback_ctrl(codec, clsh_d, CLS_H_NORMAL, false);
|
||||||
|
aqt_clsh_rdac_hd2_ctl(codec, P5_0P35, req_state);
|
||||||
|
aqt_clsh_force_iq_ctl(codec, CLS_H_NORMAL);
|
||||||
|
aqt_clsh_gm3_boost_disable(codec, CLS_H_NORMAL);
|
||||||
|
aqt_clsh_set_flyback_mode(codec, CLS_H_NORMAL);
|
||||||
|
aqt_clsh_set_buck_mode(codec, CLS_H_NORMAL);
|
||||||
|
aqt_clsh_set_buck_regulator_mode(codec, CLS_H_NORMAL);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void aqt_clsh_state_err(struct snd_soc_codec *codec,
|
||||||
|
struct aqt_clsh_cdc_data *clsh_d,
|
||||||
|
u8 req_state, bool is_enable, int mode)
|
||||||
|
{
|
||||||
|
dev_err(codec->dev,
|
||||||
|
"%s Wrong request for class H state machine requested to %s %s",
|
||||||
|
__func__, is_enable ? "enable" : "disable",
|
||||||
|
state_to_str[req_state]);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Function: aqt_clsh_is_state_valid
|
||||||
|
* Params: state
|
||||||
|
* Description:
|
||||||
|
* Provides information on valid states of Class H configuration
|
||||||
|
*/
|
||||||
|
static bool aqt_clsh_is_state_valid(u8 state)
|
||||||
|
{
|
||||||
|
switch (state) {
|
||||||
|
case AQT_CLSH_STATE_IDLE:
|
||||||
|
case AQT_CLSH_STATE_HPHL:
|
||||||
|
case AQT_CLSH_STATE_HPHR:
|
||||||
|
case AQT_CLSH_STATE_HPH_ST:
|
||||||
|
return true;
|
||||||
|
default:
|
||||||
|
return false;
|
||||||
|
};
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Function: aqt_clsh_fsm
|
||||||
|
* Params: codec, cdc_clsh_d, req_state, req_type, clsh_event
|
||||||
|
* Description:
|
||||||
|
* This function handles PRE DAC and POST DAC conditions of different devices
|
||||||
|
* and updates class H configuration of different combination of devices
|
||||||
|
* based on validity of their states. cdc_clsh_d will contain current
|
||||||
|
* class h state information
|
||||||
|
*/
|
||||||
|
void aqt_clsh_fsm(struct snd_soc_codec *codec,
|
||||||
|
struct aqt_clsh_cdc_data *cdc_clsh_d,
|
||||||
|
u8 clsh_event, u8 req_state,
|
||||||
|
int int_mode)
|
||||||
|
{
|
||||||
|
u8 old_state, new_state;
|
||||||
|
|
||||||
|
switch (clsh_event) {
|
||||||
|
case AQT_CLSH_EVENT_PRE_DAC:
|
||||||
|
old_state = cdc_clsh_d->state;
|
||||||
|
new_state = old_state | req_state;
|
||||||
|
|
||||||
|
if (!aqt_clsh_is_state_valid(new_state)) {
|
||||||
|
dev_err(codec->dev,
|
||||||
|
"%s: Class-H not a valid new state: %s\n",
|
||||||
|
__func__, state_to_str[new_state]);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
if (new_state == old_state) {
|
||||||
|
dev_err(codec->dev,
|
||||||
|
"%s: Class-H already in requested state: %s\n",
|
||||||
|
__func__, state_to_str[new_state]);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
cdc_clsh_d->state = new_state;
|
||||||
|
aqt_clsh_set_int_mode(cdc_clsh_d, req_state, int_mode);
|
||||||
|
(*clsh_state_fp[new_state]) (codec, cdc_clsh_d, req_state,
|
||||||
|
CLSH_REQ_ENABLE, int_mode);
|
||||||
|
dev_dbg(codec->dev,
|
||||||
|
"%s: ClassH state transition from %s to %s\n",
|
||||||
|
__func__, state_to_str[old_state],
|
||||||
|
state_to_str[cdc_clsh_d->state]);
|
||||||
|
break;
|
||||||
|
case AQT_CLSH_EVENT_POST_PA:
|
||||||
|
old_state = cdc_clsh_d->state;
|
||||||
|
new_state = old_state & (~req_state);
|
||||||
|
if (new_state < NUM_CLSH_STATES) {
|
||||||
|
if (!aqt_clsh_is_state_valid(old_state)) {
|
||||||
|
dev_err(codec->dev,
|
||||||
|
"%s:Invalid old state:%s\n",
|
||||||
|
__func__, state_to_str[old_state]);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
if (new_state == old_state) {
|
||||||
|
dev_err(codec->dev,
|
||||||
|
"%s: Class-H already in requested state: %s\n",
|
||||||
|
__func__,state_to_str[new_state]);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
(*clsh_state_fp[old_state]) (codec, cdc_clsh_d,
|
||||||
|
req_state, CLSH_REQ_DISABLE,
|
||||||
|
int_mode);
|
||||||
|
cdc_clsh_d->state = new_state;
|
||||||
|
aqt_clsh_set_int_mode(cdc_clsh_d, req_state, CLS_NONE);
|
||||||
|
dev_dbg(codec->dev, "%s: ClassH state transition from %s to %s\n",
|
||||||
|
__func__, state_to_str[old_state],
|
||||||
|
state_to_str[cdc_clsh_d->state]);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
};
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(aqt_clsh_fsm);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Function: aqt_clsh_get_clsh_state
|
||||||
|
* Params: clsh
|
||||||
|
* Description:
|
||||||
|
* This function returns the state of the class H controller
|
||||||
|
*/
|
||||||
|
int aqt_clsh_get_clsh_state(struct aqt_clsh_cdc_data *clsh)
|
||||||
|
{
|
||||||
|
return clsh->state;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(aqt_clsh_get_clsh_state);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Function: aqt_clsh_init
|
||||||
|
* Params: clsh
|
||||||
|
* Description:
|
||||||
|
* This function initializes the class H controller
|
||||||
|
*/
|
||||||
|
void aqt_clsh_init(struct aqt_clsh_cdc_data *clsh)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
clsh->state = AQT_CLSH_STATE_IDLE;
|
||||||
|
|
||||||
|
for (i = 0; i < NUM_CLSH_STATES; i++)
|
||||||
|
clsh_state_fp[i] = aqt_clsh_state_err;
|
||||||
|
|
||||||
|
clsh_state_fp[AQT_CLSH_STATE_HPHL] = aqt_clsh_state_hph_l;
|
||||||
|
clsh_state_fp[AQT_CLSH_STATE_HPHR] = aqt_clsh_state_hph_r;
|
||||||
|
clsh_state_fp[AQT_CLSH_STATE_HPH_ST] = aqt_clsh_state_hph_st;
|
||||||
|
/* Set interpolator modes to NONE */
|
||||||
|
aqt_clsh_set_int_mode(clsh, AQT_CLSH_STATE_HPHL, CLS_NONE);
|
||||||
|
aqt_clsh_set_int_mode(clsh, AQT_CLSH_STATE_HPHR, CLS_NONE);
|
||||||
|
clsh->flyback_users = 0;
|
||||||
|
clsh->buck_users = 0;
|
||||||
|
clsh->clsh_users = 0;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(aqt_clsh_init);
|
||||||
115
asoc/codecs/aqt1000/aqt1000-clsh.h
Normal file
115
asoc/codecs/aqt1000/aqt1000-clsh.h
Normal file
@@ -0,0 +1,115 @@
|
|||||||
|
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _AQT1000_CLSH_H
|
||||||
|
#define _AQT1000_CLSH_H
|
||||||
|
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/slab.h>
|
||||||
|
#include <sound/soc.h>
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
|
||||||
|
#define CLSH_REQ_ENABLE true
|
||||||
|
#define CLSH_REQ_DISABLE false
|
||||||
|
|
||||||
|
#define AQT_CLSH_EVENT_PRE_DAC 0x01
|
||||||
|
#define AQT_CLSH_EVENT_POST_PA 0x02
|
||||||
|
/*
|
||||||
|
* Basic states for Class H state machine.
|
||||||
|
* represented as a bit mask within a u8 data type
|
||||||
|
* bit 0: HPH Left mode
|
||||||
|
* bit 1: HPH Right mode
|
||||||
|
*/
|
||||||
|
#define AQT_CLSH_STATE_IDLE 0x00
|
||||||
|
#define AQT_CLSH_STATE_HPHL (0x01 << 0)
|
||||||
|
#define AQT_CLSH_STATE_HPHR (0x01 << 1)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Though number of CLSH states are 2, max state shoulbe be 3
|
||||||
|
* because state array index starts from 1.
|
||||||
|
*/
|
||||||
|
#define AQT_CLSH_STATE_MAX 3
|
||||||
|
#define NUM_CLSH_STATES (0x01 << AQT_CLSH_STATE_MAX)
|
||||||
|
|
||||||
|
|
||||||
|
/* Derived State: Bits 1 and 2 should be set for Headphone stereo */
|
||||||
|
#define AQT_CLSH_STATE_HPH_ST (AQT_CLSH_STATE_HPHL | \
|
||||||
|
AQT_CLSH_STATE_HPHR)
|
||||||
|
|
||||||
|
enum {
|
||||||
|
CLS_H_NORMAL = 0, /* Class-H Default */
|
||||||
|
CLS_H_HIFI, /* Class-H HiFi */
|
||||||
|
CLS_H_LP, /* Class-H Low Power */
|
||||||
|
CLS_AB, /* Class-AB Low HIFI*/
|
||||||
|
CLS_H_LOHIFI, /* LoHIFI */
|
||||||
|
CLS_H_ULP, /* Ultra Low power */
|
||||||
|
CLS_AB_HIFI, /* Class-AB */
|
||||||
|
CLS_NONE, /* None of the above modes */
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
DAC_GAIN_0DB = 0,
|
||||||
|
DAC_GAIN_0P2DB,
|
||||||
|
DAC_GAIN_0P4DB,
|
||||||
|
DAC_GAIN_0P6DB,
|
||||||
|
DAC_GAIN_0P8DB,
|
||||||
|
DAC_GAIN_M0P2DB,
|
||||||
|
DAC_GAIN_M0P4DB,
|
||||||
|
DAC_GAIN_M0P6DB,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
VREF_FILT_R_0OHM = 0,
|
||||||
|
VREF_FILT_R_25KOHM,
|
||||||
|
VREF_FILT_R_50KOHM,
|
||||||
|
VREF_FILT_R_100KOHM,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
DELTA_I_0MA,
|
||||||
|
DELTA_I_10MA,
|
||||||
|
DELTA_I_20MA,
|
||||||
|
DELTA_I_30MA,
|
||||||
|
DELTA_I_40MA,
|
||||||
|
DELTA_I_50MA,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aqt_imped_val {
|
||||||
|
u32 imped_val;
|
||||||
|
u8 index;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aqt_clsh_cdc_data {
|
||||||
|
u8 state;
|
||||||
|
int flyback_users;
|
||||||
|
int buck_users;
|
||||||
|
int clsh_users;
|
||||||
|
int interpolator_modes[AQT_CLSH_STATE_MAX];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aqt_reg_mask_val {
|
||||||
|
u16 reg;
|
||||||
|
u8 mask;
|
||||||
|
u8 val;
|
||||||
|
};
|
||||||
|
|
||||||
|
extern void aqt_clsh_fsm(struct snd_soc_codec *codec,
|
||||||
|
struct aqt_clsh_cdc_data *cdc_clsh_d,
|
||||||
|
u8 clsh_event, u8 req_state,
|
||||||
|
int int_mode);
|
||||||
|
|
||||||
|
extern void aqt_clsh_init(struct aqt_clsh_cdc_data *clsh);
|
||||||
|
extern int aqt_clsh_get_clsh_state(struct aqt_clsh_cdc_data *clsh);
|
||||||
|
extern void aqt_clsh_imped_config(struct snd_soc_codec *codec, int imped,
|
||||||
|
bool reset);
|
||||||
|
|
||||||
|
#endif /* _AQT1000_CLSH_H */
|
||||||
589
asoc/codecs/aqt1000/aqt1000-core.c
Normal file
589
asoc/codecs/aqt1000/aqt1000-core.c
Normal file
@@ -0,0 +1,589 @@
|
|||||||
|
/* Copyright (c) 2011-2018, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/of_device.h>
|
||||||
|
#include <linux/slab.h>
|
||||||
|
#include <linux/ratelimit.h>
|
||||||
|
#include <linux/mfd/core.h>
|
||||||
|
#include <linux/delay.h>
|
||||||
|
#include <linux/gpio.h>
|
||||||
|
#include <linux/debugfs.h>
|
||||||
|
#include <linux/i2c.h>
|
||||||
|
#include <linux/regmap.h>
|
||||||
|
#include <sound/soc.h>
|
||||||
|
#include "../msm-cdc-pinctrl.h"
|
||||||
|
#include "../msm-cdc-supply.h"
|
||||||
|
#include "aqt1000-registers.h"
|
||||||
|
#include "aqt1000-internal.h"
|
||||||
|
#include "aqt1000.h"
|
||||||
|
#include "aqt1000-utils.h"
|
||||||
|
|
||||||
|
static int aqt1000_bringup(struct aqt1000 *aqt)
|
||||||
|
{
|
||||||
|
struct aqt1000_pdata *pdata;
|
||||||
|
u8 clk_div = 0, mclk = 1;
|
||||||
|
|
||||||
|
if (!aqt->regmap) {
|
||||||
|
dev_err(aqt->dev, "%s: aqt regmap is NULL\n", __func__);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Bringup register write sequence */
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_BUCK_5V_CTRL_CCL_1, 0xF0, 0xF0);
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_BIAS_CCOMP_FINE_ADJ,
|
||||||
|
0xF0, 0x90);
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_ANA_BIAS, 0x80, 0x80);
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_ANA_BIAS, 0x40, 0x40);
|
||||||
|
|
||||||
|
/* Added 1msec sleep as per HW requirement */
|
||||||
|
usleep_range(1000, 1010);
|
||||||
|
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_ANA_BIAS, 0x40, 0x00);
|
||||||
|
|
||||||
|
clk_div = 0x04; /* Assumption is CLK DIV 2 */
|
||||||
|
pdata = dev_get_platdata(aqt->dev);
|
||||||
|
if (pdata) {
|
||||||
|
if (pdata->mclk_rate == AQT1000_CLK_12P288MHZ)
|
||||||
|
mclk = 0;
|
||||||
|
clk_div = (((pdata->ext_clk_rate / pdata->mclk_rate) >> 1)
|
||||||
|
<< 2);
|
||||||
|
}
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_CHIP_CFG0_CLK_CFG_MCLK,
|
||||||
|
0x03, mclk);
|
||||||
|
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_CLK_SYS_MCLK1_PRG,
|
||||||
|
0x0C, clk_div);
|
||||||
|
|
||||||
|
/* Source clock enable */
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_CLK_SYS_MCLK1_PRG, 0x02, 0x02);
|
||||||
|
|
||||||
|
/* Ungate the source clock */
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_CLK_SYS_MCLK1_PRG, 0x10, 0x10);
|
||||||
|
|
||||||
|
/* Set the I2S_HS_CLK reference to CLK DIV 2 */
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_CLK_SYS_MCLK2_I2S_HS_CLK_PRG,
|
||||||
|
0x60, 0x20);
|
||||||
|
|
||||||
|
/* Set the PLL preset to CLK9P6M_IN_12P288M_OUT */
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_CLK_SYS_PLL_PRESET, 0x0F, 0x02);
|
||||||
|
|
||||||
|
/* Enable clock PLL */
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_CLK_SYS_PLL_ENABLES,
|
||||||
|
0x01, 0x01);
|
||||||
|
|
||||||
|
/* Add 100usec delay as per HW requirement */
|
||||||
|
usleep_range(100, 110);
|
||||||
|
|
||||||
|
/* Set AQT to I2S Master */
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_I2S_I2S_0_CTL, 0x02, 0x02);
|
||||||
|
|
||||||
|
/* Enable I2S HS clock */
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_CLK_SYS_MCLK2_I2S_HS_CLK_PRG,
|
||||||
|
0x01, 0x01);
|
||||||
|
|
||||||
|
/* Codec digital reset */
|
||||||
|
regmap_update_bits(aqt->regmap, AQT1000_CHIP_CFG0_RST_CTL, 0x01, 0x01);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int aqt1000_device_init(struct aqt1000 *aqt)
|
||||||
|
{
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
mutex_init(&aqt->io_lock);
|
||||||
|
mutex_init(&aqt->xfer_lock);
|
||||||
|
mutex_init(&aqt->cdc_bg_clk_lock);
|
||||||
|
mutex_init(&aqt->master_bias_lock);
|
||||||
|
|
||||||
|
ret = aqt1000_bringup(aqt);
|
||||||
|
if (ret) {
|
||||||
|
ret = -EPROBE_DEFER;
|
||||||
|
goto done;
|
||||||
|
}
|
||||||
|
|
||||||
|
done:
|
||||||
|
mutex_destroy(&aqt->io_lock);
|
||||||
|
mutex_destroy(&aqt->xfer_lock);
|
||||||
|
mutex_destroy(&aqt->cdc_bg_clk_lock);
|
||||||
|
mutex_destroy(&aqt->master_bias_lock);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int aqt1000_i2c_write(struct aqt1000 *aqt1000, unsigned short reg,
|
||||||
|
void *val, int bytes)
|
||||||
|
{
|
||||||
|
struct i2c_msg *msg;
|
||||||
|
int ret = 0;
|
||||||
|
u8 reg_addr = 0;
|
||||||
|
u8 data[bytes + 1];
|
||||||
|
struct aqt1000_i2c *aqt1000_i2c;
|
||||||
|
u8 *value = (u8 *)val;
|
||||||
|
|
||||||
|
aqt1000_i2c = &aqt1000->i2c_dev;
|
||||||
|
if (aqt1000_i2c == NULL || aqt1000_i2c->client == NULL) {
|
||||||
|
pr_err("%s: Failed to get device info\n", __func__);
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
reg_addr = (u8)reg;
|
||||||
|
msg = &aqt1000_i2c->xfer_msg[0];
|
||||||
|
msg->addr = aqt1000_i2c->client->addr;
|
||||||
|
msg->len = bytes + 1;
|
||||||
|
msg->flags = 0;
|
||||||
|
data[0] = reg;
|
||||||
|
data[1] = *value;
|
||||||
|
msg->buf = data;
|
||||||
|
ret = i2c_transfer(aqt1000_i2c->client->adapter,
|
||||||
|
aqt1000_i2c->xfer_msg, 1);
|
||||||
|
/* Try again if the write fails */
|
||||||
|
if (ret != 1) {
|
||||||
|
ret = i2c_transfer(aqt1000_i2c->client->adapter,
|
||||||
|
aqt1000_i2c->xfer_msg, 1);
|
||||||
|
if (ret != 1) {
|
||||||
|
dev_err(aqt1000->dev,
|
||||||
|
"%s: I2C write failed, reg: 0x%x ret: %d\n",
|
||||||
|
__func__, reg, ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
dev_dbg(aqt1000->dev, "%s: write success register = %x val = %x\n",
|
||||||
|
__func__, reg, data[1]);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int aqt1000_i2c_read(struct aqt1000 *aqt1000, unsigned short reg,
|
||||||
|
void *dst, int bytes)
|
||||||
|
{
|
||||||
|
struct i2c_msg *msg;
|
||||||
|
int ret = 0;
|
||||||
|
u8 reg_addr = 0;
|
||||||
|
struct aqt1000_i2c *aqt1000_i2c;
|
||||||
|
u8 i = 0;
|
||||||
|
unsigned char *dest = (unsigned char *)dst;
|
||||||
|
|
||||||
|
aqt1000_i2c = &aqt1000->i2c_dev;
|
||||||
|
if (aqt1000_i2c == NULL || aqt1000_i2c->client == NULL) {
|
||||||
|
pr_err("%s: Failed to get device info\n", __func__);
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
for (i = 0; i < bytes; i++) {
|
||||||
|
reg_addr = (u8)reg++;
|
||||||
|
msg = &aqt1000_i2c->xfer_msg[0];
|
||||||
|
msg->addr = aqt1000_i2c->client->addr;
|
||||||
|
msg->len = 1;
|
||||||
|
msg->flags = 0;
|
||||||
|
msg->buf = ®_addr;
|
||||||
|
|
||||||
|
msg = &aqt1000_i2c->xfer_msg[1];
|
||||||
|
msg->addr = aqt1000_i2c->client->addr;
|
||||||
|
msg->len = 1;
|
||||||
|
msg->flags = I2C_M_RD;
|
||||||
|
msg->buf = dest++;
|
||||||
|
ret = i2c_transfer(aqt1000_i2c->client->adapter,
|
||||||
|
aqt1000_i2c->xfer_msg, 2);
|
||||||
|
|
||||||
|
/* Try again if read fails first time */
|
||||||
|
if (ret != 2) {
|
||||||
|
ret = i2c_transfer(aqt1000_i2c->client->adapter,
|
||||||
|
aqt1000_i2c->xfer_msg, 2);
|
||||||
|
if (ret != 2) {
|
||||||
|
dev_err(aqt1000->dev,
|
||||||
|
"%s: I2C read failed, reg: 0x%x\n",
|
||||||
|
__func__, reg);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int aqt1000_reset(struct device *dev)
|
||||||
|
{
|
||||||
|
struct aqt1000 *aqt1000;
|
||||||
|
int rc = 0;
|
||||||
|
|
||||||
|
if (!dev)
|
||||||
|
return -ENODEV;
|
||||||
|
|
||||||
|
aqt1000 = dev_get_drvdata(dev);
|
||||||
|
if (!aqt1000)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
if (!aqt1000->aqt_rst_np) {
|
||||||
|
dev_err(dev, "%s: reset gpio device node not specified\n",
|
||||||
|
__func__);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!msm_cdc_pinctrl_get_state(aqt1000->aqt_rst_np)) {
|
||||||
|
rc = msm_cdc_pinctrl_select_sleep_state(aqt1000->aqt_rst_np);
|
||||||
|
if (rc) {
|
||||||
|
dev_err(dev, "%s: aqt sleep state request fail!\n",
|
||||||
|
__func__);
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* 20ms sleep required after pulling the reset gpio to LOW */
|
||||||
|
msleep(20);
|
||||||
|
|
||||||
|
rc = msm_cdc_pinctrl_select_active_state(aqt1000->aqt_rst_np);
|
||||||
|
if (rc) {
|
||||||
|
dev_err(dev,
|
||||||
|
"%s: aqt active state request fail, ret: %d\n",
|
||||||
|
__func__, rc);
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
/* 20ms sleep required after pulling the reset gpio to HIGH */
|
||||||
|
msleep(20);
|
||||||
|
}
|
||||||
|
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int aqt1000_read_of_property_u32(struct device *dev, const char *name,
|
||||||
|
u32 *val)
|
||||||
|
{
|
||||||
|
int rc = 0;
|
||||||
|
|
||||||
|
rc = of_property_read_u32(dev->of_node, name, val);
|
||||||
|
if (rc)
|
||||||
|
dev_err(dev, "%s: Looking up %s property in node %s failed",
|
||||||
|
__func__, name, dev->of_node->full_name);
|
||||||
|
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void aqt1000_dt_parse_micbias_info(struct device *dev,
|
||||||
|
struct aqt1000_micbias_setting *mb)
|
||||||
|
{
|
||||||
|
u32 prop_val;
|
||||||
|
int rc;
|
||||||
|
|
||||||
|
if (of_find_property(dev->of_node, "qcom,cdc-micbias-ldoh-v", NULL)) {
|
||||||
|
rc = aqt1000_read_of_property_u32(dev,
|
||||||
|
"qcom,cdc-micbias-ldoh-v",
|
||||||
|
&prop_val);
|
||||||
|
if (!rc)
|
||||||
|
mb->ldoh_v = (u8)prop_val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* MB1 */
|
||||||
|
if (of_find_property(dev->of_node, "qcom,cdc-micbias-cfilt1-mv",
|
||||||
|
NULL)) {
|
||||||
|
rc = aqt1000_read_of_property_u32(dev,
|
||||||
|
"qcom,cdc-micbias-cfilt1-mv",
|
||||||
|
&prop_val);
|
||||||
|
if (!rc)
|
||||||
|
mb->cfilt1_mv = prop_val;
|
||||||
|
|
||||||
|
rc = aqt1000_read_of_property_u32(dev,
|
||||||
|
"qcom,cdc-micbias1-cfilt-sel",
|
||||||
|
&prop_val);
|
||||||
|
if (!rc)
|
||||||
|
mb->bias1_cfilt_sel = (u8)prop_val;
|
||||||
|
|
||||||
|
} else if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
|
||||||
|
NULL)) {
|
||||||
|
rc = aqt1000_read_of_property_u32(dev,
|
||||||
|
"qcom,cdc-micbias1-mv",
|
||||||
|
&prop_val);
|
||||||
|
if (!rc)
|
||||||
|
mb->micb1_mv = prop_val;
|
||||||
|
} else {
|
||||||
|
dev_info(dev, "%s: Micbias1 DT property not found\n",
|
||||||
|
__func__);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Print micbias info */
|
||||||
|
dev_dbg(dev, "%s: ldoh_v %u cfilt1_mv %u micb1_mv %u \n", __func__,
|
||||||
|
(u32)mb->ldoh_v, (u32)mb->cfilt1_mv, (u32)mb->micb1_mv);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct aqt1000_pdata *aqt1000_populate_dt_data(struct device *dev)
|
||||||
|
{
|
||||||
|
struct aqt1000_pdata *pdata;
|
||||||
|
u32 prop_val;
|
||||||
|
|
||||||
|
if (!dev || !dev->of_node)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
pdata = devm_kzalloc(dev, sizeof(struct aqt1000_pdata),
|
||||||
|
GFP_KERNEL);
|
||||||
|
if (!pdata)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
/* Parse power supplies */
|
||||||
|
msm_cdc_get_power_supplies(dev, &pdata->regulator,
|
||||||
|
&pdata->num_supplies);
|
||||||
|
if (!pdata->regulator || (pdata->num_supplies <= 0)) {
|
||||||
|
dev_err(dev, "%s: no power supplies defined for codec\n",
|
||||||
|
__func__);
|
||||||
|
goto err_power_sup;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Parse micbias info */
|
||||||
|
aqt1000_dt_parse_micbias_info(dev, &pdata->micbias);
|
||||||
|
|
||||||
|
pdata->aqt_rst_np = of_parse_phandle(dev->of_node,
|
||||||
|
"qcom,aqt-rst-gpio-node", 0);
|
||||||
|
if (!pdata->aqt_rst_np) {
|
||||||
|
dev_err(dev, "%s: Looking up %s property in node %s failed\n",
|
||||||
|
__func__, "qcom,aqt-rst-gpio-node",
|
||||||
|
dev->of_node->full_name);
|
||||||
|
goto err_parse_dt_prop;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!(aqt1000_read_of_property_u32(dev, "qcom,cdc-ext-clk-rate",
|
||||||
|
&prop_val)))
|
||||||
|
pdata->ext_clk_rate = prop_val;
|
||||||
|
if (pdata->ext_clk_rate != AQT1000_CLK_24P576MHZ &&
|
||||||
|
pdata->ext_clk_rate != AQT1000_CLK_19P2MHZ &&
|
||||||
|
pdata->ext_clk_rate != AQT1000_CLK_12P288MHZ) {
|
||||||
|
/* Use the default ext_clk_rate if the DT value is wrong */
|
||||||
|
pdata->ext_clk_rate = AQT1000_CLK_9P6MHZ;
|
||||||
|
}
|
||||||
|
|
||||||
|
prop_val = 0;
|
||||||
|
if (!(aqt1000_read_of_property_u32(dev, "qcom,cdc-mclk-clk-rate",
|
||||||
|
&prop_val)))
|
||||||
|
pdata->mclk_rate = prop_val;
|
||||||
|
|
||||||
|
if (pdata->mclk_rate != AQT1000_CLK_9P6MHZ &&
|
||||||
|
pdata->mclk_rate != AQT1000_CLK_12P288MHZ) {
|
||||||
|
dev_err(dev, "%s: Invalid mclk_rate = %u\n", __func__,
|
||||||
|
pdata->mclk_rate);
|
||||||
|
goto err_parse_dt_prop;
|
||||||
|
}
|
||||||
|
if (pdata->ext_clk_rate % pdata->mclk_rate) {
|
||||||
|
dev_err(dev,
|
||||||
|
"%s: Invalid clock group, ext_clk = %d mclk = %d\n",
|
||||||
|
__func__, pdata->ext_clk_rate, pdata->mclk_rate);
|
||||||
|
goto err_parse_dt_prop;
|
||||||
|
}
|
||||||
|
|
||||||
|
return pdata;
|
||||||
|
|
||||||
|
err_parse_dt_prop:
|
||||||
|
devm_kfree(dev, pdata->regulator);
|
||||||
|
pdata->regulator = NULL;
|
||||||
|
pdata->num_supplies = 0;
|
||||||
|
err_power_sup:
|
||||||
|
devm_kfree(dev, pdata);
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int aqt1000_bringdown(struct device *dev)
|
||||||
|
{
|
||||||
|
/* No sequence for teardown */
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void aqt1000_device_exit(struct aqt1000 *aqt)
|
||||||
|
{
|
||||||
|
aqt1000_bringdown(aqt->dev);
|
||||||
|
mutex_destroy(&aqt->io_lock);
|
||||||
|
mutex_destroy(&aqt->xfer_lock);
|
||||||
|
mutex_destroy(&aqt->cdc_bg_clk_lock);
|
||||||
|
mutex_destroy(&aqt->master_bias_lock);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int aqt1000_i2c_probe(struct i2c_client *client,
|
||||||
|
const struct i2c_device_id *id)
|
||||||
|
{
|
||||||
|
struct aqt1000 *aqt1000 = NULL;
|
||||||
|
struct aqt1000_pdata *pdata = NULL;
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
pdata = aqt1000_populate_dt_data(&client->dev);
|
||||||
|
if (!pdata) {
|
||||||
|
dev_err(&client->dev,
|
||||||
|
"%s: Fail to obtain pdata from device tree\n",
|
||||||
|
__func__);
|
||||||
|
ret = -EINVAL;
|
||||||
|
goto fail;
|
||||||
|
}
|
||||||
|
client->dev.platform_data = pdata;
|
||||||
|
|
||||||
|
aqt1000 = devm_kzalloc(&client->dev, sizeof(struct aqt1000),
|
||||||
|
GFP_KERNEL);
|
||||||
|
if (!aqt1000) {
|
||||||
|
ret = -ENOMEM;
|
||||||
|
goto fail;
|
||||||
|
}
|
||||||
|
|
||||||
|
aqt1000->regmap = aqt1000_regmap_init(&client->dev,
|
||||||
|
&aqt1000_regmap_config);
|
||||||
|
if (IS_ERR(aqt1000->regmap)) {
|
||||||
|
ret = PTR_ERR(aqt1000->regmap);
|
||||||
|
dev_err(&client->dev,
|
||||||
|
"%s: Failed to init register map: %d\n",
|
||||||
|
__func__, ret);
|
||||||
|
goto fail;
|
||||||
|
}
|
||||||
|
aqt1000->aqt_rst_np = pdata->aqt_rst_np;
|
||||||
|
if (!aqt1000->aqt_rst_np) {
|
||||||
|
dev_err(&client->dev, "%s: pinctrl not used for rst_n\n",
|
||||||
|
__func__);
|
||||||
|
ret = -EINVAL;
|
||||||
|
goto fail;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (i2c_check_functionality(client->adapter,
|
||||||
|
I2C_FUNC_I2C) == 0) {
|
||||||
|
dev_dbg(&client->dev, "%s: can't talk I2C?\n", __func__);
|
||||||
|
ret = -EIO;
|
||||||
|
goto fail;
|
||||||
|
}
|
||||||
|
dev_set_drvdata(&client->dev, aqt1000);
|
||||||
|
aqt1000->dev = &client->dev;
|
||||||
|
aqt1000->dev_up = true;
|
||||||
|
aqt1000->mclk_rate = pdata->mclk_rate;
|
||||||
|
|
||||||
|
aqt1000->num_of_supplies = pdata->num_supplies;
|
||||||
|
ret = msm_cdc_init_supplies(aqt1000->dev, &aqt1000->supplies,
|
||||||
|
pdata->regulator,
|
||||||
|
pdata->num_supplies);
|
||||||
|
if (!aqt1000->supplies) {
|
||||||
|
dev_err(aqt1000->dev, "%s: Cannot init aqt supplies\n",
|
||||||
|
__func__);
|
||||||
|
goto err_codec;
|
||||||
|
}
|
||||||
|
ret = msm_cdc_enable_static_supplies(aqt1000->dev,
|
||||||
|
aqt1000->supplies,
|
||||||
|
pdata->regulator,
|
||||||
|
pdata->num_supplies);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(aqt1000->dev, "%s: aqt static supply enable failed!\n",
|
||||||
|
__func__);
|
||||||
|
goto err_codec;
|
||||||
|
}
|
||||||
|
/* 5 usec sleep is needed as per HW requirement */
|
||||||
|
usleep_range(5, 10);
|
||||||
|
|
||||||
|
ret = aqt1000_reset(aqt1000->dev);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(aqt1000->dev, "%s: Codec reset failed\n", __func__);
|
||||||
|
goto err_supplies;
|
||||||
|
}
|
||||||
|
|
||||||
|
aqt1000->i2c_dev.client = client;
|
||||||
|
aqt1000->read_dev = aqt1000_i2c_read;
|
||||||
|
aqt1000->write_dev = aqt1000_i2c_write;
|
||||||
|
|
||||||
|
ret = aqt1000_device_init(aqt1000);
|
||||||
|
if (ret) {
|
||||||
|
pr_err("%s: error, initializing device failed (%d)\n",
|
||||||
|
__func__, ret);
|
||||||
|
goto err_supplies;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = aqt_register_codec(&client->dev);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(aqt1000->dev, "%s: Codec registration failed\n",
|
||||||
|
__func__);
|
||||||
|
goto err_cdc_register;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
err_cdc_register:
|
||||||
|
aqt1000_device_exit(aqt1000);
|
||||||
|
err_supplies:
|
||||||
|
msm_cdc_release_supplies(aqt1000->dev, aqt1000->supplies,
|
||||||
|
pdata->regulator,
|
||||||
|
pdata->num_supplies);
|
||||||
|
pdata->regulator = NULL;
|
||||||
|
pdata->num_supplies = 0;
|
||||||
|
err_codec:
|
||||||
|
devm_kfree(&client->dev, aqt1000);
|
||||||
|
dev_set_drvdata(&client->dev, NULL);
|
||||||
|
fail:
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int aqt1000_i2c_remove(struct i2c_client *client)
|
||||||
|
{
|
||||||
|
struct aqt1000 *aqt;
|
||||||
|
struct aqt1000_pdata *pdata = client->dev.platform_data;
|
||||||
|
|
||||||
|
aqt = dev_get_drvdata(&client->dev);
|
||||||
|
|
||||||
|
msm_cdc_release_supplies(aqt->dev, aqt->supplies,
|
||||||
|
pdata->regulator,
|
||||||
|
pdata->num_supplies);
|
||||||
|
aqt1000_device_exit(aqt);
|
||||||
|
dev_set_drvdata(&client->dev, NULL);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_PM_SLEEP
|
||||||
|
static int aqt1000_i2c_resume(struct device *dev)
|
||||||
|
{
|
||||||
|
pr_debug("%s system resume\n", __func__);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int aqt1000_i2c_suspend(struct device *dev)
|
||||||
|
{
|
||||||
|
pr_debug("%s system suspend\n", __func__);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static struct i2c_device_id aqt1000_id_table[] = {
|
||||||
|
{"aqt1000-i2c", 0},
|
||||||
|
{}
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(i2c, aqt1000_id_table);
|
||||||
|
|
||||||
|
static const struct dev_pm_ops aqt1000_i2c_pm_ops = {
|
||||||
|
.suspend = aqt1000_i2c_suspend,
|
||||||
|
.resume = aqt1000_i2c_resume,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct of_device_id aqt_match_table[] = {
|
||||||
|
{.compatible = "qcom,aqt1000-i2c-codec"},
|
||||||
|
{}
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, aqt_match_table);
|
||||||
|
|
||||||
|
static struct i2c_driver aqt1000_i2c_driver = {
|
||||||
|
.driver = {
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
.name = "aqt1000-i2c-codec",
|
||||||
|
#ifdef CONFIG_PM_SLEEP
|
||||||
|
.pm = &aqt1000_i2c_pm_ops,
|
||||||
|
#endif
|
||||||
|
.of_match_table = aqt_match_table,
|
||||||
|
},
|
||||||
|
.id_table = aqt1000_id_table,
|
||||||
|
.probe = aqt1000_i2c_probe,
|
||||||
|
.remove = aqt1000_i2c_remove,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init aqt1000_init(void)
|
||||||
|
{
|
||||||
|
return i2c_add_driver(&aqt1000_i2c_driver);
|
||||||
|
}
|
||||||
|
module_init(aqt1000_init);
|
||||||
|
|
||||||
|
static void __exit aqt1000_exit(void)
|
||||||
|
{
|
||||||
|
i2c_del_driver(&aqt1000_i2c_driver);
|
||||||
|
}
|
||||||
|
module_exit(aqt1000_exit);
|
||||||
|
|
||||||
|
MODULE_DESCRIPTION("AQT1000 Codec driver");
|
||||||
|
MODULE_LICENSE("GPL v2");
|
||||||
181
asoc/codecs/aqt1000/aqt1000-internal.h
Normal file
181
asoc/codecs/aqt1000/aqt1000-internal.h
Normal file
@@ -0,0 +1,181 @@
|
|||||||
|
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _AQT1000_INTERNAL_H
|
||||||
|
#define _AQT1000_INTERNAL_H
|
||||||
|
|
||||||
|
#include <linux/types.h>
|
||||||
|
#include <linux/regmap.h>
|
||||||
|
#include <sound/soc.h>
|
||||||
|
|
||||||
|
#define AQT1000_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
|
||||||
|
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
|
||||||
|
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
|
||||||
|
SNDRV_PCM_RATE_384000)
|
||||||
|
/* Fractional Rates */
|
||||||
|
#define AQT1000_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
|
||||||
|
SNDRV_PCM_RATE_176400)
|
||||||
|
|
||||||
|
#define AQT1000_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
|
||||||
|
SNDRV_PCM_FMTBIT_S24_LE)
|
||||||
|
|
||||||
|
#define AQT1000_FORMATS_S16_S24_S32_LE (SNDRV_PCM_FMTBIT_S16_LE | \
|
||||||
|
SNDRV_PCM_FMTBIT_S24_LE | \
|
||||||
|
SNDRV_PCM_FMTBIT_S32_LE)
|
||||||
|
|
||||||
|
#define AQT1000_FORMATS_S16_LE (SNDRV_PCM_FMTBIT_S16_LE)
|
||||||
|
|
||||||
|
/* Macros for packing register writes into a U32 */
|
||||||
|
#define AQT1000_PACKED_REG_SIZE sizeof(u32)
|
||||||
|
#define AQT1000_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \
|
||||||
|
do { \
|
||||||
|
((reg) = ((packed >> 16) & (0xffff))); \
|
||||||
|
((mask) = ((packed >> 8) & (0xff))); \
|
||||||
|
((val) = ((packed) & (0xff))); \
|
||||||
|
} while (0)
|
||||||
|
|
||||||
|
#define STRING(name) #name
|
||||||
|
#define AQT_DAPM_ENUM(name, reg, offset, text) \
|
||||||
|
static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \
|
||||||
|
static const struct snd_kcontrol_new name##_mux = \
|
||||||
|
SOC_DAPM_ENUM(STRING(name), name##_enum)
|
||||||
|
|
||||||
|
#define AQT_DAPM_ENUM_EXT(name, reg, offset, text, getname, putname) \
|
||||||
|
static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \
|
||||||
|
static const struct snd_kcontrol_new name##_mux = \
|
||||||
|
SOC_DAPM_ENUM_EXT(STRING(name), name##_enum, getname, putname)
|
||||||
|
|
||||||
|
#define AQT_DAPM_MUX(name, shift, kctl) \
|
||||||
|
SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, shift, 0, &kctl##_mux)
|
||||||
|
|
||||||
|
|
||||||
|
#define AQT1000_INTERP_MUX_NUM_INPUTS 3
|
||||||
|
#define AQT1000_RX_PATH_CTL_OFFSET 20
|
||||||
|
|
||||||
|
#define BYTE_BIT_MASK(nr) (1 << ((nr) % BITS_PER_BYTE))
|
||||||
|
|
||||||
|
#define AQT1000_REG_BITS 8
|
||||||
|
#define AQT1000_MAX_VALID_ADC_MUX 3
|
||||||
|
|
||||||
|
#define AQT1000_AMIC_PWR_LEVEL_LP 0
|
||||||
|
#define AQT1000_AMIC_PWR_LEVEL_DEFAULT 1
|
||||||
|
#define AQT1000_AMIC_PWR_LEVEL_HP 2
|
||||||
|
#define AQT1000_AMIC_PWR_LVL_MASK 0x60
|
||||||
|
#define AQT1000_AMIC_PWR_LVL_SHIFT 0x5
|
||||||
|
|
||||||
|
#define AQT1000_DEC_PWR_LVL_MASK 0x06
|
||||||
|
#define AQT1000_DEC_PWR_LVL_DF 0x00
|
||||||
|
#define AQT1000_DEC_PWR_LVL_LP 0x02
|
||||||
|
#define AQT1000_DEC_PWR_LVL_HP 0x04
|
||||||
|
#define AQT1000_STRING_LEN 100
|
||||||
|
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR_COEFF_MAX 5
|
||||||
|
|
||||||
|
#define AQT1000_MAX_MICBIAS 1
|
||||||
|
#define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
|
||||||
|
|
||||||
|
#define TX_HPF_CUT_OFF_FREQ_MASK 0x60
|
||||||
|
#define CF_MIN_3DB_4HZ 0x0
|
||||||
|
#define CF_MIN_3DB_75HZ 0x1
|
||||||
|
#define CF_MIN_3DB_150HZ 0x2
|
||||||
|
|
||||||
|
enum {
|
||||||
|
AUDIO_NOMINAL,
|
||||||
|
HPH_PA_DELAY,
|
||||||
|
CLSH_Z_CONFIG,
|
||||||
|
ANC_MIC_AMIC1,
|
||||||
|
ANC_MIC_AMIC2,
|
||||||
|
ANC_MIC_AMIC3,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
MIC_BIAS_1 = 1,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
MICB_PULLUP_ENABLE,
|
||||||
|
MICB_PULLUP_DISABLE,
|
||||||
|
MICB_ENABLE,
|
||||||
|
MICB_DISABLE,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
INTn_1_INP_SEL_ZERO = 0,
|
||||||
|
INTn_1_INP_SEL_DEC0,
|
||||||
|
INTn_1_INP_SEL_DEC1,
|
||||||
|
INTn_1_INP_SEL_IIR0,
|
||||||
|
INTn_1_INP_SEL_IIR1,
|
||||||
|
INTn_1_INP_SEL_RX0,
|
||||||
|
INTn_1_INP_SEL_RX1,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
INTn_2_INP_SEL_ZERO = 0,
|
||||||
|
INTn_2_INP_SEL_RX0,
|
||||||
|
INTn_2_INP_SEL_RX1,
|
||||||
|
INTn_2_INP_SEL_PROXIMITY,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Codec supports 2 IIR filters */
|
||||||
|
enum {
|
||||||
|
IIR0 = 0,
|
||||||
|
IIR1,
|
||||||
|
IIR_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
ASRC_IN_HPHL,
|
||||||
|
ASRC_IN_HPHR,
|
||||||
|
ASRC_INVALID,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
CONV_88P2K_TO_384K,
|
||||||
|
CONV_96K_TO_352P8K,
|
||||||
|
CONV_352P8K_TO_384K,
|
||||||
|
CONV_384K_TO_352P8K,
|
||||||
|
CONV_384K_TO_384K,
|
||||||
|
CONV_96K_TO_384K,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum aqt_notify_event {
|
||||||
|
AQT_EVENT_INVALID,
|
||||||
|
/* events for micbias ON and OFF */
|
||||||
|
AQT_EVENT_PRE_MICBIAS_1_OFF,
|
||||||
|
AQT_EVENT_POST_MICBIAS_1_OFF,
|
||||||
|
AQT_EVENT_PRE_MICBIAS_1_ON,
|
||||||
|
AQT_EVENT_POST_MICBIAS_1_ON,
|
||||||
|
AQT_EVENT_PRE_DAPM_MICBIAS_1_OFF,
|
||||||
|
AQT_EVENT_POST_DAPM_MICBIAS_1_OFF,
|
||||||
|
AQT_EVENT_PRE_DAPM_MICBIAS_1_ON,
|
||||||
|
AQT_EVENT_POST_DAPM_MICBIAS_1_ON,
|
||||||
|
/* events for PA ON and OFF */
|
||||||
|
AQT_EVENT_PRE_HPHL_PA_ON,
|
||||||
|
AQT_EVENT_POST_HPHL_PA_OFF,
|
||||||
|
AQT_EVENT_PRE_HPHR_PA_ON,
|
||||||
|
AQT_EVENT_POST_HPHR_PA_OFF,
|
||||||
|
AQT_EVENT_PRE_HPHL_PA_OFF,
|
||||||
|
AQT_EVENT_PRE_HPHR_PA_OFF,
|
||||||
|
AQT_EVENT_OCP_OFF,
|
||||||
|
AQT_EVENT_OCP_ON,
|
||||||
|
AQT_EVENT_LAST,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct interp_sample_rate {
|
||||||
|
int sample_rate;
|
||||||
|
int rate_val;
|
||||||
|
};
|
||||||
|
|
||||||
|
extern struct regmap_config aqt1000_regmap_config;
|
||||||
|
extern int aqt_register_codec(struct device *dev);
|
||||||
|
|
||||||
|
#endif /* _AQT1000_INTERNAL_H */
|
||||||
185
asoc/codecs/aqt1000/aqt1000-irq.c
Normal file
185
asoc/codecs/aqt1000/aqt1000-irq.c
Normal file
@@ -0,0 +1,185 @@
|
|||||||
|
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/sched.h>
|
||||||
|
#include <linux/irq.h>
|
||||||
|
#include <linux/delay.h>
|
||||||
|
#include <linux/of.h>
|
||||||
|
#include <linux/of_irq.h>
|
||||||
|
#include <linux/slab.h>
|
||||||
|
#include <linux/ratelimit.h>
|
||||||
|
#include <linux/irqdomain.h>
|
||||||
|
#include <linux/regmap.h>
|
||||||
|
|
||||||
|
#include "aqt1000-registers.h"
|
||||||
|
#include "aqt1000-irq.h"
|
||||||
|
|
||||||
|
|
||||||
|
static int aqt_irq_init(struct aqt1000_irq *aqt_irq)
|
||||||
|
{
|
||||||
|
int i, ret;
|
||||||
|
|
||||||
|
if (aqt_irq == NULL) {
|
||||||
|
pr_err("%s: aqt_irq is NULL\n", __func__);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
mutex_init(&aqt_irq->irq_lock);
|
||||||
|
mutex_init(&aqt_irq->nested_irq_lock);
|
||||||
|
|
||||||
|
aqt_irq->irq = aqt_irq_get_upstream_irq(aqt_irq);
|
||||||
|
if (!aqt_irq->irq) {
|
||||||
|
pr_warn("%s: irq driver is not yet initialized\n", __func__);
|
||||||
|
mutex_destroy(&aqt_irq->irq_lock);
|
||||||
|
mutex_destroy(&aqt_irq->nested_irq_lock);
|
||||||
|
return -EPROBE_DEFER;
|
||||||
|
}
|
||||||
|
pr_debug("%s: probed irq %d\n", __func__, aqt_irq->irq);
|
||||||
|
|
||||||
|
/* Setup downstream IRQs */
|
||||||
|
ret = aqt_irq_setup_downstream_irq(aqt_irq);
|
||||||
|
if (ret) {
|
||||||
|
pr_err("%s: Failed to setup downstream IRQ\n", __func__);
|
||||||
|
goto fail_irq_init;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* mask all the interrupts */
|
||||||
|
for (i = 0; i < aqt_irq->num_irqs; i++) {
|
||||||
|
aqt_irq->irq_masks_cur |= BYTE_BIT_MASK(i);
|
||||||
|
aqt_irq->irq_masks_cache |= BYTE_BIT_MASK(i);
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = request_threaded_irq(aqt_irq->irq, NULL, aqt_irq_thread,
|
||||||
|
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
|
||||||
|
"aqt", aqt_irq);
|
||||||
|
if (ret != 0) {
|
||||||
|
dev_err(aqt_irq->dev, "Failed to request IRQ %d: %d\n",
|
||||||
|
aqt_irq->irq, ret);
|
||||||
|
} else {
|
||||||
|
ret = enable_irq_wake(aqt_irq->irq);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(aqt_irq->dev,
|
||||||
|
"Failed to set wake interrupt on IRQ %d: %d\n",
|
||||||
|
aqt_irq->irq, ret);
|
||||||
|
free_irq(aqt_irq->irq, aqt_irq);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ret)
|
||||||
|
goto fail_irq_init;
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
fail_irq_init:
|
||||||
|
dev_err(aqt_irq->dev,
|
||||||
|
"%s: Failed to init aqt irq\n", __func__);
|
||||||
|
aqt_irq_put_upstream_irq(aqt_irq);
|
||||||
|
mutex_destroy(&aqt_irq->irq_lock);
|
||||||
|
mutex_destroy(&aqt_irq->nested_irq_lock);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int aqt_irq_probe(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
int irq;
|
||||||
|
struct aqt1000_irq *aqt_irq = NULL;
|
||||||
|
int ret = -EINVAL;
|
||||||
|
|
||||||
|
irq = platform_get_irq_byname(pdev, "aqt-int");
|
||||||
|
if (irq < 0) {
|
||||||
|
dev_err(&pdev->dev, "%s: Couldn't find aqt-int node(%d)\n",
|
||||||
|
__func__, irq);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
aqt_irq = kzalloc(sizeof(*aqt_irq), GFP_KERNEL);
|
||||||
|
if (!aqt_irq)
|
||||||
|
return -ENOMEM;
|
||||||
|
/*
|
||||||
|
* AQT interrupt controller supports N to N irq mapping with
|
||||||
|
* single cell binding with irq numbers(offsets) only.
|
||||||
|
* Use irq_domain_simple_ops that has irq_domain_simple_map and
|
||||||
|
* irq_domain_xlate_onetwocell.
|
||||||
|
*/
|
||||||
|
aqt_irq->dev = &pdev->dev;
|
||||||
|
aqt_irq->domain = irq_domain_add_linear(aqt_irq->dev->of_node,
|
||||||
|
WSA_NUM_IRQS, &irq_domain_simple_ops,
|
||||||
|
aqt_irq);
|
||||||
|
if (!aqt_irq->domain) {
|
||||||
|
dev_err(&pdev->dev, "%s: domain is NULL\n", __func__);
|
||||||
|
ret = -ENOMEM;
|
||||||
|
goto err;
|
||||||
|
}
|
||||||
|
aqt_irq->dev = &pdev->dev;
|
||||||
|
|
||||||
|
dev_dbg(&pdev->dev, "%s: virq = %d\n", __func__, irq);
|
||||||
|
aqt_irq->irq = irq;
|
||||||
|
aqt_irq->num_irq_regs = 2;
|
||||||
|
aqt_irq->num_irqs = WSA_NUM_IRQS;
|
||||||
|
ret = aqt_irq_init(aqt_irq);
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(&pdev->dev, "%s: failed to do irq init %d\n",
|
||||||
|
__func__, ret);
|
||||||
|
goto err;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
err:
|
||||||
|
kfree(aqt_irq);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int aqt_irq_remove(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct irq_domain *domain;
|
||||||
|
struct aqt1000_irq *data;
|
||||||
|
|
||||||
|
domain = irq_find_host(pdev->dev.of_node);
|
||||||
|
if (unlikely(!domain)) {
|
||||||
|
pr_err("%s: domain is NULL\n", __func__);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
data = (struct aqt_irq *)domain->host_data;
|
||||||
|
data->irq = 0;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct of_device_id of_match[] = {
|
||||||
|
{ .compatible = "qcom,aqt-irq" },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_driver aqt_irq_driver = {
|
||||||
|
.probe = aqt_irq_probe,
|
||||||
|
.remove = aqt_irq_remove,
|
||||||
|
.driver = {
|
||||||
|
.name = "aqt_intc",
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
.of_match_table = of_match_ptr(of_match),
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static int aqt_irq_drv_init(void)
|
||||||
|
{
|
||||||
|
return platform_driver_register(&aqt_irq_driver);
|
||||||
|
}
|
||||||
|
subsys_initcall(aqt_irq_drv_init);
|
||||||
|
|
||||||
|
static void aqt_irq_drv_exit(void)
|
||||||
|
{
|
||||||
|
platform_driver_unregister(&aqt_irq_driver);
|
||||||
|
}
|
||||||
|
module_exit(aqt_irq_drv_exit);
|
||||||
|
|
||||||
|
MODULE_DESCRIPTION("AQT1000 IRQ driver");
|
||||||
|
MODULE_LICENSE("GPL v2");
|
||||||
73
asoc/codecs/aqt1000/aqt1000-irq.h
Normal file
73
asoc/codecs/aqt1000/aqt1000-irq.h
Normal file
@@ -0,0 +1,73 @@
|
|||||||
|
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __AQT1000_IRQ_H_
|
||||||
|
#define __AQT1000_IRQ_H_
|
||||||
|
|
||||||
|
#include <linux/interrupt.h>
|
||||||
|
#include <linux/regmap.h>
|
||||||
|
|
||||||
|
enum {
|
||||||
|
/* INTR_CTRL_INT_MASK_2 */
|
||||||
|
AQT1000_IRQ_MBHC_BUTTON_RELEASE_DET = 0,
|
||||||
|
AQT1000_IRQ_MBHC_BUTTON_PRESS_DET,
|
||||||
|
AQT1000_IRQ_MBHC_ELECT_INS_REM_DET,
|
||||||
|
AQT1000_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
|
||||||
|
AQT1000_IRQ_MBHC_SW_DET,
|
||||||
|
AQT1000_IRQ_HPH_PA_OCPL_FAULT,
|
||||||
|
AQT1000_IRQ_HPH_PA_OCPR_FAULT,
|
||||||
|
AQT1000_IRQ_HPH_PA_CNPL_COMPLETE,
|
||||||
|
|
||||||
|
/* INTR_CTRL_INT_MASK_3 */
|
||||||
|
AQT1000_IRQ_HPH_PA_CNPR_COMPLETE,
|
||||||
|
AQT1000_CDC_HPHL_SURGE,
|
||||||
|
AQT1000_CDC_HPHR_SURGE,
|
||||||
|
AQT1000_PLL_LOCK_LOSS,
|
||||||
|
AQT1000_FLL_LOCK_LOSS,
|
||||||
|
AQT1000_DSD_INT,
|
||||||
|
AQT1000_NUM_IRQS,
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct aqt_irq - AQT IRQ resource structure
|
||||||
|
* @irq_lock: lock used by irq_chip functions.
|
||||||
|
* @nested_irq_lock: lock used while handling nested interrupts.
|
||||||
|
* @irq: interrupt number.
|
||||||
|
* @irq_masks_cur: current mask value to be written to mask registers.
|
||||||
|
* @irq_masks_cache: cached mask value.
|
||||||
|
* @num_irqs: number of supported interrupts.
|
||||||
|
* @num_irq_regs: number of irq registers.
|
||||||
|
* @parent: parent pointer.
|
||||||
|
* @dev: device pointer.
|
||||||
|
* @domain: irq domain pointer.
|
||||||
|
*
|
||||||
|
* Contains required members used in wsa irq driver.
|
||||||
|
*/
|
||||||
|
|
||||||
|
struct aqt1000_irq {
|
||||||
|
struct mutex irq_lock;
|
||||||
|
struct mutex nested_irq_lock;
|
||||||
|
unsigned int irq;
|
||||||
|
u8 irq_masks_cur;
|
||||||
|
u8 irq_masks_cache;
|
||||||
|
bool irq_level_high[8];
|
||||||
|
int num_irqs;
|
||||||
|
int num_irq_regs;
|
||||||
|
void *parent;
|
||||||
|
struct device *dev;
|
||||||
|
struct irq_domain *domain;
|
||||||
|
};
|
||||||
|
|
||||||
|
int aqt_irq_init(void);
|
||||||
|
void aqt_irq_exit(void);
|
||||||
|
|
||||||
|
#endif /* __AQT1000_IRQ_H_ */
|
||||||
1133
asoc/codecs/aqt1000/aqt1000-mbhc.c
Normal file
1133
asoc/codecs/aqt1000/aqt1000-mbhc.c
Normal file
File diff suppressed because it is too large
Load Diff
84
asoc/codecs/aqt1000/aqt1000-mbhc.h
Normal file
84
asoc/codecs/aqt1000/aqt1000-mbhc.h
Normal file
@@ -0,0 +1,84 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
#ifndef __AQT_MBHC_H__
|
||||||
|
#define __AQT_MBHC_H__
|
||||||
|
#include "../wcd-mbhc-v2.h"
|
||||||
|
|
||||||
|
enum aqt_on_demand_supply_name {
|
||||||
|
AQT_ON_DEMAND_MICBIAS = 0,
|
||||||
|
AQT_ON_DEMAND_SUPPLIES_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aqt_on_demand_supply {
|
||||||
|
struct regulator *supply;
|
||||||
|
int ondemand_supply_count;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aqt_mbhc {
|
||||||
|
struct wcd_mbhc wcd_mbhc;
|
||||||
|
struct blocking_notifier_head notifier;
|
||||||
|
struct aqt_on_demand_supply on_demand_list[
|
||||||
|
AQT_ON_DEMAND_SUPPLIES_MAX];
|
||||||
|
struct aqt1000 *aqt;
|
||||||
|
struct fw_info *fw_data;
|
||||||
|
bool mbhc_started;
|
||||||
|
bool is_hph_recover;
|
||||||
|
};
|
||||||
|
|
||||||
|
#if IS_ENABLED(CONFIG_SND_SOC_AQT_MBHC)
|
||||||
|
extern int aqt_mbhc_init(struct aqt_mbhc **mbhc,
|
||||||
|
struct snd_soc_codec *codec,
|
||||||
|
struct fw_info *fw_data);
|
||||||
|
extern void aqt_mbhc_hs_detect_exit(struct snd_soc_codec *codec);
|
||||||
|
extern int aqt_mbhc_hs_detect(struct snd_soc_codec *codec,
|
||||||
|
struct wcd_mbhc_config *mbhc_cfg);
|
||||||
|
extern void aqt_mbhc_deinit(struct snd_soc_codec *codec);
|
||||||
|
extern int aqt_mbhc_post_ssr_init(struct aqt_mbhc *mbhc,
|
||||||
|
struct snd_soc_codec *codec);
|
||||||
|
extern int aqt_mbhc_get_impedance(struct aqt_mbhc *aqt_mbhc,
|
||||||
|
uint32_t *zl, uint32_t *zr);
|
||||||
|
#else
|
||||||
|
static inline int aqt_mbhc_init(struct aqt_mbhc **mbhc,
|
||||||
|
struct snd_soc_codec *codec,
|
||||||
|
struct fw_info *fw_data)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
static inline void aqt_mbhc_hs_detect_exit(struct snd_soc_codec *codec)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
static inline int aqt_mbhc_hs_detect(struct snd_soc_codec *codec,
|
||||||
|
struct wcd_mbhc_config *mbhc_cfg)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
static inline void aqt_mbhc_deinit(struct snd_soc_codec *codec)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
static inline int aqt_mbhc_post_ssr_init(struct aqt_mbhc *mbhc,
|
||||||
|
struct snd_soc_codec *codec)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
static inline int aqt_mbhc_get_impedance(struct aqt_mbhc *aqt_mbhc,
|
||||||
|
uint32_t *zl, uint32_t *zr)
|
||||||
|
{
|
||||||
|
if (zl)
|
||||||
|
*zl = 0;
|
||||||
|
if (zr)
|
||||||
|
*zr = 0;
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __AQT_MBHC_H__ */
|
||||||
1616
asoc/codecs/aqt1000/aqt1000-reg-defaults.h
Normal file
1616
asoc/codecs/aqt1000/aqt1000-reg-defaults.h
Normal file
File diff suppressed because it is too large
Load Diff
881
asoc/codecs/aqt1000/aqt1000-registers.h
Normal file
881
asoc/codecs/aqt1000/aqt1000-registers.h
Normal file
@@ -0,0 +1,881 @@
|
|||||||
|
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _AQT1000_REGISTERS_H
|
||||||
|
#define _AQT1000_REGISTERS_H
|
||||||
|
|
||||||
|
#define AQT1000_PAGE0_BASE (0x00000000)
|
||||||
|
#define AQT1000_PAGE0_PAGE_REGISTER (0x00000000)
|
||||||
|
#define AQT1000_CHIP_CFG0_BASE (0x00000001)
|
||||||
|
#define AQT1000_CHIP_CFG0_CHIP_ID_BYTE0 (0x00000001)
|
||||||
|
#define AQT1000_CHIP_CFG0_CHIP_ID_BYTE1 (0x00000002)
|
||||||
|
#define AQT1000_CHIP_CFG0_CHIP_ID_BYTE2 (0x00000003)
|
||||||
|
#define AQT1000_CHIP_CFG0_CHIP_ID_BYTE3 (0x00000004)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_CTL (0x00000005)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_TEST0 (0x00000006)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_TEST1 (0x00000007)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT0 (0x00000009)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT1 (0x0000000A)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT2 (0x0000000B)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT3 (0x0000000C)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT4 (0x0000000D)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT5 (0x0000000E)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT6 (0x0000000F)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT7 (0x00000010)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT8 (0x00000011)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT9 (0x00000012)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT10 (0x00000013)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT11 (0x00000014)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT12 (0x00000015)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT13 (0x00000016)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT14 (0x00000017)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT15 (0x00000018)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE_STATUS (0x00000019)
|
||||||
|
#define AQT1000_CHIP_CFG0_I2C_SLAVE_ID_NONNEGO (0x0000001A)
|
||||||
|
#define AQT1000_CHIP_CFG0_I2C_SLAVE_ID_1 (0x0000001B)
|
||||||
|
#define AQT1000_CHIP_CFG0_I2C_SLAVE_ID_2 (0x0000001C)
|
||||||
|
#define AQT1000_CHIP_CFG0_I2C_SLAVE_ID_3 (0x0000001D)
|
||||||
|
#define AQT1000_CHIP_CFG0_I2C_ACTIVE (0x00000020)
|
||||||
|
#define AQT1000_CHIP_CFG0_CLK_CFG_MCLK (0x00000021)
|
||||||
|
#define AQT1000_CHIP_CFG0_CLK_CFG_MCLK2 (0x00000022)
|
||||||
|
#define AQT1000_CHIP_CFG0_CLK_CTL_CDC_DIG (0x00000023)
|
||||||
|
#define AQT1000_CHIP_CFG0_RST_CTL (0x00000032)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_CTL (0x0000003D)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_TEST0 (0x0000003E)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_TEST1 (0x0000003F)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT0 (0x00000040)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT1 (0x00000041)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT2 (0x00000042)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT3 (0x00000043)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT4 (0x00000044)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT5 (0x00000045)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT6 (0x00000046)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT7 (0x00000047)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT8 (0x00000048)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT9 (0x00000049)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT10 (0x0000004A)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT11 (0x0000004B)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT12 (0x0000004C)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT13 (0x0000004D)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT14 (0x0000004E)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT15 (0x0000004F)
|
||||||
|
#define AQT1000_CHIP_CFG0_EFUSE2_STATUS (0x00000050)
|
||||||
|
#define AQT1000_CHIP_CFG1_BASE (0x00000051)
|
||||||
|
#define AQT1000_CHIP_CFG1_PWR_CTL (0x00000051)
|
||||||
|
#define AQT1000_CHIP_CFG1_BUS_MTRX_CFG (0x00000052)
|
||||||
|
#define AQT1000_CHIP_CFG1_DMA_BUS_VOTE (0x00000053)
|
||||||
|
#define AQT1000_CHIP_CFG1_USB_BUS_VOTE (0x00000054)
|
||||||
|
#define AQT1000_CHIP_CFG1_BLSP_BUS_VOTE (0x00000055)
|
||||||
|
#define AQT1000_CHIP_CFG1_PWR_MEM_SD (0x00000059)
|
||||||
|
#define AQT1000_CHIP_CFG1_PWR_SYS_MEM_SD_RAM (0x0000005C)
|
||||||
|
#define AQT1000_CHIP_CFG1_PWR_SYS_MEM_SD_ROM (0x0000005D)
|
||||||
|
#define AQT1000_CHIP_CFG1_PWR_SYS_MEM_FORCE_DS_RAM (0x0000005E)
|
||||||
|
#define AQT1000_CHIP_CFG1_PWR_SYS_MEM_FORCE_DS_ROM (0x0000005F)
|
||||||
|
#define AQT1000_CHIP_CFG1_CLK_CFG_FLL (0x00000061)
|
||||||
|
#define AQT1000_CHIP_CFG1_CLK_CFG_SPI_M (0x00000062)
|
||||||
|
#define AQT1000_CHIP_CFG1_CLK_CFG_I2C_M (0x00000063)
|
||||||
|
#define AQT1000_CHIP_CFG1_CLK_CFG_UART (0x00000064)
|
||||||
|
#define AQT1000_CHIP_CFG1_RST_USB_SS (0x00000071)
|
||||||
|
#define AQT1000_CHIP_CFG1_RST_BLSP (0x00000072)
|
||||||
|
#define AQT1000_CHIP_CFG1_RST_BUS_MTRX (0x00000073)
|
||||||
|
#define AQT1000_CHIP_CFG1_RST_MISC (0x00000074)
|
||||||
|
#define AQT1000_CHIP_CFG1_ANA_WAIT_STATE_CTL (0x00000081)
|
||||||
|
#define AQT1000_PAGE1_BASE (0x00000100)
|
||||||
|
#define AQT1000_PAGE1_PAGE_REGISTER (0x00000100)
|
||||||
|
#define AQT1000_FLL_BASE (0x00000101)
|
||||||
|
#define AQT1000_FLL_USER_CTL_0 (0x00000101)
|
||||||
|
#define AQT1000_FLL_USER_CTL_1 (0x00000102)
|
||||||
|
#define AQT1000_FLL_USER_CTL_2 (0x00000103)
|
||||||
|
#define AQT1000_FLL_USER_CTL_3 (0x00000104)
|
||||||
|
#define AQT1000_FLL_USER_CTL_4 (0x00000105)
|
||||||
|
#define AQT1000_FLL_USER_CTL_5 (0x00000106)
|
||||||
|
#define AQT1000_FLL_USER_CTL_6 (0x00000107)
|
||||||
|
#define AQT1000_FLL_USER_CTL_7 (0x00000108)
|
||||||
|
#define AQT1000_FLL_USER_CTL_8 (0x00000109)
|
||||||
|
#define AQT1000_FLL_USER_CTL_9 (0x0000010A)
|
||||||
|
#define AQT1000_FLL_L_VAL_CTL_0 (0x0000010B)
|
||||||
|
#define AQT1000_FLL_L_VAL_CTL_1 (0x0000010C)
|
||||||
|
#define AQT1000_FLL_DSM_FRAC_CTL_0 (0x0000010D)
|
||||||
|
#define AQT1000_FLL_DSM_FRAC_CTL_1 (0x0000010E)
|
||||||
|
#define AQT1000_FLL_CONFIG_CTL_0 (0x0000010F)
|
||||||
|
#define AQT1000_FLL_CONFIG_CTL_1 (0x00000110)
|
||||||
|
#define AQT1000_FLL_CONFIG_CTL_2 (0x00000111)
|
||||||
|
#define AQT1000_FLL_CONFIG_CTL_3 (0x00000112)
|
||||||
|
#define AQT1000_FLL_CONFIG_CTL_4 (0x00000113)
|
||||||
|
#define AQT1000_FLL_TEST_CTL_0 (0x00000114)
|
||||||
|
#define AQT1000_FLL_TEST_CTL_1 (0x00000115)
|
||||||
|
#define AQT1000_FLL_TEST_CTL_2 (0x00000116)
|
||||||
|
#define AQT1000_FLL_TEST_CTL_3 (0x00000117)
|
||||||
|
#define AQT1000_FLL_TEST_CTL_4 (0x00000118)
|
||||||
|
#define AQT1000_FLL_TEST_CTL_5 (0x00000119)
|
||||||
|
#define AQT1000_FLL_TEST_CTL_6 (0x0000011A)
|
||||||
|
#define AQT1000_FLL_TEST_CTL_7 (0x0000011B)
|
||||||
|
#define AQT1000_FLL_FREQ_CTL_0 (0x0000011C)
|
||||||
|
#define AQT1000_FLL_FREQ_CTL_1 (0x0000011D)
|
||||||
|
#define AQT1000_FLL_FREQ_CTL_2 (0x0000011E)
|
||||||
|
#define AQT1000_FLL_FREQ_CTL_3 (0x0000011F)
|
||||||
|
#define AQT1000_FLL_SSC_CTL_0 (0x00000120)
|
||||||
|
#define AQT1000_FLL_SSC_CTL_1 (0x00000121)
|
||||||
|
#define AQT1000_FLL_SSC_CTL_2 (0x00000122)
|
||||||
|
#define AQT1000_FLL_SSC_CTL_3 (0x00000123)
|
||||||
|
#define AQT1000_FLL_FLL_MODE (0x00000124)
|
||||||
|
#define AQT1000_FLL_STATUS_0 (0x00000125)
|
||||||
|
#define AQT1000_FLL_STATUS_1 (0x00000126)
|
||||||
|
#define AQT1000_FLL_STATUS_2 (0x00000127)
|
||||||
|
#define AQT1000_FLL_STATUS_3 (0x00000128)
|
||||||
|
#define AQT1000_PAGE2_BASE (0x00000200)
|
||||||
|
#define AQT1000_PAGE2_PAGE_REGISTER (0x00000200)
|
||||||
|
#define AQT1000_I2S_BASE (0x00000201)
|
||||||
|
#define AQT1000_I2S_I2S_0_TX_CFG (0x00000201)
|
||||||
|
#define AQT1000_I2S_I2S_0_RX_CFG (0x00000202)
|
||||||
|
#define AQT1000_I2S_I2S_0_CTL (0x00000203)
|
||||||
|
#define AQT1000_I2S_I2S_CLKSRC_CTL (0x00000204)
|
||||||
|
#define AQT1000_I2S_I2S_HS_CLK_CTL (0x00000205)
|
||||||
|
#define AQT1000_I2S_I2S_0_RST (0x00000206)
|
||||||
|
#define AQT1000_I2S_SHADOW_I2S_0_CTL (0x00000207)
|
||||||
|
#define AQT1000_I2S_SHADOW_I2S_0_RX_CFG (0x00000208)
|
||||||
|
#define AQT1000_PAGE5_BASE (0x00000500)
|
||||||
|
#define AQT1000_PAGE5_PAGE_REGISTER (0x00000500)
|
||||||
|
#define AQT1000_INTR_CTRL_INTR_CTRL_BASE (0x00000501)
|
||||||
|
#define AQT1000_INTR_CTRL_MCU_INT_POLARITY (0x00000501)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_MASK_0 (0x00000502)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_MASK_1 (0x00000503)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_MASK_2 (0x00000504)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_MASK_3 (0x00000505)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_MASK_4 (0x00000506)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_MASK_5 (0x00000507)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_MASK_6 (0x00000508)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_STATUS_0 (0x00000509)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_STATUS_1 (0x0000050A)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_STATUS_2 (0x0000050B)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_STATUS_3 (0x0000050C)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_STATUS_4 (0x0000050D)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_STATUS_5 (0x0000050E)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_STATUS_6 (0x0000050F)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_CLEAR_0 (0x00000510)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_CLEAR_1 (0x00000511)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_CLEAR_2 (0x00000512)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_CLEAR_3 (0x00000513)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_CLEAR_4 (0x00000514)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_CLEAR_5 (0x00000515)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_CLEAR_6 (0x00000516)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TYPE_0 (0x00000517)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TYPE_1 (0x00000518)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TYPE_2 (0x00000519)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TYPE_3 (0x0000051A)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TYPE_4 (0x0000051B)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TYPE_5 (0x0000051C)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TYPE_6 (0x0000051D)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TEST_EN_0 (0x0000051E)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TEST_EN_1 (0x0000051F)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TEST_EN_2 (0x00000520)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TEST_EN_3 (0x00000521)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TEST_EN_4 (0x00000522)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TEST_EN_5 (0x00000523)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TEST_EN_6 (0x00000524)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TEST_VAL_0 (0x00000525)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TEST_VAL_1 (0x00000526)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TEST_VAL_2 (0x00000527)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TEST_VAL_3 (0x00000528)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TEST_VAL_4 (0x00000529)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TEST_VAL_5 (0x0000052A)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_TEST_VAL_6 (0x0000052B)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_DEST_0 (0x0000052C)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_DEST_1 (0x0000052D)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_DEST_2 (0x0000052E)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_DEST_3 (0x0000052F)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_DEST_4 (0x00000530)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_DEST_5 (0x00000531)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_DEST_6 (0x00000532)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_DEST_7 (0x00000533)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_DEST_8 (0x00000534)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_DEST_9 (0x00000535)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_DEST_10 (0x00000536)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_DEST_11 (0x00000537)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_DEST_12 (0x00000538)
|
||||||
|
#define AQT1000_INTR_CTRL_INT_DEST_13 (0x00000539)
|
||||||
|
#define AQT1000_INTR_CTRL_CLR_COMMIT (0x000005E1)
|
||||||
|
#define AQT1000_ANA_BASE (0x00000600)
|
||||||
|
#define AQT1000_ANA_PAGE_REGISTER (0x00000600)
|
||||||
|
#define AQT1000_ANA_BIAS (0x00000601)
|
||||||
|
#define AQT1000_ANA_RX_SUPPLIES (0x00000608)
|
||||||
|
#define AQT1000_ANA_HPH (0x00000609)
|
||||||
|
#define AQT1000_ANA_AMIC1 (0x0000060E)
|
||||||
|
#define AQT1000_ANA_AMIC2 (0x0000060F)
|
||||||
|
#define AQT1000_ANA_AMIC3 (0x00000610)
|
||||||
|
#define AQT1000_ANA_AMIC3_HPF (0x00000611)
|
||||||
|
#define AQT1000_ANA_MBHC_MECH (0x00000614)
|
||||||
|
#define AQT1000_ANA_MBHC_ELECT (0x00000615)
|
||||||
|
#define AQT1000_ANA_MBHC_ZDET (0x00000616)
|
||||||
|
#define AQT1000_ANA_MBHC_RESULT_1 (0x00000617)
|
||||||
|
#define AQT1000_ANA_MBHC_RESULT_2 (0x00000618)
|
||||||
|
#define AQT1000_ANA_MBHC_RESULT_3 (0x00000619)
|
||||||
|
#define AQT1000_ANA_MBHC_BTN0 (0x0000061A)
|
||||||
|
#define AQT1000_ANA_MBHC_BTN1 (0x0000061B)
|
||||||
|
#define AQT1000_ANA_MBHC_BTN2 (0x0000061C)
|
||||||
|
#define AQT1000_ANA_MBHC_BTN3 (0x0000061D)
|
||||||
|
#define AQT1000_ANA_MBHC_BTN4 (0x0000061E)
|
||||||
|
#define AQT1000_ANA_MBHC_BTN5 (0x0000061F)
|
||||||
|
#define AQT1000_ANA_MBHC_BTN6 (0x00000620)
|
||||||
|
#define AQT1000_ANA_MBHC_BTN7 (0x00000621)
|
||||||
|
#define AQT1000_ANA_MICB1 (0x00000622)
|
||||||
|
#define AQT1000_ANA_MICB1_RAMP (0x00000624)
|
||||||
|
#define AQT1000_BIAS_BASE (0x00000628)
|
||||||
|
#define AQT1000_BIAS_CTL (0x00000628)
|
||||||
|
#define AQT1000_BIAS_CCOMP_FINE_ADJ (0x00000629)
|
||||||
|
#define AQT1000_LED_BASE (0x0000062E)
|
||||||
|
#define AQT1000_LED_LED_MODE_SEL_R (0x0000062E)
|
||||||
|
#define AQT1000_LED_LED_MISC_R (0x0000062F)
|
||||||
|
#define AQT1000_LED_LED_MODE_SEL_G (0x00000630)
|
||||||
|
#define AQT1000_LED_LED_MISC_G (0x00000631)
|
||||||
|
#define AQT1000_LED_LED_MODE_SEL_B (0x00000632)
|
||||||
|
#define AQT1000_LED_LED_MISC_B (0x00000633)
|
||||||
|
#define AQT1000_LDOH_BASE (0x0000063A)
|
||||||
|
#define AQT1000_LDOH_MODE (0x0000063A)
|
||||||
|
#define AQT1000_LDOH_BIAS (0x0000063B)
|
||||||
|
#define AQT1000_LDOH_STB_LOADS (0x0000063C)
|
||||||
|
#define AQT1000_LDOH_MISC1 (0x0000063D)
|
||||||
|
#define AQT1000_LDOL_BASE (0x00000640)
|
||||||
|
#define AQT1000_LDOL_VDDCX_ADJUST (0x00000640)
|
||||||
|
#define AQT1000_LDOL_DISABLE_LDOL (0x00000641)
|
||||||
|
#define AQT1000_BUCK_5V_BASE (0x00000644)
|
||||||
|
#define AQT1000_BUCK_5V_EN_CTL (0x00000644)
|
||||||
|
#define AQT1000_BUCK_5V_VOUT_SEL (0x00000645)
|
||||||
|
#define AQT1000_BUCK_5V_CTRL_VCL_1 (0x00000646)
|
||||||
|
#define AQT1000_BUCK_5V_CTRL_VCL_2 (0x00000647)
|
||||||
|
#define AQT1000_BUCK_5V_CTRL_CCL_2 (0x00000648)
|
||||||
|
#define AQT1000_BUCK_5V_CTRL_CCL_1 (0x00000649)
|
||||||
|
#define AQT1000_BUCK_5V_CTRL_CCL_3 (0x0000064A)
|
||||||
|
#define AQT1000_BUCK_5V_CTRL_CCL_4 (0x0000064B)
|
||||||
|
#define AQT1000_BUCK_5V_CTRL_CCL_5 (0x0000064C)
|
||||||
|
#define AQT1000_BUCK_5V_IBIAS_CTL_1 (0x0000064D)
|
||||||
|
#define AQT1000_BUCK_5V_IBIAS_CTL_2 (0x0000064E)
|
||||||
|
#define AQT1000_BUCK_5V_IBIAS_CTL_3 (0x0000064F)
|
||||||
|
#define AQT1000_BUCK_5V_IBIAS_CTL_4 (0x00000650)
|
||||||
|
#define AQT1000_BUCK_5V_IBIAS_CTL_5 (0x00000651)
|
||||||
|
#define AQT1000_BUCK_5V_ATEST_DTEST_CTL (0x00000652)
|
||||||
|
#define AQT1000_PON_BASE (0x00000653)
|
||||||
|
#define AQT1000_PON_BG_CTRL (0x00000653)
|
||||||
|
#define AQT1000_PON_TEST_CTRL (0x00000654)
|
||||||
|
#define AQT1000_MBHC_BASE (0x00000656)
|
||||||
|
#define AQT1000_MBHC_CTL_CLK (0x00000656)
|
||||||
|
#define AQT1000_MBHC_CTL_ANA (0x00000657)
|
||||||
|
#define AQT1000_MBHC_CTL_SPARE_1 (0x00000658)
|
||||||
|
#define AQT1000_MBHC_CTL_SPARE_2 (0x00000659)
|
||||||
|
#define AQT1000_MBHC_CTL_BCS (0x0000065A)
|
||||||
|
#define AQT1000_MBHC_MOISTURE_DET_FSM_STATUS (0x0000065B)
|
||||||
|
#define AQT1000_MBHC_TEST_CTL (0x0000065C)
|
||||||
|
#define AQT1000_MICB1_BASE (0x0000066B)
|
||||||
|
#define AQT1000_MICB1_TEST_CTL_1 (0x0000066B)
|
||||||
|
#define AQT1000_MICB1_TEST_CTL_2 (0x0000066C)
|
||||||
|
#define AQT1000_MICB1_TEST_CTL_3 (0x0000066D)
|
||||||
|
#define AQT1000_MICB1_MISC_BASE (0x0000066E)
|
||||||
|
#define AQT1000_MICB1_MISC_MICB1_INM_RES_BIAS (0x0000066E)
|
||||||
|
#define AQT1000_MICB1_MISC_MICB_MISC1 (0x0000066F)
|
||||||
|
#define AQT1000_MICB1_MISC_MICB_MISC2 (0x00000670)
|
||||||
|
#define AQT1000_TX_COM_BASE (0x00000677)
|
||||||
|
#define AQT1000_TX_COM_ADC_VCM (0x00000677)
|
||||||
|
#define AQT1000_TX_COM_BIAS_ATEST (0x00000678)
|
||||||
|
#define AQT1000_TX_COM_ADC_INT1_IB (0x00000679)
|
||||||
|
#define AQT1000_TX_COM_ADC_INT2_IB (0x0000067A)
|
||||||
|
#define AQT1000_TX_COM_TXFE_DIV_CTL (0x0000067B)
|
||||||
|
#define AQT1000_TX_COM_TXFE_DIV_START (0x0000067C)
|
||||||
|
#define AQT1000_TX_COM_TXFE_DIV_STOP_9P6M (0x0000067D)
|
||||||
|
#define AQT1000_TX_COM_TXFE_DIV_STOP_12P288M (0x0000067E)
|
||||||
|
#define AQT1000_TX_1_2_BASE (0x0000067F)
|
||||||
|
#define AQT1000_TX_1_2_TEST_EN (0x0000067F)
|
||||||
|
#define AQT1000_TX_1_2_ADC_IB (0x00000680)
|
||||||
|
#define AQT1000_TX_1_2_ATEST_REFCTL (0x00000681)
|
||||||
|
#define AQT1000_TX_1_2_TEST_CTL (0x00000682)
|
||||||
|
#define AQT1000_TX_1_2_TEST_BLK_EN (0x00000683)
|
||||||
|
#define AQT1000_TX_1_2_TXFE_CLKDIV (0x00000684)
|
||||||
|
#define AQT1000_TX_1_2_SAR1_ERR (0x00000685)
|
||||||
|
#define AQT1000_TX_1_2_SAR2_ERR (0x00000686)
|
||||||
|
#define AQT1000_TX_3_BASE (0x00000687)
|
||||||
|
#define AQT1000_TX_3_TEST_EN (0x00000687)
|
||||||
|
#define AQT1000_TX_3_ADC_IB (0x00000688)
|
||||||
|
#define AQT1000_TX_3_ATEST_REFCTL (0x00000689)
|
||||||
|
#define AQT1000_TX_3_TEST_CTL (0x0000068A)
|
||||||
|
#define AQT1000_TX_3_TEST_BLK_EN (0x0000068B)
|
||||||
|
#define AQT1000_TX_3_TXFE_CLKDIV (0x0000068C)
|
||||||
|
#define AQT1000_TX_3_SAR1_ERR (0x0000068D)
|
||||||
|
#define AQT1000_TX_3_SAR2_ERR (0x0000068E)
|
||||||
|
#define AQT1000_TX_BASE (0x0000068F)
|
||||||
|
#define AQT1000_TX_ATEST1_2_SEL (0x0000068F)
|
||||||
|
#define AQT1000_CLASSH_BASE (0x00000697)
|
||||||
|
#define AQT1000_CLASSH_MODE_1 (0x00000697)
|
||||||
|
#define AQT1000_CLASSH_MODE_2 (0x00000698)
|
||||||
|
#define AQT1000_CLASSH_MODE_3 (0x00000699)
|
||||||
|
#define AQT1000_CLASSH_CTRL_VCL_1 (0x0000069A)
|
||||||
|
#define AQT1000_CLASSH_CTRL_VCL_2 (0x0000069B)
|
||||||
|
#define AQT1000_CLASSH_CTRL_CCL_1 (0x0000069C)
|
||||||
|
#define AQT1000_CLASSH_CTRL_CCL_2 (0x0000069D)
|
||||||
|
#define AQT1000_CLASSH_CTRL_CCL_3 (0x0000069E)
|
||||||
|
#define AQT1000_CLASSH_CTRL_CCL_4 (0x0000069F)
|
||||||
|
#define AQT1000_CLASSH_CTRL_CCL_5 (0x000006A0)
|
||||||
|
#define AQT1000_CLASSH_BUCK_TMUX_A_D (0x000006A1)
|
||||||
|
#define AQT1000_CLASSH_BUCK_SW_DRV_CNTL (0x000006A2)
|
||||||
|
#define AQT1000_CLASSH_SPARE (0x000006A3)
|
||||||
|
#define AQT1000_FLYBACK_BASE (0x000006A4)
|
||||||
|
#define AQT1000_FLYBACK_EN (0x000006A4)
|
||||||
|
#define AQT1000_FLYBACK_VNEG_CTRL_1 (0x000006A5)
|
||||||
|
#define AQT1000_FLYBACK_VNEG_CTRL_2 (0x000006A6)
|
||||||
|
#define AQT1000_FLYBACK_VNEG_CTRL_3 (0x000006A7)
|
||||||
|
#define AQT1000_FLYBACK_VNEG_CTRL_4 (0x000006A8)
|
||||||
|
#define AQT1000_FLYBACK_VNEG_CTRL_5 (0x000006A9)
|
||||||
|
#define AQT1000_FLYBACK_VNEG_CTRL_6 (0x000006AA)
|
||||||
|
#define AQT1000_FLYBACK_VNEG_CTRL_7 (0x000006AB)
|
||||||
|
#define AQT1000_FLYBACK_VNEG_CTRL_8 (0x000006AC)
|
||||||
|
#define AQT1000_FLYBACK_VNEG_CTRL_9 (0x000006AD)
|
||||||
|
#define AQT1000_FLYBACK_VNEGDAC_CTRL_1 (0x000006AE)
|
||||||
|
#define AQT1000_FLYBACK_VNEGDAC_CTRL_2 (0x000006AF)
|
||||||
|
#define AQT1000_FLYBACK_VNEGDAC_CTRL_3 (0x000006B0)
|
||||||
|
#define AQT1000_FLYBACK_CTRL_1 (0x000006B1)
|
||||||
|
#define AQT1000_FLYBACK_TEST_CTL (0x000006B2)
|
||||||
|
#define AQT1000_RX_BASE (0x000006B3)
|
||||||
|
#define AQT1000_RX_AUX_SW_CTL (0x000006B3)
|
||||||
|
#define AQT1000_RX_PA_AUX_IN_CONN (0x000006B4)
|
||||||
|
#define AQT1000_RX_TIMER_DIV (0x000006B5)
|
||||||
|
#define AQT1000_RX_OCP_CTL (0x000006B6)
|
||||||
|
#define AQT1000_RX_OCP_COUNT (0x000006B7)
|
||||||
|
#define AQT1000_RX_BIAS_ATEST (0x000006B8)
|
||||||
|
#define AQT1000_RX_BIAS_MISC1 (0x000006B9)
|
||||||
|
#define AQT1000_RX_BIAS_HPH_LDO (0x000006BA)
|
||||||
|
#define AQT1000_RX_BIAS_HPH_PA (0x000006BB)
|
||||||
|
#define AQT1000_RX_BIAS_HPH_RDACBUFF_CNP2 (0x000006BC)
|
||||||
|
#define AQT1000_RX_BIAS_HPH_RDAC_LDO (0x000006BD)
|
||||||
|
#define AQT1000_RX_BIAS_HPH_CNP1 (0x000006BE)
|
||||||
|
#define AQT1000_RX_BIAS_HPH_LOWPOWER (0x000006BF)
|
||||||
|
#define AQT1000_RX_BIAS_MISC2 (0x000006C0)
|
||||||
|
#define AQT1000_RX_BIAS_MISC3 (0x000006C1)
|
||||||
|
#define AQT1000_RX_BIAS_MISC4 (0x000006C2)
|
||||||
|
#define AQT1000_RX_BIAS_MISC5 (0x000006C3)
|
||||||
|
#define AQT1000_RX_BIAS_BUCK_RST (0x000006C4)
|
||||||
|
#define AQT1000_RX_BIAS_BUCK_VREF_ERRAMP (0x000006C5)
|
||||||
|
#define AQT1000_RX_BIAS_FLYB_ERRAMP (0x000006C6)
|
||||||
|
#define AQT1000_RX_BIAS_FLYB_BUFF (0x000006C7)
|
||||||
|
#define AQT1000_RX_BIAS_FLYB_MID_RST (0x000006C8)
|
||||||
|
#define AQT1000_HPH_BASE (0x000006C9)
|
||||||
|
#define AQT1000_HPH_L_STATUS (0x000006C9)
|
||||||
|
#define AQT1000_HPH_R_STATUS (0x000006CA)
|
||||||
|
#define AQT1000_HPH_CNP_EN (0x000006CB)
|
||||||
|
#define AQT1000_HPH_CNP_WG_CTL (0x000006CC)
|
||||||
|
#define AQT1000_HPH_CNP_WG_TIME (0x000006CD)
|
||||||
|
#define AQT1000_HPH_OCP_CTL (0x000006CE)
|
||||||
|
#define AQT1000_HPH_AUTO_CHOP (0x000006CF)
|
||||||
|
#define AQT1000_HPH_CHOP_CTL (0x000006D0)
|
||||||
|
#define AQT1000_HPH_PA_CTL1 (0x000006D1)
|
||||||
|
#define AQT1000_HPH_PA_CTL2 (0x000006D2)
|
||||||
|
#define AQT1000_HPH_L_EN (0x000006D3)
|
||||||
|
#define AQT1000_HPH_L_TEST (0x000006D4)
|
||||||
|
#define AQT1000_HPH_L_ATEST (0x000006D5)
|
||||||
|
#define AQT1000_HPH_R_EN (0x000006D6)
|
||||||
|
#define AQT1000_HPH_R_TEST (0x000006D7)
|
||||||
|
#define AQT1000_HPH_R_ATEST (0x000006D8)
|
||||||
|
#define AQT1000_HPH_RDAC_CLK_CTL1 (0x000006D9)
|
||||||
|
#define AQT1000_HPH_RDAC_CLK_CTL2 (0x000006DA)
|
||||||
|
#define AQT1000_HPH_RDAC_LDO_CTL (0x000006DB)
|
||||||
|
#define AQT1000_HPH_RDAC_CHOP_CLK_LP_CTL (0x000006DC)
|
||||||
|
#define AQT1000_HPH_REFBUFF_UHQA_CTL (0x000006DD)
|
||||||
|
#define AQT1000_HPH_REFBUFF_LP_CTL (0x000006DE)
|
||||||
|
#define AQT1000_HPH_L_DAC_CTL (0x000006DF)
|
||||||
|
#define AQT1000_HPH_R_DAC_CTL (0x000006E0)
|
||||||
|
#define AQT1000_HPHLR_BASE (0x000006E1)
|
||||||
|
#define AQT1000_HPHLR_SURGE_COMP_SEL (0x000006E1)
|
||||||
|
#define AQT1000_HPHLR_SURGE_EN (0x000006E2)
|
||||||
|
#define AQT1000_HPHLR_SURGE_MISC1 (0x000006E3)
|
||||||
|
#define AQT1000_HPHLR_SURGE_STATUS (0x000006E4)
|
||||||
|
#define AQT1000_ANA_NEW_BASE (0x00000700)
|
||||||
|
#define AQT1000_ANA_NEW_PAGE_REGISTER (0x00000700)
|
||||||
|
#define AQT1000_HPH_NEW_BASE (0x00000701)
|
||||||
|
#define AQT1000_HPH_NEW_ANA_HPH2 (0x00000701)
|
||||||
|
#define AQT1000_HPH_NEW_ANA_HPH3 (0x00000702)
|
||||||
|
#define AQT1000_CLK_SYS_BASE (0x0000070E)
|
||||||
|
#define AQT1000_CLK_SYS_MCLK1_PRG (0x0000070E)
|
||||||
|
#define AQT1000_CLK_SYS_MCLK2_I2S_HS_CLK_PRG (0x0000070F)
|
||||||
|
#define AQT1000_CLK_SYS_XO_CAP_XTP (0x00000710)
|
||||||
|
#define AQT1000_CLK_SYS_XO_CAP_XTM (0x00000711)
|
||||||
|
#define AQT1000_CLK_SYS_PLL_ENABLES (0x00000712)
|
||||||
|
#define AQT1000_CLK_SYS_PLL_PRESET (0x00000713)
|
||||||
|
#define AQT1000_CLK_SYS_PLL_STATUS (0x00000714)
|
||||||
|
#define AQT1000_MBHC_NEW_BASE (0x0000071F)
|
||||||
|
#define AQT1000_MBHC_NEW_ELECT_REM_CLAMP_CTL (0x0000071F)
|
||||||
|
#define AQT1000_MBHC_NEW_CTL_1 (0x00000720)
|
||||||
|
#define AQT1000_MBHC_NEW_CTL_2 (0x00000721)
|
||||||
|
#define AQT1000_MBHC_NEW_PLUG_DETECT_CTL (0x00000722)
|
||||||
|
#define AQT1000_MBHC_NEW_ZDET_ANA_CTL (0x00000723)
|
||||||
|
#define AQT1000_MBHC_NEW_ZDET_RAMP_CTL (0x00000724)
|
||||||
|
#define AQT1000_MBHC_NEW_FSM_STATUS (0x00000725)
|
||||||
|
#define AQT1000_MBHC_NEW_ADC_RESULT (0x00000726)
|
||||||
|
#define AQT1000_HPH_NEW_INT_BASE (0x00000732)
|
||||||
|
#define AQT1000_HPH_NEW_INT_RDAC_GAIN_CTL (0x00000732)
|
||||||
|
#define AQT1000_HPH_NEW_INT_RDAC_HD2_CTL_L (0x00000733)
|
||||||
|
#define AQT1000_HPH_NEW_INT_RDAC_VREF_CTL (0x00000734)
|
||||||
|
#define AQT1000_HPH_NEW_INT_RDAC_OVERRIDE_CTL (0x00000735)
|
||||||
|
#define AQT1000_HPH_NEW_INT_RDAC_HD2_CTL_R (0x00000736)
|
||||||
|
#define AQT1000_HPH_NEW_INT_PA_MISC1 (0x00000737)
|
||||||
|
#define AQT1000_HPH_NEW_INT_PA_MISC2 (0x00000738)
|
||||||
|
#define AQT1000_HPH_NEW_INT_PA_RDAC_MISC (0x00000739)
|
||||||
|
#define AQT1000_HPH_NEW_INT_HPH_TIMER1 (0x0000073A)
|
||||||
|
#define AQT1000_HPH_NEW_INT_HPH_TIMER2 (0x0000073B)
|
||||||
|
#define AQT1000_HPH_NEW_INT_HPH_TIMER3 (0x0000073C)
|
||||||
|
#define AQT1000_HPH_NEW_INT_HPH_TIMER4 (0x0000073D)
|
||||||
|
#define AQT1000_HPH_NEW_INT_PA_RDAC_MISC2 (0x0000073E)
|
||||||
|
#define AQT1000_HPH_NEW_INT_PA_RDAC_MISC3 (0x0000073F)
|
||||||
|
#define AQT1000_RX_NEW_INT_BASE (0x00000745)
|
||||||
|
#define AQT1000_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI (0x00000745)
|
||||||
|
#define AQT1000_RX_NEW_INT_HPH_RDAC_BIAS_ULP (0x00000746)
|
||||||
|
#define AQT1000_RX_NEW_INT_HPH_RDAC_LDO_LP (0x00000747)
|
||||||
|
#define AQT1000_CLK_SYS_INT_BASE (0x0000076C)
|
||||||
|
#define AQT1000_CLK_SYS_INT_CLK_TEST1 (0x0000076C)
|
||||||
|
#define AQT1000_CLK_SYS_INT_XO_TEST1 (0x0000076D)
|
||||||
|
#define AQT1000_CLK_SYS_INT_XO_TEST2 (0x0000076E)
|
||||||
|
#define AQT1000_CLK_SYS_INT_POST_DIV_REG0 (0x0000076F)
|
||||||
|
#define AQT1000_CLK_SYS_INT_POST_DIV_REG1 (0x00000770)
|
||||||
|
#define AQT1000_CLK_SYS_INT_REF_DIV_REG0 (0x00000771)
|
||||||
|
#define AQT1000_CLK_SYS_INT_REF_DIV_REG1 (0x00000772)
|
||||||
|
#define AQT1000_CLK_SYS_INT_FILTER_REG0 (0x00000773)
|
||||||
|
#define AQT1000_CLK_SYS_INT_FILTER_REG1 (0x00000774)
|
||||||
|
#define AQT1000_CLK_SYS_INT_PLL_L_VAL (0x00000775)
|
||||||
|
#define AQT1000_CLK_SYS_INT_PLL_M_VAL (0x00000776)
|
||||||
|
#define AQT1000_CLK_SYS_INT_PLL_N_VAL (0x00000777)
|
||||||
|
#define AQT1000_CLK_SYS_INT_TEST_REG0 (0x00000778)
|
||||||
|
#define AQT1000_CLK_SYS_INT_PFD_CP_DSM_PROG (0x00000779)
|
||||||
|
#define AQT1000_CLK_SYS_INT_VCO_PROG (0x0000077A)
|
||||||
|
#define AQT1000_CLK_SYS_INT_TEST_REG1 (0x0000077B)
|
||||||
|
#define AQT1000_CLK_SYS_INT_LDO_LOCK_CFG (0x0000077C)
|
||||||
|
#define AQT1000_CLK_SYS_INT_DIG_LOCK_DET_CFG (0x0000077D)
|
||||||
|
#define AQT1000_MBHC_NEW_INT_BASE (0x000007AF)
|
||||||
|
#define AQT1000_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL (0x000007AF)
|
||||||
|
#define AQT1000_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL (0x000007B0)
|
||||||
|
#define AQT1000_MBHC_NEW_INT_MECH_DET_CURRENT (0x000007B1)
|
||||||
|
#define AQT1000_MBHC_NEW_INT_SPARE_2 (0x000007B2)
|
||||||
|
#define AQT1000_PAGE10_BASE (0x00000A00)
|
||||||
|
#define AQT1000_PAGE10_PAGE_REGISTER (0x00000A00)
|
||||||
|
#define AQT1000_CDC_ANC0_BASE (0x00000A01)
|
||||||
|
#define AQT1000_CDC_ANC0_CLK_RESET_CTL (0x00000A01)
|
||||||
|
#define AQT1000_CDC_ANC0_MODE_1_CTL (0x00000A02)
|
||||||
|
#define AQT1000_CDC_ANC0_MODE_2_CTL (0x00000A03)
|
||||||
|
#define AQT1000_CDC_ANC0_FF_SHIFT (0x00000A04)
|
||||||
|
#define AQT1000_CDC_ANC0_FB_SHIFT (0x00000A05)
|
||||||
|
#define AQT1000_CDC_ANC0_LPF_FF_A_CTL (0x00000A06)
|
||||||
|
#define AQT1000_CDC_ANC0_LPF_FF_B_CTL (0x00000A07)
|
||||||
|
#define AQT1000_CDC_ANC0_LPF_FB_CTL (0x00000A08)
|
||||||
|
#define AQT1000_CDC_ANC0_SMLPF_CTL (0x00000A09)
|
||||||
|
#define AQT1000_CDC_ANC0_DCFLT_SHIFT_CTL (0x00000A0A)
|
||||||
|
#define AQT1000_CDC_ANC0_IIR_ADAPT_CTL (0x00000A0B)
|
||||||
|
#define AQT1000_CDC_ANC0_IIR_COEFF_1_CTL (0x00000A0C)
|
||||||
|
#define AQT1000_CDC_ANC0_IIR_COEFF_2_CTL (0x00000A0D)
|
||||||
|
#define AQT1000_CDC_ANC0_FF_A_GAIN_CTL (0x00000A0E)
|
||||||
|
#define AQT1000_CDC_ANC0_FF_B_GAIN_CTL (0x00000A0F)
|
||||||
|
#define AQT1000_CDC_ANC0_FB_GAIN_CTL (0x00000A10)
|
||||||
|
#define AQT1000_CDC_ANC0_RC_COMMON_CTL (0x00000A11)
|
||||||
|
#define AQT1000_CDC_ANC0_FIFO_COMMON_CTL (0x00000A13)
|
||||||
|
#define AQT1000_CDC_ANC0_RC0_STATUS_FMIN_CNTR (0x00000A14)
|
||||||
|
#define AQT1000_CDC_ANC0_RC1_STATUS_FMIN_CNTR (0x00000A15)
|
||||||
|
#define AQT1000_CDC_ANC0_RC0_STATUS_FMAX_CNTR (0x00000A16)
|
||||||
|
#define AQT1000_CDC_ANC0_RC1_STATUS_FMAX_CNTR (0x00000A17)
|
||||||
|
#define AQT1000_CDC_ANC0_STATUS_FIFO (0x00000A18)
|
||||||
|
#define AQT1000_CDC_ANC1_BASE (0x00000A19)
|
||||||
|
#define AQT1000_CDC_ANC1_CLK_RESET_CTL (0x00000A19)
|
||||||
|
#define AQT1000_CDC_ANC1_MODE_1_CTL (0x00000A1A)
|
||||||
|
#define AQT1000_CDC_ANC1_MODE_2_CTL (0x00000A1B)
|
||||||
|
#define AQT1000_CDC_ANC1_FF_SHIFT (0x00000A1C)
|
||||||
|
#define AQT1000_CDC_ANC1_FB_SHIFT (0x00000A1D)
|
||||||
|
#define AQT1000_CDC_ANC1_LPF_FF_A_CTL (0x00000A1E)
|
||||||
|
#define AQT1000_CDC_ANC1_LPF_FF_B_CTL (0x00000A1F)
|
||||||
|
#define AQT1000_CDC_ANC1_LPF_FB_CTL (0x00000A20)
|
||||||
|
#define AQT1000_CDC_ANC1_SMLPF_CTL (0x00000A21)
|
||||||
|
#define AQT1000_CDC_ANC1_DCFLT_SHIFT_CTL (0x00000A22)
|
||||||
|
#define AQT1000_CDC_ANC1_IIR_ADAPT_CTL (0x00000A23)
|
||||||
|
#define AQT1000_CDC_ANC1_IIR_COEFF_1_CTL (0x00000A24)
|
||||||
|
#define AQT1000_CDC_ANC1_IIR_COEFF_2_CTL (0x00000A25)
|
||||||
|
#define AQT1000_CDC_ANC1_FF_A_GAIN_CTL (0x00000A26)
|
||||||
|
#define AQT1000_CDC_ANC1_FF_B_GAIN_CTL (0x00000A27)
|
||||||
|
#define AQT1000_CDC_ANC1_FB_GAIN_CTL (0x00000A28)
|
||||||
|
#define AQT1000_CDC_ANC1_RC_COMMON_CTL (0x00000A29)
|
||||||
|
#define AQT1000_CDC_ANC1_FIFO_COMMON_CTL (0x00000A2B)
|
||||||
|
#define AQT1000_CDC_ANC1_RC0_STATUS_FMIN_CNTR (0x00000A2C)
|
||||||
|
#define AQT1000_CDC_ANC1_RC1_STATUS_FMIN_CNTR (0x00000A2D)
|
||||||
|
#define AQT1000_CDC_ANC1_RC0_STATUS_FMAX_CNTR (0x00000A2E)
|
||||||
|
#define AQT1000_CDC_ANC1_RC1_STATUS_FMAX_CNTR (0x00000A2F)
|
||||||
|
#define AQT1000_CDC_ANC1_STATUS_FIFO (0x00000A30)
|
||||||
|
#define AQT1000_CDC_TX0_BASE (0x00000A31)
|
||||||
|
#define AQT1000_CDC_TX0_TX_PATH_CTL (0x00000A31)
|
||||||
|
#define AQT1000_CDC_TX0_TX_PATH_CFG0 (0x00000A32)
|
||||||
|
#define AQT1000_CDC_TX0_TX_PATH_CFG1 (0x00000A33)
|
||||||
|
#define AQT1000_CDC_TX0_TX_VOL_CTL (0x00000A34)
|
||||||
|
#define AQT1000_CDC_TX0_TX_PATH_SEC0 (0x00000A37)
|
||||||
|
#define AQT1000_CDC_TX0_TX_PATH_SEC1 (0x00000A38)
|
||||||
|
#define AQT1000_CDC_TX0_TX_PATH_SEC2 (0x00000A39)
|
||||||
|
#define AQT1000_CDC_TX0_TX_PATH_SEC3 (0x00000A3A)
|
||||||
|
#define AQT1000_CDC_TX0_TX_PATH_SEC4 (0x00000A3B)
|
||||||
|
#define AQT1000_CDC_TX0_TX_PATH_SEC5 (0x00000A3C)
|
||||||
|
#define AQT1000_CDC_TX0_TX_PATH_SEC6 (0x00000A3D)
|
||||||
|
#define AQT1000_CDC_TX1_BASE (0x00000A41)
|
||||||
|
#define AQT1000_CDC_TX1_TX_PATH_CTL (0x00000A41)
|
||||||
|
#define AQT1000_CDC_TX1_TX_PATH_CFG0 (0x00000A42)
|
||||||
|
#define AQT1000_CDC_TX1_TX_PATH_CFG1 (0x00000A43)
|
||||||
|
#define AQT1000_CDC_TX1_TX_VOL_CTL (0x00000A44)
|
||||||
|
#define AQT1000_CDC_TX1_TX_PATH_SEC0 (0x00000A47)
|
||||||
|
#define AQT1000_CDC_TX1_TX_PATH_SEC1 (0x00000A48)
|
||||||
|
#define AQT1000_CDC_TX1_TX_PATH_SEC2 (0x00000A49)
|
||||||
|
#define AQT1000_CDC_TX1_TX_PATH_SEC3 (0x00000A4A)
|
||||||
|
#define AQT1000_CDC_TX1_TX_PATH_SEC4 (0x00000A4B)
|
||||||
|
#define AQT1000_CDC_TX1_TX_PATH_SEC5 (0x00000A4C)
|
||||||
|
#define AQT1000_CDC_TX1_TX_PATH_SEC6 (0x00000A4D)
|
||||||
|
#define AQT1000_CDC_TX2_BASE (0x00000A51)
|
||||||
|
#define AQT1000_CDC_TX2_TX_PATH_CTL (0x00000A51)
|
||||||
|
#define AQT1000_CDC_TX2_TX_PATH_CFG0 (0x00000A52)
|
||||||
|
#define AQT1000_CDC_TX2_TX_PATH_CFG1 (0x00000A53)
|
||||||
|
#define AQT1000_CDC_TX2_TX_VOL_CTL (0x00000A54)
|
||||||
|
#define AQT1000_CDC_TX2_TX_PATH_SEC0 (0x00000A57)
|
||||||
|
#define AQT1000_CDC_TX2_TX_PATH_SEC1 (0x00000A58)
|
||||||
|
#define AQT1000_CDC_TX2_TX_PATH_SEC2 (0x00000A59)
|
||||||
|
#define AQT1000_CDC_TX2_TX_PATH_SEC3 (0x00000A5A)
|
||||||
|
#define AQT1000_CDC_TX2_TX_PATH_SEC4 (0x00000A5B)
|
||||||
|
#define AQT1000_CDC_TX2_TX_PATH_SEC5 (0x00000A5C)
|
||||||
|
#define AQT1000_CDC_TX2_TX_PATH_SEC6 (0x00000A5D)
|
||||||
|
#define AQT1000_CDC_TX2_TX_PATH_SEC7 (0x00000A5E)
|
||||||
|
#define AQT1000_PAGE11_BASE (0x00000B00)
|
||||||
|
#define AQT1000_PAGE11_PAGE_REGISTER (0x00000B00)
|
||||||
|
#define AQT1000_CDC_COMPANDER1_BASE (0x00000B01)
|
||||||
|
#define AQT1000_CDC_COMPANDER1_CTL0 (0x00000B01)
|
||||||
|
#define AQT1000_CDC_COMPANDER1_CTL1 (0x00000B02)
|
||||||
|
#define AQT1000_CDC_COMPANDER1_CTL2 (0x00000B03)
|
||||||
|
#define AQT1000_CDC_COMPANDER1_CTL3 (0x00000B04)
|
||||||
|
#define AQT1000_CDC_COMPANDER1_CTL4 (0x00000B05)
|
||||||
|
#define AQT1000_CDC_COMPANDER1_CTL5 (0x00000B06)
|
||||||
|
#define AQT1000_CDC_COMPANDER1_CTL6 (0x00000B07)
|
||||||
|
#define AQT1000_CDC_COMPANDER1_CTL7 (0x00000B08)
|
||||||
|
#define AQT1000_CDC_COMPANDER2_BASE (0x00000B09)
|
||||||
|
#define AQT1000_CDC_COMPANDER2_CTL0 (0x00000B09)
|
||||||
|
#define AQT1000_CDC_COMPANDER2_CTL1 (0x00000B0A)
|
||||||
|
#define AQT1000_CDC_COMPANDER2_CTL2 (0x00000B0B)
|
||||||
|
#define AQT1000_CDC_COMPANDER2_CTL3 (0x00000B0C)
|
||||||
|
#define AQT1000_CDC_COMPANDER2_CTL4 (0x00000B0D)
|
||||||
|
#define AQT1000_CDC_COMPANDER2_CTL5 (0x00000B0E)
|
||||||
|
#define AQT1000_CDC_COMPANDER2_CTL6 (0x00000B0F)
|
||||||
|
#define AQT1000_CDC_COMPANDER2_CTL7 (0x00000B10)
|
||||||
|
#define AQT1000_CDC_RX1_BASE (0x00000B55)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_CTL (0x00000B55)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_CFG0 (0x00000B56)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_CFG1 (0x00000B57)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_CFG2 (0x00000B58)
|
||||||
|
#define AQT1000_CDC_RX1_RX_VOL_CTL (0x00000B59)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_MIX_CTL (0x00000B5A)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_MIX_CFG (0x00000B5B)
|
||||||
|
#define AQT1000_CDC_RX1_RX_VOL_MIX_CTL (0x00000B5C)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_SEC0 (0x00000B5D)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_SEC1 (0x00000B5E)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_SEC2 (0x00000B5F)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_SEC3 (0x00000B60)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_SEC4 (0x00000B61)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_SEC5 (0x00000B62)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_SEC6 (0x00000B63)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_SEC7 (0x00000B64)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_MIX_SEC0 (0x00000B65)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_MIX_SEC1 (0x00000B66)
|
||||||
|
#define AQT1000_CDC_RX1_RX_PATH_DSMDEM_CTL (0x00000B67)
|
||||||
|
#define AQT1000_CDC_RX2_BASE (0x00000B69)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_CTL (0x00000B69)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_CFG0 (0x00000B6A)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_CFG1 (0x00000B6B)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_CFG2 (0x00000B6C)
|
||||||
|
#define AQT1000_CDC_RX2_RX_VOL_CTL (0x00000B6D)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_MIX_CTL (0x00000B6E)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_MIX_CFG (0x00000B6F)
|
||||||
|
#define AQT1000_CDC_RX2_RX_VOL_MIX_CTL (0x00000B70)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_SEC0 (0x00000B71)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_SEC1 (0x00000B72)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_SEC2 (0x00000B73)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_SEC3 (0x00000B74)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_SEC4 (0x00000B75)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_SEC5 (0x00000B76)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_SEC6 (0x00000B77)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_SEC7 (0x00000B78)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_MIX_SEC0 (0x00000B79)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_MIX_SEC1 (0x00000B7A)
|
||||||
|
#define AQT1000_CDC_RX2_RX_PATH_DSMDEM_CTL (0x00000B7B)
|
||||||
|
#define AQT1000_CDC_EQ_IIR0_BASE (0x00000BD1)
|
||||||
|
#define AQT1000_CDC_EQ_IIR0_PATH_CTL (0x00000BD1)
|
||||||
|
#define AQT1000_CDC_EQ_IIR0_PATH_CFG0 (0x00000BD2)
|
||||||
|
#define AQT1000_CDC_EQ_IIR0_PATH_CFG1 (0x00000BD3)
|
||||||
|
#define AQT1000_CDC_EQ_IIR0_PATH_CFG2 (0x00000BD4)
|
||||||
|
#define AQT1000_CDC_EQ_IIR0_PATH_CFG3 (0x00000BD5)
|
||||||
|
#define AQT1000_CDC_EQ_IIR0_COEF_CFG0 (0x00000BD6)
|
||||||
|
#define AQT1000_CDC_EQ_IIR0_COEF_CFG1 (0x00000BD7)
|
||||||
|
#define AQT1000_CDC_EQ_IIR1_BASE (0x00000BE1)
|
||||||
|
#define AQT1000_CDC_EQ_IIR1_PATH_CTL (0x00000BE1)
|
||||||
|
#define AQT1000_CDC_EQ_IIR1_PATH_CFG0 (0x00000BE2)
|
||||||
|
#define AQT1000_CDC_EQ_IIR1_PATH_CFG1 (0x00000BE3)
|
||||||
|
#define AQT1000_CDC_EQ_IIR1_PATH_CFG2 (0x00000BE4)
|
||||||
|
#define AQT1000_CDC_EQ_IIR1_PATH_CFG3 (0x00000BE5)
|
||||||
|
#define AQT1000_CDC_EQ_IIR1_COEF_CFG0 (0x00000BE6)
|
||||||
|
#define AQT1000_CDC_EQ_IIR1_COEF_CFG1 (0x00000BE7)
|
||||||
|
#define AQT1000_PAGE12_BASE (0x00000C00)
|
||||||
|
#define AQT1000_PAGE12_PAGE_REGISTER (0x00000C00)
|
||||||
|
#define AQT1000_CDC_CLSH_CDC_CLSH_BASE (0x00000C01)
|
||||||
|
#define AQT1000_CDC_CLSH_CRC (0x00000C01)
|
||||||
|
#define AQT1000_CDC_CLSH_DLY_CTRL (0x00000C02)
|
||||||
|
#define AQT1000_CDC_CLSH_DECAY_CTRL (0x00000C03)
|
||||||
|
#define AQT1000_CDC_CLSH_HPH_V_PA (0x00000C04)
|
||||||
|
#define AQT1000_CDC_CLSH_EAR_V_PA (0x00000C05)
|
||||||
|
#define AQT1000_CDC_CLSH_HPH_V_HD (0x00000C06)
|
||||||
|
#define AQT1000_CDC_CLSH_EAR_V_HD (0x00000C07)
|
||||||
|
#define AQT1000_CDC_CLSH_K1_MSB (0x00000C08)
|
||||||
|
#define AQT1000_CDC_CLSH_K1_LSB (0x00000C09)
|
||||||
|
#define AQT1000_CDC_CLSH_K2_MSB (0x00000C0A)
|
||||||
|
#define AQT1000_CDC_CLSH_K2_LSB (0x00000C0B)
|
||||||
|
#define AQT1000_CDC_CLSH_IDLE_CTRL (0x00000C0C)
|
||||||
|
#define AQT1000_CDC_CLSH_IDLE_HPH (0x00000C0D)
|
||||||
|
#define AQT1000_CDC_CLSH_IDLE_EAR (0x00000C0E)
|
||||||
|
#define AQT1000_CDC_CLSH_TEST0 (0x00000C0F)
|
||||||
|
#define AQT1000_CDC_CLSH_TEST1 (0x00000C10)
|
||||||
|
#define AQT1000_CDC_CLSH_OVR_VREF (0x00000C11)
|
||||||
|
#define AQT1000_MIXING_ASRC0_BASE (0x00000C55)
|
||||||
|
#define AQT1000_MIXING_ASRC0_CLK_RST_CTL (0x00000C55)
|
||||||
|
#define AQT1000_MIXING_ASRC0_CTL0 (0x00000C56)
|
||||||
|
#define AQT1000_MIXING_ASRC0_CTL1 (0x00000C57)
|
||||||
|
#define AQT1000_MIXING_ASRC0_FIFO_CTL (0x00000C58)
|
||||||
|
#define AQT1000_MIXING_ASRC0_STATUS_FMIN_CNTR_LSB (0x00000C59)
|
||||||
|
#define AQT1000_MIXING_ASRC0_STATUS_FMIN_CNTR_MSB (0x00000C5A)
|
||||||
|
#define AQT1000_MIXING_ASRC0_STATUS_FMAX_CNTR_LSB (0x00000C5B)
|
||||||
|
#define AQT1000_MIXING_ASRC0_STATUS_FMAX_CNTR_MSB (0x00000C5C)
|
||||||
|
#define AQT1000_MIXING_ASRC0_STATUS_FIFO (0x00000C5D)
|
||||||
|
#define AQT1000_MIXING_ASRC1_BASE (0x00000C61)
|
||||||
|
#define AQT1000_MIXING_ASRC1_CLK_RST_CTL (0x00000C61)
|
||||||
|
#define AQT1000_MIXING_ASRC1_CTL0 (0x00000C62)
|
||||||
|
#define AQT1000_MIXING_ASRC1_CTL1 (0x00000C63)
|
||||||
|
#define AQT1000_MIXING_ASRC1_FIFO_CTL (0x00000C64)
|
||||||
|
#define AQT1000_MIXING_ASRC1_STATUS_FMIN_CNTR_LSB (0x00000C65)
|
||||||
|
#define AQT1000_MIXING_ASRC1_STATUS_FMIN_CNTR_MSB (0x00000C66)
|
||||||
|
#define AQT1000_MIXING_ASRC1_STATUS_FMAX_CNTR_LSB (0x00000C67)
|
||||||
|
#define AQT1000_MIXING_ASRC1_STATUS_FMAX_CNTR_MSB (0x00000C68)
|
||||||
|
#define AQT1000_MIXING_ASRC1_STATUS_FIFO (0x00000C69)
|
||||||
|
#define AQT1000_CDC_SIDETONE_SRC0_BASE (0x00000CB5)
|
||||||
|
#define AQT1000_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL (0x00000CB5)
|
||||||
|
#define AQT1000_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1 (0x00000CB6)
|
||||||
|
#define AQT1000_SIDETONE_ASRC0_BASE (0x00000CBD)
|
||||||
|
#define AQT1000_SIDETONE_ASRC0_CLK_RST_CTL (0x00000CBD)
|
||||||
|
#define AQT1000_SIDETONE_ASRC0_CTL0 (0x00000CBE)
|
||||||
|
#define AQT1000_SIDETONE_ASRC0_CTL1 (0x00000CBF)
|
||||||
|
#define AQT1000_SIDETONE_ASRC0_FIFO_CTL (0x00000CC0)
|
||||||
|
#define AQT1000_SIDETONE_ASRC0_STATUS_FMIN_CNTR_LSB (0x00000CC1)
|
||||||
|
#define AQT1000_SIDETONE_ASRC0_STATUS_FMIN_CNTR_MSB (0x00000CC2)
|
||||||
|
#define AQT1000_SIDETONE_ASRC0_STATUS_FMAX_CNTR_LSB (0x00000CC3)
|
||||||
|
#define AQT1000_SIDETONE_ASRC0_STATUS_FMAX_CNTR_MSB (0x00000CC4)
|
||||||
|
#define AQT1000_SIDETONE_ASRC0_STATUS_FIFO (0x00000CC5)
|
||||||
|
#define AQT1000_EC_REF_HQ0_BASE (0x00000CD5)
|
||||||
|
#define AQT1000_EC_REF_HQ0_EC_REF_HQ_PATH_CTL (0x00000CD5)
|
||||||
|
#define AQT1000_EC_REF_HQ0_EC_REF_HQ_CFG0 (0x00000CD6)
|
||||||
|
#define AQT1000_EC_REF_HQ1_BASE (0x00000CDD)
|
||||||
|
#define AQT1000_EC_REF_HQ1_EC_REF_HQ_PATH_CTL (0x00000CDD)
|
||||||
|
#define AQT1000_EC_REF_HQ1_EC_REF_HQ_CFG0 (0x00000CDE)
|
||||||
|
#define AQT1000_EC_ASRC0_BASE (0x00000CE5)
|
||||||
|
#define AQT1000_EC_ASRC0_CLK_RST_CTL (0x00000CE5)
|
||||||
|
#define AQT1000_EC_ASRC0_CTL0 (0x00000CE6)
|
||||||
|
#define AQT1000_EC_ASRC0_CTL1 (0x00000CE7)
|
||||||
|
#define AQT1000_EC_ASRC0_FIFO_CTL (0x00000CE8)
|
||||||
|
#define AQT1000_EC_ASRC0_STATUS_FMIN_CNTR_LSB (0x00000CE9)
|
||||||
|
#define AQT1000_EC_ASRC0_STATUS_FMIN_CNTR_MSB (0x00000CEA)
|
||||||
|
#define AQT1000_EC_ASRC0_STATUS_FMAX_CNTR_LSB (0x00000CEB)
|
||||||
|
#define AQT1000_EC_ASRC0_STATUS_FMAX_CNTR_MSB (0x00000CEC)
|
||||||
|
#define AQT1000_EC_ASRC0_STATUS_FIFO (0x00000CED)
|
||||||
|
#define AQT1000_EC_ASRC1_BASE (0x00000CF1)
|
||||||
|
#define AQT1000_EC_ASRC1_CLK_RST_CTL (0x00000CF1)
|
||||||
|
#define AQT1000_EC_ASRC1_CTL0 (0x00000CF2)
|
||||||
|
#define AQT1000_EC_ASRC1_CTL1 (0x00000CF3)
|
||||||
|
#define AQT1000_EC_ASRC1_FIFO_CTL (0x00000CF4)
|
||||||
|
#define AQT1000_EC_ASRC1_STATUS_FMIN_CNTR_LSB (0x00000CF5)
|
||||||
|
#define AQT1000_EC_ASRC1_STATUS_FMIN_CNTR_MSB (0x00000CF6)
|
||||||
|
#define AQT1000_EC_ASRC1_STATUS_FMAX_CNTR_LSB (0x00000CF7)
|
||||||
|
#define AQT1000_EC_ASRC1_STATUS_FMAX_CNTR_MSB (0x00000CF8)
|
||||||
|
#define AQT1000_EC_ASRC1_STATUS_FIFO (0x00000CF9)
|
||||||
|
#define AQT1000_PAGE13_BASE (0x00000D00)
|
||||||
|
#define AQT1000_PAGE13_PAGE_REGISTER (0x00000D00)
|
||||||
|
#define AQT1000_CDC_RX_INP_MUX_CDC_RX_INP_MUX_BASE (0x00000D01)
|
||||||
|
#define AQT1000_CDC_RX_INP_MUX_RX_INT1_CFG0 (0x00000D03)
|
||||||
|
#define AQT1000_CDC_RX_INP_MUX_RX_INT1_CFG1 (0x00000D04)
|
||||||
|
#define AQT1000_CDC_RX_INP_MUX_RX_INT2_CFG0 (0x00000D05)
|
||||||
|
#define AQT1000_CDC_RX_INP_MUX_RX_INT2_CFG1 (0x00000D06)
|
||||||
|
#define AQT1000_CDC_RX_INP_MUX_EQ_IIR_CFG0 (0x00000D11)
|
||||||
|
#define AQT1000_CDC_RX_INP_MUX_DSD_CFG0 (0x00000D12)
|
||||||
|
#define AQT1000_CDC_RX_INP_MUX_RX_MIX_CFG0 (0x00000D13)
|
||||||
|
#define AQT1000_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 (0x00000D18)
|
||||||
|
#define AQT1000_CDC_RX_INP_MUX_ANC_CFG0 (0x00000D1A)
|
||||||
|
#define AQT1000_CDC_RX_INP_MUX_SPLINE_ASRC_CFG0 (0x00000D1B)
|
||||||
|
#define AQT1000_CDC_RX_INP_MUX_EC_REF_HQ_CFG0 (0x00000D1C)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_CDC_TX_INP_MUX_BASE (0x00000D1D)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x00000D1D)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x00000D1E)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_ADC_MUX1_CFG0 (0x00000D1F)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_ADC_MUX1_CFG1 (0x00000D20)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_ADC_MUX2_CFG0 (0x00000D21)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_ADC_MUX2_CFG1 (0x00000D22)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_ADC_MUX10_CFG0 (0x00000D29)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_ADC_MUX10_CFG1 (0x00000D2A)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_ADC_MUX11_CFG0 (0x00000D2B)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_ADC_MUX11_CFG1 (0x00000D2C)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_ADC_MUX12_CFG0 (0x00000D2D)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_ADC_MUX12_CFG1 (0x00000D2E)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_ADC_MUX13_CFG0 (0x00000D2F)
|
||||||
|
#define AQT1000_CDC_TX_INP_MUX_ADC_MUX13_CFG1 (0x00000D30)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR_INP_MUX_CDC_SIDETONE_IIR_INP_MUX_BASE (0xD31)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0 (0x00000D31)
|
||||||
|
#define AQT1000_CDC_IF_ROUTER_CDC_IF_ROUTER_BASE (0x00000D3D)
|
||||||
|
#define AQT1000_CDC_IF_ROUTER_TX_MUX_CFG0 (0x00000D3D)
|
||||||
|
#define AQT1000_CDC_CLK_RST_CTRL_CDC_CLK_RST_CTRL_BASE (0x00000D41)
|
||||||
|
#define AQT1000_CDC_CLK_RST_CTRL_MCLK_CONTROL (0x00000D41)
|
||||||
|
#define AQT1000_CDC_CLK_RST_CTRL_FS_CNT_CONTROL (0x00000D42)
|
||||||
|
#define AQT1000_CDC_CLK_RST_CTRL_DSD_CONTROL (0x00000D44)
|
||||||
|
#define AQT1000_CDC_CLK_RST_CTRL_ASRC_SHARE_CONTROL (0x00000D45)
|
||||||
|
#define AQT1000_CDC_CLK_RST_CTRL_GFM_CONTROL (0x00000D46)
|
||||||
|
#define AQT1000_CDC_CLK_RST_CTRL_I2S_CONTROL (0x00000D47)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR0_BASE (0x00000D55)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR0_IIR_PATH_CTL (0x00000D55)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL (0x00000D56)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL (0x00000D57)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL (0x00000D58)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL (0x00000D59)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL (0x00000D5A)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL (0x00000D5B)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL (0x00000D5C)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL (0x00000D5D)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR0_IIR_CTL (0x00000D5E)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL (0x00000D5F)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL (0x00000D60)
|
||||||
|
#define AQT1000_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL (0x00000D61)
|
||||||
|
#define AQT1000_CDC_TOP_CDC_TOP_BASE (0x00000D81)
|
||||||
|
#define AQT1000_CDC_TOP_TOP_CFG0 (0x00000D81)
|
||||||
|
#define AQT1000_CDC_TOP_HPHL_COMP_WR_LSB (0x00000D89)
|
||||||
|
#define AQT1000_CDC_TOP_HPHL_COMP_WR_MSB (0x00000D8A)
|
||||||
|
#define AQT1000_CDC_TOP_HPHL_COMP_LUT (0x00000D8B)
|
||||||
|
#define AQT1000_CDC_TOP_HPHL_COMP_RD_LSB (0x00000D8C)
|
||||||
|
#define AQT1000_CDC_TOP_HPHL_COMP_RD_MSB (0x00000D8D)
|
||||||
|
#define AQT1000_CDC_TOP_HPHR_COMP_WR_LSB (0x00000D8E)
|
||||||
|
#define AQT1000_CDC_TOP_HPHR_COMP_WR_MSB (0x00000D8F)
|
||||||
|
#define AQT1000_CDC_TOP_HPHR_COMP_LUT (0x00000D90)
|
||||||
|
#define AQT1000_CDC_TOP_HPHR_COMP_RD_LSB (0x00000D91)
|
||||||
|
#define AQT1000_CDC_TOP_HPHR_COMP_RD_MSB (0x00000D92)
|
||||||
|
#define AQT1000_CDC_DSD0_BASE (0x00000DB1)
|
||||||
|
#define AQT1000_CDC_DSD0_PATH_CTL (0x00000DB1)
|
||||||
|
#define AQT1000_CDC_DSD0_CFG0 (0x00000DB2)
|
||||||
|
#define AQT1000_CDC_DSD0_CFG1 (0x00000DB3)
|
||||||
|
#define AQT1000_CDC_DSD0_CFG2 (0x00000DB4)
|
||||||
|
#define AQT1000_CDC_DSD0_CFG3 (0x00000DB5)
|
||||||
|
#define AQT1000_CDC_DSD0_CFG4 (0x00000DB6)
|
||||||
|
#define AQT1000_CDC_DSD0_CFG5 (0x00000DB7)
|
||||||
|
#define AQT1000_CDC_DSD1_BASE (0x00000DC1)
|
||||||
|
#define AQT1000_CDC_DSD1_PATH_CTL (0x00000DC1)
|
||||||
|
#define AQT1000_CDC_DSD1_CFG0 (0x00000DC2)
|
||||||
|
#define AQT1000_CDC_DSD1_CFG1 (0x00000DC3)
|
||||||
|
#define AQT1000_CDC_DSD1_CFG2 (0x00000DC4)
|
||||||
|
#define AQT1000_CDC_DSD1_CFG3 (0x00000DC5)
|
||||||
|
#define AQT1000_CDC_DSD1_CFG4 (0x00000DC6)
|
||||||
|
#define AQT1000_CDC_DSD1_CFG5 (0x00000DC7)
|
||||||
|
#define AQT1000_CDC_RX_IDLE_DET_CDC_RX_IDLE_DET_BASE (0x00000DD1)
|
||||||
|
#define AQT1000_CDC_RX_IDLE_DET_PATH_CTL (0x00000DD1)
|
||||||
|
#define AQT1000_CDC_RX_IDLE_DET_CFG0 (0x00000DD2)
|
||||||
|
#define AQT1000_CDC_RX_IDLE_DET_CFG1 (0x00000DD3)
|
||||||
|
#define AQT1000_CDC_RX_IDLE_DET_CFG2 (0x00000DD4)
|
||||||
|
#define AQT1000_CDC_RX_IDLE_DET_CFG3 (0x00000DD5)
|
||||||
|
#define AQT1000_CDC_DOP_DET_CDC_DOP_DET_BASE (0x00000DD9)
|
||||||
|
#define AQT1000_CDC_DOP_DET_CTL (0x00000DD9)
|
||||||
|
#define AQT1000_CDC_DOP_DET_CFG0 (0x00000DDA)
|
||||||
|
#define AQT1000_CDC_DOP_DET_CFG1 (0x00000DDB)
|
||||||
|
#define AQT1000_CDC_DOP_DET_CFG2 (0x00000DDC)
|
||||||
|
#define AQT1000_CDC_DOP_DET_CFG3 (0x00000DDD)
|
||||||
|
#define AQT1000_CDC_DOP_DET_CFG4 (0x00000DDE)
|
||||||
|
#define AQT1000_CDC_DOP_DET_STATUS0 (0x00000DE1)
|
||||||
|
#define AQT1000_PAGE15_BASE (0x00000F00)
|
||||||
|
#define AQT1000_PAGE15_PAGE_REGISTER (0x00000F00)
|
||||||
|
#define AQT1000_CDC_DEBUG_CDC_DEBUG_BASE (0x00000FA1)
|
||||||
|
#define AQT1000_CDC_DEBUG_DSD0_DEBUG_CFG0 (0x00000FA1)
|
||||||
|
#define AQT1000_CDC_DEBUG_DSD0_DEBUG_CFG1 (0x00000FA2)
|
||||||
|
#define AQT1000_CDC_DEBUG_DSD0_DEBUG_CFG2 (0x00000FA3)
|
||||||
|
#define AQT1000_CDC_DEBUG_DSD0_DEBUG_CFG3 (0x00000FA4)
|
||||||
|
#define AQT1000_CDC_DEBUG_DSD1_DEBUG_CFG0 (0x00000FA5)
|
||||||
|
#define AQT1000_CDC_DEBUG_DSD1_DEBUG_CFG1 (0x00000FA6)
|
||||||
|
#define AQT1000_CDC_DEBUG_DSD1_DEBUG_CFG2 (0x00000FA7)
|
||||||
|
#define AQT1000_CDC_DEBUG_DSD1_DEBUG_CFG3 (0x00000FA8)
|
||||||
|
#define AQT1000_CDC_DEBUG_RC_RE_ASRC_DEBUG_CFG0 (0x00000FAB)
|
||||||
|
#define AQT1000_CDC_DEBUG_ANC0_RC0_FIFO_CTL (0x00000FAC)
|
||||||
|
#define AQT1000_CDC_DEBUG_ANC0_RC1_FIFO_CTL (0x00000FAD)
|
||||||
|
#define AQT1000_CDC_DEBUG_ANC1_RC0_FIFO_CTL (0x00000FAE)
|
||||||
|
#define AQT1000_CDC_DEBUG_ANC1_RC1_FIFO_CTL (0x00000FAF)
|
||||||
|
#define AQT1000_CDC_DEBUG_ANC_RC_RST_DBG_CNTR (0x00000FB0)
|
||||||
|
#define AQT1000_PAGE128_BASE (0x00008000)
|
||||||
|
#define AQT1000_PAGE128_PAGE_REGISTER (0x00008000)
|
||||||
|
#define AQT1000_TLMM_TLMM_BASE (0x00008001)
|
||||||
|
#define AQT1000_TLMM_SPI_CLK_PINCFG (0x00008001)
|
||||||
|
#define AQT1000_TLMM_SPI_MOSI_PINCFG (0x00008002)
|
||||||
|
#define AQT1000_TLMM_SPI_MISO_PINCFG (0x00008003)
|
||||||
|
#define AQT1000_TLMM_SPI_CS_N_PINCFG (0x00008004)
|
||||||
|
#define AQT1000_TLMM_GPIO1_PINCFG (0x00008005)
|
||||||
|
#define AQT1000_TLMM_GPIO2_PINCFG (0x00008006)
|
||||||
|
#define AQT1000_TLMM_GPIO3_PINCFG (0x00008007)
|
||||||
|
#define AQT1000_TLMM_GPIO4_PINCFG (0x00008008)
|
||||||
|
#define AQT1000_TLMM_GPIO5_PINCFG (0x00008009)
|
||||||
|
#define AQT1000_TLMM_GPIO6_PINCFG (0x0000800A)
|
||||||
|
#define AQT1000_TLMM_GPIO7_PINCFG (0x0000800B)
|
||||||
|
#define AQT1000_TLMM_GPIO8_PINCFG (0x0000800C)
|
||||||
|
#define AQT1000_TLMM_GPIO9_PINCFG (0x0000800D)
|
||||||
|
#define AQT1000_TLMM_GPIO10_PINCFG (0x0000800E)
|
||||||
|
#define AQT1000_PAD_CTRL_PAD_CTRL_BASE (0x00008031)
|
||||||
|
#define AQT1000_PAD_CTRL_PAD_PDN_CTRL_0 (0x00008031)
|
||||||
|
#define AQT1000_PAD_CTRL_PAD_PDN_CTRL_1 (0x00008032)
|
||||||
|
#define AQT1000_PAD_CTRL_PAD_PU_CTRL_0 (0x00008033)
|
||||||
|
#define AQT1000_PAD_CTRL_PAD_PU_CTRL_1 (0x00008034)
|
||||||
|
#define AQT1000_PAD_CTRL_GPIO_CTL_0_OE (0x00008036)
|
||||||
|
#define AQT1000_PAD_CTRL_GPIO_CTL_1_OE (0x00008037)
|
||||||
|
#define AQT1000_PAD_CTRL_GPIO_CTL_0_DATA (0x00008038)
|
||||||
|
#define AQT1000_PAD_CTRL_GPIO_CTL_1_DATA (0x00008039)
|
||||||
|
#define AQT1000_PAD_CTRL_PAD_DRVCTL (0x0000803A)
|
||||||
|
#define AQT1000_PAD_CTRL_PIN_STATUS (0x0000803B)
|
||||||
|
#define AQT1000_PAD_CTRL_MEM_CTRL (0x0000803C)
|
||||||
|
#define AQT1000_PAD_CTRL_PAD_INP_DISABLE_0 (0x0000803E)
|
||||||
|
#define AQT1000_PAD_CTRL_PAD_INP_DISABLE_1 (0x0000803F)
|
||||||
|
#define AQT1000_PAD_CTRL_PIN_CTL_OE_0 (0x00008040)
|
||||||
|
#define AQT1000_PAD_CTRL_PIN_CTL_OE_1 (0x00008041)
|
||||||
|
#define AQT1000_PAD_CTRL_PIN_CTL_DATA_0 (0x00008042)
|
||||||
|
#define AQT1000_PAD_CTRL_PIN_CTL_DATA_1 (0x00008043)
|
||||||
|
#define AQT1000_PAD_CTRL_USB_PHY_CLK_DIV (0x00008044)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_BUS_CDC (0x00008045)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_BUS_SEL (0x00008046)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_EN_1 (0x00008047)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_EN_2 (0x00008048)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_EN_3 (0x00008049)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_EN_4 (0x0000804A)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_EN_5 (0x0000804B)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_0 (0x0000804C)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_1 (0x0000804D)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_2 (0x0000804E)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_3 (0x0000804F)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_4 (0x00008050)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_5 (0x00008051)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_6 (0x00008052)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_7 (0x00008053)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_8 (0x00008054)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_9 (0x00008055)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_10 (0x00008056)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_11 (0x00008057)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_12 (0x00008058)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_13 (0x00008059)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_READ_0 (0x0000805A)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_READ_1 (0x0000805B)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_READ_2 (0x0000805C)
|
||||||
|
#define AQT1000_PAD_CTRL_DEBUG_READ_3 (0x0000805D)
|
||||||
|
#define AQT1000_PAD_CTRL_FPGA_CTL (0x00008061)
|
||||||
|
#define AQT1000_MAX_REGISTER (0x000080FF)
|
||||||
|
|
||||||
|
#endif /*_AQT_REGISTERS_H*/
|
||||||
110
asoc/codecs/aqt1000/aqt1000-regmap.c
Normal file
110
asoc/codecs/aqt1000/aqt1000-regmap.c
Normal file
@@ -0,0 +1,110 @@
|
|||||||
|
/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/regmap.h>
|
||||||
|
#include <linux/device.h>
|
||||||
|
#include "aqt1000-registers.h"
|
||||||
|
#include "aqt1000-reg-defaults.h"
|
||||||
|
#include "aqt1000-internal.h"
|
||||||
|
|
||||||
|
static bool aqt1000_is_readable_register(struct device *dev, unsigned int reg)
|
||||||
|
{
|
||||||
|
u8 pg_num, reg_offset;
|
||||||
|
const u8 *reg_tbl = NULL;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Get the page number from MSB of codec register. If its 0x80, assign
|
||||||
|
* the corresponding page index PAGE_0x80.
|
||||||
|
*/
|
||||||
|
pg_num = reg >> 0x8;
|
||||||
|
if (pg_num == 0x80)
|
||||||
|
pg_num = AQT1000_PAGE_128;
|
||||||
|
else if (pg_num > 15)
|
||||||
|
return false;
|
||||||
|
|
||||||
|
reg_tbl = aqt1000_reg[pg_num];
|
||||||
|
reg_offset = reg & 0xFF;
|
||||||
|
|
||||||
|
if (reg_tbl && reg_tbl[reg_offset])
|
||||||
|
return true;
|
||||||
|
else
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool aqt1000_is_volatile_register(struct device *dev, unsigned int reg)
|
||||||
|
{
|
||||||
|
u8 pg_num, reg_offset;
|
||||||
|
const u8 *reg_tbl = NULL;
|
||||||
|
|
||||||
|
pg_num = reg >> 0x8;
|
||||||
|
if (pg_num == 0x80)
|
||||||
|
pg_num = AQT1000_PAGE_128;
|
||||||
|
else if (pg_num > 15)
|
||||||
|
return false;
|
||||||
|
|
||||||
|
reg_tbl = aqt1000_reg[pg_num];
|
||||||
|
reg_offset = reg & 0xFF;
|
||||||
|
|
||||||
|
if (reg_tbl && reg_tbl[reg_offset] == AQT1000_RO)
|
||||||
|
return true;
|
||||||
|
|
||||||
|
/* IIR Coeff registers are not cacheable */
|
||||||
|
if ((reg >= AQT1000_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL) &&
|
||||||
|
(reg <= AQT1000_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL))
|
||||||
|
return true;
|
||||||
|
|
||||||
|
if ((reg >= AQT1000_CDC_ANC0_IIR_COEFF_1_CTL) &&
|
||||||
|
(reg <= AQT1000_CDC_ANC0_FB_GAIN_CTL))
|
||||||
|
return true;
|
||||||
|
|
||||||
|
if ((reg >= AQT1000_CDC_ANC1_IIR_COEFF_1_CTL) &&
|
||||||
|
(reg <= AQT1000_CDC_ANC1_FB_GAIN_CTL))
|
||||||
|
return true;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Need to mark volatile for registers that are writable but
|
||||||
|
* only few bits are read-only
|
||||||
|
*/
|
||||||
|
switch (reg) {
|
||||||
|
case AQT1000_BUCK_5V_CTRL_CCL_1:
|
||||||
|
case AQT1000_BIAS_CCOMP_FINE_ADJ:
|
||||||
|
case AQT1000_ANA_BIAS:
|
||||||
|
case AQT1000_BUCK_5V_IBIAS_CTL_4:
|
||||||
|
case AQT1000_BUCK_5V_CTRL_CCL_2:
|
||||||
|
case AQT1000_CHIP_CFG0_RST_CTL:
|
||||||
|
case AQT1000_CHIP_CFG0_CLK_CTL_CDC_DIG:
|
||||||
|
case AQT1000_CHIP_CFG0_CLK_CFG_MCLK:
|
||||||
|
case AQT1000_CHIP_CFG0_EFUSE_CTL:
|
||||||
|
case AQT1000_CDC_CLK_RST_CTRL_FS_CNT_CONTROL:
|
||||||
|
case AQT1000_CDC_CLK_RST_CTRL_MCLK_CONTROL:
|
||||||
|
case AQT1000_ANA_RX_SUPPLIES:
|
||||||
|
case AQT1000_ANA_MBHC_MECH:
|
||||||
|
case AQT1000_ANA_MBHC_ELECT:
|
||||||
|
case AQT1000_ANA_MBHC_ZDET:
|
||||||
|
case AQT1000_ANA_MICB1:
|
||||||
|
case AQT1000_BUCK_5V_EN_CTL:
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct regmap_config aqt1000_regmap_config = {
|
||||||
|
.reg_bits = 16,
|
||||||
|
.val_bits = 8,
|
||||||
|
.cache_type = REGCACHE_RBTREE,
|
||||||
|
.reg_defaults = aqt1000_defaults,
|
||||||
|
.num_reg_defaults = ARRAY_SIZE(aqt1000_defaults),
|
||||||
|
.max_register = AQT1000_MAX_REGISTER,
|
||||||
|
.volatile_reg = aqt1000_is_volatile_register,
|
||||||
|
.readable_reg = aqt1000_is_readable_register,
|
||||||
|
};
|
||||||
170
asoc/codecs/aqt1000/aqt1000-routing.h
Normal file
170
asoc/codecs/aqt1000/aqt1000-routing.h
Normal file
@@ -0,0 +1,170 @@
|
|||||||
|
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
#ifndef AQT1000_ROUTING_H
|
||||||
|
#define AQT1000_ROUTING_H
|
||||||
|
|
||||||
|
#include <sound/soc-dapm.h>
|
||||||
|
|
||||||
|
const struct snd_soc_dapm_route aqt_audio_map[] = {
|
||||||
|
|
||||||
|
/* CDC Tx interface */
|
||||||
|
|
||||||
|
{"AQT AIF1 CAP", NULL, "AQT AIF1 CAP Mixer"},
|
||||||
|
{"AQT AIF1 CAP Mixer", "TX0", "AQT TX0_MUX"},
|
||||||
|
{"AQT AIF1 CAP Mixer", "TX1", "AQT TX1_MUX"},
|
||||||
|
|
||||||
|
{"AQT TX0_MUX", "DEC_L", "AQT ADC0 MUX"},
|
||||||
|
{"AQT TX0_MUX", "DEC_R", "AQT ADC1 MUX"},
|
||||||
|
{"AQT TX0_MUX", "DEC_V", "AQT ADC2 MUX"},
|
||||||
|
|
||||||
|
{"AQT TX1_MUX", "DEC_L", "AQT ADC0 MUX"},
|
||||||
|
{"AQT TX1_MUX", "DEC_R", "AQT ADC1 MUX"},
|
||||||
|
{"AQT TX1_MUX", "DEC_V", "AQT ADC2 MUX"},
|
||||||
|
|
||||||
|
{"AQT ADC0 MUX", "AMIC", "AQT AMIC0_MUX"},
|
||||||
|
{"AQT ADC0 MUX", "ANC_FB0", "AQT ANC_FB_TUNE0"},
|
||||||
|
{"AQT ADC0 MUX", "ANC_FB1", "AQT ANC_FB_TUNE1"},
|
||||||
|
|
||||||
|
{"AQT ADC1 MUX", "AMIC", "AQT AMIC1_MUX"},
|
||||||
|
{"AQT ADC1 MUX", "ANC_FB0", "AQT ANC_FB_TUNE0"},
|
||||||
|
{"AQT ADC1 MUX", "ANC_FB1", "AQT ANC_FB_TUNE1"},
|
||||||
|
|
||||||
|
{"AQT ADC2 MUX", "AMIC", "AQT AMIC2_MUX"},
|
||||||
|
{"AQT ADC2 MUX", "ANC_FB0", "AQT ANC_FB_TUNE0"},
|
||||||
|
{"AQT ADC2 MUX", "ANC_FB1", "AQT ANC_FB_TUNE1"},
|
||||||
|
|
||||||
|
{"AQT AMIC0_MUX", "ADC_L", "AQT ADC_L"},
|
||||||
|
{"AQT AMIC0_MUX", "ADC_R", "AQT ADC_R"},
|
||||||
|
{"AQT AMIC0_MUX", "ADC_V", "AQT ADC_V"},
|
||||||
|
|
||||||
|
{"AQT AMIC1_MUX", "ADC_L", "AQT ADC_L"},
|
||||||
|
{"AQT AMIC1_MUX", "ADC_R", "AQT ADC_R"},
|
||||||
|
{"AQT AMIC1_MUX", "ADC_V", "AQT ADC_V"},
|
||||||
|
|
||||||
|
{"AQT AMIC2_MUX", "ADC_L", "AQT ADC_L"},
|
||||||
|
{"AQT AMIC2_MUX", "ADC_R", "AQT ADC_R"},
|
||||||
|
{"AQT AMIC2_MUX", "ADC_V", "AQT ADC_V"},
|
||||||
|
|
||||||
|
{"AQT ADC_L", NULL, "AQT AMIC1"},
|
||||||
|
{"AQT ADC_R", NULL, "AQT AMIC2"},
|
||||||
|
{"AQT ADC_V", NULL, "AQT AMIC3"},
|
||||||
|
|
||||||
|
{"AQT AMIC10_MUX", "ADC_L", "AQT ADC_L"},
|
||||||
|
{"AQT AMIC10_MUX", "ADC_R", "AQT ADC_R"},
|
||||||
|
{"AQT AMIC10_MUX", "ADC_V", "AQT ADC_V"},
|
||||||
|
|
||||||
|
{"AQT AMIC11_MUX", "ADC_L", "AQT ADC_L"},
|
||||||
|
{"AQT AMIC11_MUX", "ADC_R", "AQT ADC_R"},
|
||||||
|
{"AQT AMIC11_MUX", "ADC_V", "AQT ADC_V"},
|
||||||
|
|
||||||
|
{"AQT AMIC12_MUX", "ADC_L", "AQT ADC_L"},
|
||||||
|
{"AQT AMIC12_MUX", "ADC_R", "AQT ADC_R"},
|
||||||
|
{"AQT AMIC12_MUX", "ADC_V", "AQT ADC_V"},
|
||||||
|
|
||||||
|
{"AQT AMIC13_MUX", "ADC_L", "AQT ADC_L"},
|
||||||
|
{"AQT AMIC13_MUX", "ADC_R", "AQT ADC_R"},
|
||||||
|
{"AQT AMIC13_MUX", "ADC_V", "AQT ADC_V"},
|
||||||
|
|
||||||
|
{"AQT ANC OUT HPHL Enable", "Switch", "AQT AMIC10_MUX"},
|
||||||
|
{"AQT ANC OUT HPHL Enable", "Switch", "AQT AMIC11_MUX"},
|
||||||
|
{"AQT ANC OUT HPHR Enable", "Switch", "AQT AMIC12_MUX"},
|
||||||
|
{"AQT ANC OUT HPHR Enable", "Switch", "AQT AMIC13_MUX"},
|
||||||
|
|
||||||
|
{"AQT RX INT1 MIX2", NULL, "AQT ANC OUT HPHL Enable"},
|
||||||
|
{"AQT RX INT2 MIX2", NULL, "AQT ANC OUT HPHR Enable"},
|
||||||
|
|
||||||
|
{"AQT ANC0 FB MUX", "ANC_IN_HPHL", "AQT RX INT1 MIX2"},
|
||||||
|
{"AQT ANC1 FB MUX", "ANC_IN_HPHR", "AQT RX INT2 MIX2"},
|
||||||
|
|
||||||
|
{"AQT I2S_L RX", "AIF1_PB", "AQT AIF1 PB"},
|
||||||
|
{"AQT I2S_R RX", "AIF1_PB", "AQT AIF1 PB"},
|
||||||
|
|
||||||
|
{"AQT RX INT1_1 MUX", "I2S_L", "AQT I2S_L RX"},
|
||||||
|
{"AQT RX INT1_1 MUX", "I2S_R", "AQT I2S_R RX"},
|
||||||
|
{"AQT RX INT1_1 MUX", "DEC_L", "AQT ADC0 MUX"},
|
||||||
|
{"AQT RX INT1_1 MUX", "DEC_R", "AQT ADC1 MUX"},
|
||||||
|
{"AQT RX INT1_1 MUX", "DEC_V", "AQT ADC2 MUX"},
|
||||||
|
|
||||||
|
{"AQT RX INT2_1 MUX", "I2S_L", "AQT I2S_L RX"},
|
||||||
|
{"AQT RX INT2_1 MUX", "I2S_R", "AQT I2S_R RX"},
|
||||||
|
{"AQT RX INT2_1 MUX", "DEC_L", "AQT ADC0 MUX"},
|
||||||
|
{"AQT RX INT2_1 MUX", "DEC_R", "AQT ADC1 MUX"},
|
||||||
|
{"AQT RX INT2_1 MUX", "DEC_V", "AQT ADC2 MUX"},
|
||||||
|
|
||||||
|
{"AQT RX INT1_2 MUX", "I2S_L", "AQT I2S_L RX"},
|
||||||
|
{"AQT RX INT1_2 MUX", "I2S_R", "AQT I2S_R RX"},
|
||||||
|
{"AQT RX INT1_2 MUX", "DEC_L", "AQT ADC0 MUX"},
|
||||||
|
{"AQT RX INT1_2 MUX", "DEC_R", "AQT ADC1 MUX"},
|
||||||
|
{"AQT RX INT1_2 MUX", "DEC_V", "AQT ADC2 MUX"},
|
||||||
|
{"AQT RX INT1_2 MUX", "IIR0", "AQT IIR0"},
|
||||||
|
|
||||||
|
{"AQT RX INT2_2 MUX", "I2S_L", "AQT I2S_L RX"},
|
||||||
|
{"AQT RX INT2_2 MUX", "I2S_R", "AQT I2S_R RX"},
|
||||||
|
{"AQT RX INT2_2 MUX", "DEC_L", "AQT ADC0 MUX"},
|
||||||
|
{"AQT RX INT2_2 MUX", "DEC_R", "AQT ADC1 MUX"},
|
||||||
|
{"AQT RX INT2_2 MUX", "DEC_V", "AQT ADC2 MUX"},
|
||||||
|
{"AQT RX INT2_2 MUX", "IIR0", "AQT IIR0"},
|
||||||
|
|
||||||
|
{"AQT RX INT1_1 INTERP", NULL, "AQT RX INT1_1 MUX"},
|
||||||
|
{"AQT RX INT1 MIX1", NULL, "AQT RX INT1_1 INTERP"},
|
||||||
|
{"AQT RX INT1 MIX2", NULL, "AQT RX INT1 MIX1"},
|
||||||
|
|
||||||
|
{"AQT RX INT1_2 INTERP", NULL, "AQT RX INT1_2 MUX"},
|
||||||
|
{"AQT RX INT1 MIX1", NULL, "AQT RX INT1_2 INTERP"},
|
||||||
|
|
||||||
|
{"AQT ASRC0 MUX", "ASRC_IN_HPHL", "AQT RX INT1_2 INTERP"},
|
||||||
|
{"AQT RX INT1 MIX1", "HPHL Switch", "AQT ASRC0 MUX"},
|
||||||
|
|
||||||
|
{"AQT RX INT2_1 INTERP", NULL, "AQT RX INT2_1 MUX"},
|
||||||
|
{"AQT RX INT2 MIX1", NULL, "AQT RX INT2_1 INTERP"},
|
||||||
|
{"AQT RX INT2 MIX2", NULL, "AQT RX INT2 MIX1"},
|
||||||
|
|
||||||
|
{"AQT RX INT2_2 INTERP", NULL, "AQT RX INT2_2 MUX"},
|
||||||
|
{"AQT RX INT2 MIX1", NULL, "AQT RX INT2_2 INTERP"},
|
||||||
|
|
||||||
|
{"AQT ASRC1 MUX", "ASRC_IN_HPHR", "AQT RX INT2_2 INTERP"},
|
||||||
|
{"AQT RX INT2 MIX1", "HPHR Switch", "AQT ASRC1 MUX"},
|
||||||
|
|
||||||
|
{"AQT RX INT1 DEM MUX", "CLSH_DSM_OUT", "AQT RX INT1 MIX2"},
|
||||||
|
{"AQT RX INT1 DAC", NULL, "AQT RX INT1 DEM MUX"},
|
||||||
|
{"AQT RX INT1 DAC", NULL, "AQT RX_BIAS"},
|
||||||
|
{"AQT HPHL PA", NULL, "AQT RX INT1 DAC"},
|
||||||
|
{"AQT HPHL", NULL, "AQT HPHL PA"},
|
||||||
|
|
||||||
|
{"AQT RX INT2 DEM MUX", "CLSH_DSM_OUT", "AQT RX INT2 MIX2"},
|
||||||
|
{"AQT RX INT2 DAC", NULL, "AQT RX INT2 DEM MUX"},
|
||||||
|
{"AQT RX INT2 DAC", NULL, "AQT RX_BIAS"},
|
||||||
|
{"AQT HPHR PA", NULL, "AQT RX INT2 DAC"},
|
||||||
|
{"AQT HPHR", NULL, "AQT HPHR PA"},
|
||||||
|
|
||||||
|
{"AQT ANC HPHL PA", NULL, "AQT RX INT1 DAC"},
|
||||||
|
{"AQT ANC HPHL", NULL, "AQT ANC HPHL PA"},
|
||||||
|
|
||||||
|
{"AQT ANC HPHR PA", NULL, "AQT RX INT2 DAC"},
|
||||||
|
{"AQT ANC HPHR", NULL, "AQT ANC HPHR PA"},
|
||||||
|
|
||||||
|
{"AQT IIR0", NULL, "AQT TX_PATH2"},
|
||||||
|
{"AQT SRC0", NULL, "AQT IIR0"},
|
||||||
|
{"AQT RX INT1 MIX2", "SRC0", "AQT SRC0"},
|
||||||
|
{"AQT RX INT2 MIX2", "SRC0", "AQT SRC0"},
|
||||||
|
|
||||||
|
/* Native clk main path routing */
|
||||||
|
{"AQT RX INT1_1 NATIVE MUX", "ON", "AQT RX INT1_1 MUX"},
|
||||||
|
{"AQT RX INT1_1 INTERP", NULL, "AQT RX INT1_1 NATIVE MUX"},
|
||||||
|
{"AQT RX INT1_1 NATIVE MUX", NULL, "AQT RX INT1 NATIVE SUPPLY"},
|
||||||
|
|
||||||
|
{"AQT RX INT2_1 NATIVE MUX", "ON", "AQT RX INT2_1 MUX"},
|
||||||
|
{"AQT RX INT2_1 INTERP", NULL, "AQT RX INT2_1 NATIVE MUX"},
|
||||||
|
{"AQT RX INT2_1 NATIVE MUX", NULL, "AQT RX INT2 NATIVE SUPPLY"},
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
199
asoc/codecs/aqt1000/aqt1000-utils.c
Normal file
199
asoc/codecs/aqt1000/aqt1000-utils.c
Normal file
@@ -0,0 +1,199 @@
|
|||||||
|
/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/slab.h>
|
||||||
|
#include <linux/regmap.h>
|
||||||
|
#include <linux/delay.h>
|
||||||
|
#include <linux/sched.h>
|
||||||
|
#include "aqt1000.h"
|
||||||
|
#include "aqt1000-utils.h"
|
||||||
|
|
||||||
|
#define REG_BYTES 2
|
||||||
|
#define VAL_BYTES 1
|
||||||
|
/*
|
||||||
|
* Page Register Address that APP Proc uses to
|
||||||
|
* access codec registers is identified as 0x00
|
||||||
|
*/
|
||||||
|
#define PAGE_REG_ADDR 0x00
|
||||||
|
|
||||||
|
static int aqt_page_write(struct aqt1000 *aqt, unsigned short *reg)
|
||||||
|
{
|
||||||
|
int ret = 0;
|
||||||
|
unsigned short c_reg, reg_addr;
|
||||||
|
u8 pg_num, prev_pg_num;
|
||||||
|
|
||||||
|
c_reg = *reg;
|
||||||
|
pg_num = c_reg >> 8;
|
||||||
|
reg_addr = c_reg & 0xff;
|
||||||
|
if (aqt->prev_pg_valid) {
|
||||||
|
prev_pg_num = aqt->prev_pg;
|
||||||
|
if (prev_pg_num != pg_num) {
|
||||||
|
ret = aqt->write_dev(
|
||||||
|
aqt, PAGE_REG_ADDR,
|
||||||
|
(void *) &pg_num, 1);
|
||||||
|
if (ret < 0)
|
||||||
|
dev_err(aqt->dev,
|
||||||
|
"%s: page write error, pg_num: 0x%x\n",
|
||||||
|
__func__, pg_num);
|
||||||
|
else {
|
||||||
|
aqt->prev_pg = pg_num;
|
||||||
|
dev_dbg(aqt->dev, "%s: Page 0x%x Write to 0x00\n",
|
||||||
|
__func__, pg_num);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
ret = aqt->write_dev(
|
||||||
|
aqt, PAGE_REG_ADDR, (void *) &pg_num, 1);
|
||||||
|
if (ret < 0)
|
||||||
|
dev_err(aqt->dev,
|
||||||
|
"%s: page write error, pg_num: 0x%x\n",
|
||||||
|
__func__, pg_num);
|
||||||
|
else {
|
||||||
|
aqt->prev_pg = pg_num;
|
||||||
|
aqt->prev_pg_valid = true;
|
||||||
|
dev_dbg(aqt->dev, "%s: Page 0x%x Write to 0x00\n",
|
||||||
|
__func__, pg_num);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
*reg = reg_addr;
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int regmap_bus_read(void *context, const void *reg, size_t reg_size,
|
||||||
|
void *val, size_t val_size)
|
||||||
|
{
|
||||||
|
struct device *dev = context;
|
||||||
|
struct aqt1000 *aqt = dev_get_drvdata(dev);
|
||||||
|
unsigned short c_reg, rreg;
|
||||||
|
int ret, i;
|
||||||
|
|
||||||
|
if (!aqt) {
|
||||||
|
dev_err(dev, "%s: aqt is NULL\n", __func__);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
if (!reg || !val) {
|
||||||
|
dev_err(dev, "%s: reg or val is NULL\n", __func__);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (reg_size != REG_BYTES) {
|
||||||
|
dev_err(dev, "%s: register size %zd bytes, not supported\n",
|
||||||
|
__func__, reg_size);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
mutex_lock(&aqt->io_lock);
|
||||||
|
c_reg = *(u16 *)reg;
|
||||||
|
rreg = c_reg;
|
||||||
|
|
||||||
|
ret = aqt_page_write(aqt, &c_reg);
|
||||||
|
if (ret)
|
||||||
|
goto err;
|
||||||
|
ret = aqt->read_dev(aqt, c_reg, val, val_size);
|
||||||
|
if (ret < 0)
|
||||||
|
dev_err(dev, "%s: Codec read failed (%d), reg: 0x%x, size:%zd\n",
|
||||||
|
__func__, ret, rreg, val_size);
|
||||||
|
else {
|
||||||
|
for (i = 0; i < val_size; i++)
|
||||||
|
dev_dbg(dev, "%s: Read 0x%02x from 0x%x\n",
|
||||||
|
__func__, ((u8 *)val)[i], rreg + i);
|
||||||
|
}
|
||||||
|
err:
|
||||||
|
mutex_unlock(&aqt->io_lock);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int regmap_bus_gather_write(void *context,
|
||||||
|
const void *reg, size_t reg_size,
|
||||||
|
const void *val, size_t val_size)
|
||||||
|
{
|
||||||
|
struct device *dev = context;
|
||||||
|
struct aqt1000 *aqt = dev_get_drvdata(dev);
|
||||||
|
unsigned short c_reg, rreg;
|
||||||
|
int ret, i;
|
||||||
|
|
||||||
|
if (!aqt) {
|
||||||
|
dev_err(dev, "%s: aqt is NULL\n", __func__);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
if (!reg || !val) {
|
||||||
|
dev_err(dev, "%s: reg or val is NULL\n", __func__);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
if (reg_size != REG_BYTES) {
|
||||||
|
dev_err(dev, "%s: register size %zd bytes, not supported\n",
|
||||||
|
__func__, reg_size);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
mutex_lock(&aqt->io_lock);
|
||||||
|
c_reg = *(u16 *)reg;
|
||||||
|
rreg = c_reg;
|
||||||
|
|
||||||
|
ret = aqt_page_write(aqt, &c_reg);
|
||||||
|
if (ret)
|
||||||
|
goto err;
|
||||||
|
|
||||||
|
for (i = 0; i < val_size; i++)
|
||||||
|
dev_dbg(dev, "Write %02x to 0x%x\n", ((u8 *)val)[i],
|
||||||
|
rreg + i);
|
||||||
|
|
||||||
|
ret = aqt->write_dev(aqt, c_reg, (void *) val, val_size);
|
||||||
|
if (ret < 0)
|
||||||
|
dev_err(dev, "%s: Codec write failed (%d), reg:0x%x, size:%zd\n",
|
||||||
|
__func__, ret, rreg, val_size);
|
||||||
|
|
||||||
|
err:
|
||||||
|
mutex_unlock(&aqt->io_lock);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int regmap_bus_write(void *context, const void *data, size_t count)
|
||||||
|
{
|
||||||
|
struct device *dev = context;
|
||||||
|
struct aqt1000 *aqt = dev_get_drvdata(dev);
|
||||||
|
|
||||||
|
if (!aqt)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
WARN_ON(count < REG_BYTES);
|
||||||
|
|
||||||
|
return regmap_bus_gather_write(context, data, REG_BYTES,
|
||||||
|
data + REG_BYTES,
|
||||||
|
count - REG_BYTES);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct regmap_bus regmap_bus_config = {
|
||||||
|
.write = regmap_bus_write,
|
||||||
|
.gather_write = regmap_bus_gather_write,
|
||||||
|
.read = regmap_bus_read,
|
||||||
|
.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
|
||||||
|
.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* aqt1000_regmap_init:
|
||||||
|
* Initialize aqt1000 register map
|
||||||
|
*
|
||||||
|
* @dev: pointer to wcd device
|
||||||
|
* @config: pointer to register map config
|
||||||
|
*
|
||||||
|
* Returns pointer to regmap structure for success
|
||||||
|
* or NULL in case of failure.
|
||||||
|
*/
|
||||||
|
struct regmap *aqt1000_regmap_init(struct device *dev,
|
||||||
|
const struct regmap_config *config)
|
||||||
|
{
|
||||||
|
return devm_regmap_init(dev, ®map_bus_config, dev, config);
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(aqt1000_regmap_init);
|
||||||
22
asoc/codecs/aqt1000/aqt1000-utils.h
Normal file
22
asoc/codecs/aqt1000/aqt1000-utils.h
Normal file
@@ -0,0 +1,22 @@
|
|||||||
|
/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __WCD9XXX_UTILS_H__
|
||||||
|
#define __WCD9XXX_UTILS_H__
|
||||||
|
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/device.h>
|
||||||
|
#include <linux/regmap.h>
|
||||||
|
|
||||||
|
struct regmap *aqt1000_regmap_init(struct device *dev,
|
||||||
|
const struct regmap_config *config);
|
||||||
|
#endif
|
||||||
3293
asoc/codecs/aqt1000/aqt1000.c
Normal file
3293
asoc/codecs/aqt1000/aqt1000.c
Normal file
File diff suppressed because it is too large
Load Diff
229
asoc/codecs/aqt1000/aqt1000.h
Normal file
229
asoc/codecs/aqt1000/aqt1000.h
Normal file
@@ -0,0 +1,229 @@
|
|||||||
|
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef AQT1000_H
|
||||||
|
#define AQT1000_H
|
||||||
|
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/of_device.h>
|
||||||
|
#include <linux/i2c.h>
|
||||||
|
#include "pdata.h"
|
||||||
|
#include "aqt1000-clsh.h"
|
||||||
|
|
||||||
|
#define AQT1000_MAX_MICBIAS 1
|
||||||
|
#define AQT1000_NUM_INTERPOLATORS 2
|
||||||
|
#define AQT1000_NUM_DECIMATORS 3
|
||||||
|
#define AQT1000_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
|
||||||
|
#define AQT1000_RX_PATH_CTL_OFFSET 20
|
||||||
|
|
||||||
|
#define AQT1000_CLK_24P576MHZ 24576000
|
||||||
|
#define AQT1000_CLK_19P2MHZ 19200000
|
||||||
|
#define AQT1000_CLK_12P288MHZ 12288000
|
||||||
|
#define AQT1000_CLK_9P6MHZ 9600000
|
||||||
|
|
||||||
|
#define AQT1000_ST_IIR_COEFF_MAX 5
|
||||||
|
|
||||||
|
enum {
|
||||||
|
AQT1000_RX0 = 0,
|
||||||
|
AQT1000_RX1,
|
||||||
|
AQT1000_RX_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
AQT_NONE,
|
||||||
|
AQT_MCLK,
|
||||||
|
AQT_RCO,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
AQT_TX0 = 0,
|
||||||
|
AQT_TX1,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
ASRC0,
|
||||||
|
ASRC1,
|
||||||
|
ASRC_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Each IIR has 5 Filter Stages */
|
||||||
|
enum {
|
||||||
|
BAND1 = 0,
|
||||||
|
BAND2,
|
||||||
|
BAND3,
|
||||||
|
BAND4,
|
||||||
|
BAND5,
|
||||||
|
BAND_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
AQT1000_TX0 = 0,
|
||||||
|
AQT1000_TX1,
|
||||||
|
AQT1000_TX2,
|
||||||
|
AQT1000_TX_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
INTERP_HPHL,
|
||||||
|
INTERP_HPHR,
|
||||||
|
INTERP_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
INTERP_MAIN_PATH,
|
||||||
|
INTERP_MIX_PATH,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
COMPANDER_1, /* HPH_L */
|
||||||
|
COMPANDER_2, /* HPH_R */
|
||||||
|
COMPANDER_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
AIF1_PB = 0,
|
||||||
|
AIF1_CAP,
|
||||||
|
NUM_CODEC_DAIS,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aqt_codec_dai_data {
|
||||||
|
u32 rate;
|
||||||
|
u32 *ch_num;
|
||||||
|
u32 ch_act;
|
||||||
|
u32 ch_tot;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aqt_idle_detect_config {
|
||||||
|
u8 hph_idle_thr;
|
||||||
|
u8 hph_idle_detect_en;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aqt1000_i2c {
|
||||||
|
struct i2c_client *client;
|
||||||
|
struct i2c_msg xfer_msg[2];
|
||||||
|
struct mutex xfer_lock;
|
||||||
|
int mod_id;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aqt1000_cdc_dai_data {
|
||||||
|
u32 rate; /* sample rate */
|
||||||
|
u32 bit_width; /* sit width 16,24,32 */
|
||||||
|
struct list_head ch_list;
|
||||||
|
wait_queue_head_t dai_wait;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct tx_mute_work {
|
||||||
|
struct aqt1000 *aqt;
|
||||||
|
u8 decimator;
|
||||||
|
struct delayed_work dwork;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct hpf_work {
|
||||||
|
struct aqt1000 *aqt;
|
||||||
|
u8 decimator;
|
||||||
|
u8 hpf_cut_off_freq;
|
||||||
|
struct delayed_work dwork;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aqt1000 {
|
||||||
|
struct device *dev;
|
||||||
|
struct mutex io_lock;
|
||||||
|
struct mutex xfer_lock;
|
||||||
|
struct mutex reset_lock;
|
||||||
|
|
||||||
|
struct device_node *aqt_rst_np;
|
||||||
|
|
||||||
|
int (*read_dev)(struct aqt1000 *aqt, unsigned short reg,
|
||||||
|
void *dest, int bytes);
|
||||||
|
int (*write_dev)(struct aqt1000 *aqt, unsigned short reg,
|
||||||
|
void *src, int bytes);
|
||||||
|
|
||||||
|
u32 num_of_supplies;
|
||||||
|
struct regulator_bulk_data *supplies;
|
||||||
|
|
||||||
|
u32 mclk_rate;
|
||||||
|
struct regmap *regmap;
|
||||||
|
struct snd_soc_codec *codec;
|
||||||
|
bool dev_up;
|
||||||
|
bool prev_pg_valid;
|
||||||
|
u8 prev_pg;
|
||||||
|
|
||||||
|
struct aqt1000_i2c i2c_dev;
|
||||||
|
|
||||||
|
/* Codec params */
|
||||||
|
|
||||||
|
/* ANC related */
|
||||||
|
u32 anc_slot;
|
||||||
|
bool anc_func;
|
||||||
|
|
||||||
|
/* compander */
|
||||||
|
int comp_enabled[COMPANDER_MAX];
|
||||||
|
|
||||||
|
/* class h specific data */
|
||||||
|
struct aqt_clsh_cdc_data clsh_d;
|
||||||
|
|
||||||
|
/* Interpolator Mode Select for HPH_L and HPH_R */
|
||||||
|
u32 hph_mode;
|
||||||
|
|
||||||
|
unsigned long status_mask;
|
||||||
|
|
||||||
|
struct aqt1000_cdc_dai_data dai[NUM_CODEC_DAIS];
|
||||||
|
|
||||||
|
struct mutex micb_lock;
|
||||||
|
|
||||||
|
struct clk *ext_clk;
|
||||||
|
|
||||||
|
/* mbhc module */
|
||||||
|
struct aqt1000_mbhc *mbhc;
|
||||||
|
|
||||||
|
struct mutex codec_mutex;
|
||||||
|
|
||||||
|
/* cal info for codec */
|
||||||
|
struct fw_info *fw_data;
|
||||||
|
|
||||||
|
int native_clk_users;
|
||||||
|
/* ASRC users count */
|
||||||
|
int asrc_users[ASRC_MAX];
|
||||||
|
int asrc_output_mode[ASRC_MAX];
|
||||||
|
/* Main path clock users count */
|
||||||
|
int main_clk_users[AQT1000_NUM_INTERPOLATORS];
|
||||||
|
|
||||||
|
struct aqt_idle_detect_config idle_det_cfg;
|
||||||
|
u32 rx_bias_count;
|
||||||
|
|
||||||
|
s32 micb_ref;
|
||||||
|
s32 pullup_ref;
|
||||||
|
int master_bias_users;
|
||||||
|
int mclk_users;
|
||||||
|
int i2s_users;
|
||||||
|
|
||||||
|
struct hpf_work tx_hpf_work[AQT1000_NUM_DECIMATORS];
|
||||||
|
struct tx_mute_work tx_mute_dwork[AQT1000_NUM_DECIMATORS];
|
||||||
|
|
||||||
|
struct mutex master_bias_lock;
|
||||||
|
struct mutex cdc_bg_clk_lock;
|
||||||
|
struct mutex i2s_lock;
|
||||||
|
|
||||||
|
/* Interrupt */
|
||||||
|
struct regmap_irq_chip_data *irq_chip;
|
||||||
|
int num_irq_regs;
|
||||||
|
struct irq_domain *virq;
|
||||||
|
int irq;
|
||||||
|
int irq_base;
|
||||||
|
|
||||||
|
/* Entry for version info */
|
||||||
|
struct snd_info_entry *entry;
|
||||||
|
struct snd_info_entry *version_entry;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* AQT1000_H */
|
||||||
40
asoc/codecs/aqt1000/pdata.h
Normal file
40
asoc/codecs/aqt1000/pdata.h
Normal file
@@ -0,0 +1,40 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _AQT1000_PDATA_H_
|
||||||
|
#define _AQT1000_PDATA_H_
|
||||||
|
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/device.h>
|
||||||
|
#include "../msm-cdc-supply.h"
|
||||||
|
|
||||||
|
struct aqt1000_micbias_setting {
|
||||||
|
u8 ldoh_v;
|
||||||
|
u32 cfilt1_mv;
|
||||||
|
u32 micb1_mv;
|
||||||
|
u8 bias1_cfilt_sel;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct aqt1000_pdata {
|
||||||
|
unsigned int irq_gpio;
|
||||||
|
unsigned int irq_flags;
|
||||||
|
struct cdc_regulator *regulator;
|
||||||
|
int num_supplies;
|
||||||
|
struct aqt1000_micbias_setting micbias;
|
||||||
|
struct device_node *aqt_rst_np;
|
||||||
|
u32 mclk_rate;
|
||||||
|
u32 ext_clk_rate;
|
||||||
|
u32 ext_1p8v_supply;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* _AQT1000_PDATA_H_ */
|
||||||
@@ -2,6 +2,7 @@
|
|||||||
#define _CALIB_HWDEP_H
|
#define _CALIB_HWDEP_H
|
||||||
|
|
||||||
#define WCD9XXX_CODEC_HWDEP_NODE 1000
|
#define WCD9XXX_CODEC_HWDEP_NODE 1000
|
||||||
|
#define AQT1000_CODEC_HWDEP_NODE 1001
|
||||||
enum wcd_cal_type {
|
enum wcd_cal_type {
|
||||||
WCD9XXX_MIN_CAL,
|
WCD9XXX_MIN_CAL,
|
||||||
WCD9XXX_ANC_CAL = WCD9XXX_MIN_CAL,
|
WCD9XXX_ANC_CAL = WCD9XXX_MIN_CAL,
|
||||||
|
|||||||
Reference in New Issue
Block a user