samsung-sm8650/android_kernel_samsung_sm8650-modules
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

gsi: Add HAL Layer for GSI

Browse Source 
Add Hardware Abstraction Layer infrastructure to GSI
driver. This change includes registers HAL component
for GSI.

Change-Id: I87e7c22ed88117a74af4220b4c05c610bae498cc
Signed-off-by: Amir Levy <alevy@codeaurora.org>
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
This commit is contained in:
Sivan Reinstein
2020-10-08 09:20:40 +03:00
parent 4c6c6a1b80
commit b4f2036141
20 changed files with 3296 additions and 3449 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
config/dataipa.h
View File

@@ -4,7 +4,6 @@
*/ */
#define CONFIG_GSI 1 #define CONFIG_GSI 1
#define CONFIG_GSI_REGISTER_VERSION_2 1
#define CONFIG_RMNET_IPA3 1 #define CONFIG_RMNET_IPA3 1
#define CONFIG_RNDIS_IPA 1 #define CONFIG_RNDIS_IPA 1
#define CONFIG_IPA_WDI_UNIFIED_API 1 #define CONFIG_IPA_WDI_UNIFIED_API 1

1
config/dataipa_GKI.conf
View File

@@ -1,5 +1,4 @@
export CONFIG_GSI=m export CONFIG_GSI=m
export CONFIG_GSI_REGISTER_VERSION_2=y
export CONFIG_IPA_CLIENTS_MANAGER=m export CONFIG_IPA_CLIENTS_MANAGER=m
export CONFIG_IPA_WDI_UNIFIED_API=y export CONFIG_IPA_WDI_UNIFIED_API=y
export CONFIG_RMNET_IPA3=y export CONFIG_RMNET_IPA3=y

1
config/dataipa_QGKI.conf
View File

@@ -1,5 +1,4 @@
export CONFIG_GSI=y export CONFIG_GSI=y
export CONFIG_GSI_REGISTER_VERSION_2=y
export CONFIG_IPA_CLIENTS_MANAGER=y export CONFIG_IPA_CLIENTS_MANAGER=y
export CONFIG_IPA_WDI_UNIFIED_API=y export CONFIG_IPA_WDI_UNIFIED_API=y
export CONFIG_RMNET_IPA3=y export CONFIG_RMNET_IPA3=y

3
drivers/platform/msm/Makefile
View File

@@ -27,8 +27,9 @@ endif
DATAIPADRVTOP = $(srctree)/techpack/dataipa/drivers/platform/msm DATAIPADRVTOP = $(srctree)/techpack/dataipa/drivers/platform/msm
ifneq (,$(filter $(CONFIG_IPA3),y m)) ifneq (,$(filter $(CONFIG_IPA3) $(CONFIG_GSI),y m))
LINUXINCLUDE += -I$(DATAIPADRVTOP)/gsi LINUXINCLUDE += -I$(DATAIPADRVTOP)/gsi
LINUXINCLUDE += -I$(DATAIPADRVTOP)/gsi/gsihal
LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa
LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3 LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3
LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/ipahal LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/ipahal

2
drivers/platform/msm/gsi/Makefile
View File

@@ -2,7 +2,7 @@
obj-$(CONFIG_GSI) += gsim.o obj-$(CONFIG_GSI) += gsim.o
gsim-objs := gsi.o gsim-objs := gsi.o gsihal/gsihal.o gsihal/gsihal_reg.o
gsim-$(CONFIG_DEBUG_FS) += gsi_dbg.o gsim-$(CONFIG_DEBUG_FS) += gsi_dbg.o

1562
drivers/platform/msm/gsi/gsi.c
View File

File diff suppressed because it is too large Load Diff

6
drivers/platform/msm/gsi/gsi.h
View File

@@ -30,9 +30,6 @@
#define GSI_NO_EVT_ERINDEX 31 #define GSI_NO_EVT_ERINDEX 31
#define GSI_ISR_CACHE_MAX 20 #define GSI_ISR_CACHE_MAX 20
#define gsi_readl(c) (readl_relaxed(c))
#define gsi_writel(v, c) ({ __iowmb(); writel_relaxed((v), (c)); })
#define GSI_IPC_LOGGING(buf, fmt, args...) \ #define GSI_IPC_LOGGING(buf, fmt, args...) \
do { \ do { \
if (buf) \ if (buf) \
@@ -2037,10 +2034,11 @@ void gsi_wdi3_dump_register(unsigned long chan_hdl);
* @gsi_base_addr: Base address of GSI register space * @gsi_base_addr: Base address of GSI register space
* @gsi_size: Mapping size of the GSI register space * @gsi_size: Mapping size of the GSI register space
* @ver: The appropriate GSI version enum
* *
* @Return gsi_status * @Return gsi_status
*/ */
int gsi_map_base(phys_addr_t gsi_base_addr, u32 gsi_size); int gsi_map_base(phys_addr_t gsi_base_addr, u32 gsi_size, enum gsi_ver ver);
/** /**
* gsi_unmap_base - Peripheral should call this function to undo the * gsi_unmap_base - Peripheral should call this function to undo the

151
drivers/platform/msm/gsi/gsi_dbg.c
View File

@@ -9,8 +9,8 @@
#include <linux/random.h> #include <linux/random.h>
#include <linux/uaccess.h> #include <linux/uaccess.h>
#include <linux/msm_gsi.h> #include <linux/msm_gsi.h>
#include "gsi_reg.h"
#include "gsi.h" #include "gsi.h"
#include "gsihal.h"
#define TERR(fmt, args...) \ #define TERR(fmt, args...) \
pr_err("%s:%d " fmt, __func__, __LINE__, ## args) pr_err("%s:%d " fmt, __func__, __LINE__, ## args)
@@ -69,53 +69,53 @@ static ssize_t gsi_dump_evt(struct file *file,
return -EINVAL; return -EINVAL;
} }
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_0,
GSI_EE_n_EV_CH_k_CNTXT_0_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d CTX0 0x%x\n", arg1, val); TERR("EV%2d CTX0 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_1,
GSI_EE_n_EV_CH_k_CNTXT_1_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d CTX1 0x%x\n", arg1, val); TERR("EV%2d CTX1 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_2,
GSI_EE_n_EV_CH_k_CNTXT_2_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d CTX2 0x%x\n", arg1, val); TERR("EV%2d CTX2 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_3,
GSI_EE_n_EV_CH_k_CNTXT_3_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d CTX3 0x%x\n", arg1, val); TERR("EV%2d CTX3 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_4,
GSI_EE_n_EV_CH_k_CNTXT_4_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d CTX4 0x%x\n", arg1, val); TERR("EV%2d CTX4 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_5,
GSI_EE_n_EV_CH_k_CNTXT_5_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d CTX5 0x%x\n", arg1, val); TERR("EV%2d CTX5 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_6,
GSI_EE_n_EV_CH_k_CNTXT_6_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d CTX6 0x%x\n", arg1, val); TERR("EV%2d CTX6 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_7,
GSI_EE_n_EV_CH_k_CNTXT_7_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d CTX7 0x%x\n", arg1, val); TERR("EV%2d CTX7 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_8,
GSI_EE_n_EV_CH_k_CNTXT_8_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d CTX8 0x%x\n", arg1, val); TERR("EV%2d CTX8 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_9,
GSI_EE_n_EV_CH_k_CNTXT_9_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d CTX9 0x%x\n", arg1, val); TERR("EV%2d CTX9 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_10,
GSI_EE_n_EV_CH_k_CNTXT_10_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d CTX10 0x%x\n", arg1, val); TERR("EV%2d CTX10 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_11,
GSI_EE_n_EV_CH_k_CNTXT_11_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d CTX11 0x%x\n", arg1, val); TERR("EV%2d CTX11 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_12,
GSI_EE_n_EV_CH_k_CNTXT_12_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d CTX12 0x%x\n", arg1, val); TERR("EV%2d CTX12 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_CNTXT_13,
GSI_EE_n_EV_CH_k_CNTXT_13_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d CTX13 0x%x\n", arg1, val); TERR("EV%2d CTX13 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_SCRATCH_0,
GSI_EE_n_EV_CH_k_SCRATCH_0_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d SCR0 0x%x\n", arg1, val); TERR("EV%2d SCR0 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_EV_CH_k_SCRATCH_1,
GSI_EE_n_EV_CH_k_SCRATCH_1_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("EV%2d SCR1 0x%x\n", arg1, val); TERR("EV%2d SCR1 0x%x\n", arg1, val);
if (arg2) { if (arg2) {
@@ -182,57 +182,50 @@ static ssize_t gsi_dump_ch(struct file *file,
return -EINVAL; return -EINVAL;
} }
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_0,
GSI_EE_n_GSI_CH_k_CNTXT_0_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("CH%2d CTX0 0x%x\n", arg1, val); TERR("CH%2d CTX0 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_1,
GSI_EE_n_GSI_CH_k_CNTXT_1_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("CH%2d CTX1 0x%x\n", arg1, val); TERR("CH%2d CTX1 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_2,
GSI_EE_n_GSI_CH_k_CNTXT_2_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("CH%2d CTX2 0x%x\n", arg1, val); TERR("CH%2d CTX2 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_3,
GSI_EE_n_GSI_CH_k_CNTXT_3_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("CH%2d CTX3 0x%x\n", arg1, val); TERR("CH%2d CTX3 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_4,
GSI_EE_n_GSI_CH_k_CNTXT_4_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("CH%2d CTX4 0x%x\n", arg1, val); TERR("CH%2d CTX4 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_5,
GSI_EE_n_GSI_CH_k_CNTXT_5_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("CH%2d CTX5 0x%x\n", arg1, val); TERR("CH%2d CTX5 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_6,
GSI_EE_n_GSI_CH_k_CNTXT_6_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("CH%2d CTX6 0x%x\n", arg1, val); TERR("CH%2d CTX6 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_7,
GSI_EE_n_GSI_CH_k_CNTXT_7_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("CH%2d CTX7 0x%x\n", arg1, val); TERR("CH%2d CTX7 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_RE_FETCH_READ_PTR,
GSI_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OFFS(arg1, gsi_ctx->per.ee, arg1);
gsi_ctx->per.ee));
TERR("CH%2d REFRP 0x%x\n", arg1, val); TERR("CH%2d REFRP 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR,
GSI_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OFFS(arg1, gsi_ctx->per.ee, arg1);
gsi_ctx->per.ee));
TERR("CH%2d REFWP 0x%x\n", arg1, val); TERR("CH%2d REFWP 0x%x\n", arg1, val);
if (gsi_ctx->per.ver >= GSI_VER_2_5) { val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_QOS,
val = gsi_readl(gsi_ctx->base + gsi_ctx->per.ee, arg1);
GSI_V2_5_EE_n_GSI_CH_k_QOS_OFFS(arg1, gsi_ctx->per.ee));
} else {
val = gsi_readl(gsi_ctx->base +
GSI_EE_n_GSI_CH_k_QOS_OFFS(arg1, gsi_ctx->per.ee));
}
TERR("CH%2d QOS 0x%x\n", arg1, val); TERR("CH%2d QOS 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_0,
GSI_EE_n_GSI_CH_k_SCRATCH_0_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("CH%2d SCR0 0x%x\n", arg1, val); TERR("CH%2d SCR0 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_1,
GSI_EE_n_GSI_CH_k_SCRATCH_1_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("CH%2d SCR1 0x%x\n", arg1, val); TERR("CH%2d SCR1 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_2,
GSI_EE_n_GSI_CH_k_SCRATCH_2_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("CH%2d SCR2 0x%x\n", arg1, val); TERR("CH%2d SCR2 0x%x\n", arg1, val);
val = gsi_readl(gsi_ctx->base + val = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_SCRATCH_3,
GSI_EE_n_GSI_CH_k_SCRATCH_3_OFFS(arg1, gsi_ctx->per.ee)); gsi_ctx->per.ee, arg1);
TERR("CH%2d SCR3 0x%x\n", arg1, val); TERR("CH%2d SCR3 0x%x\n", arg1, val);
if (arg2) { if (arg2) {
@@ -482,17 +475,15 @@ static void gsi_dbg_update_ch_dp_stats(struct gsi_chan_ctx *ctx)
int ee = gsi_ctx->per.ee; int ee = gsi_ctx->per.ee;
uint16_t used_hw; uint16_t used_hw;
rp_hw = gsi_readl(gsi_ctx->base + rp_hw = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_4,
GSI_EE_n_GSI_CH_k_CNTXT_4_OFFS(ctx->props.ch_id, ee)); ee, ctx->props.ch_id);
rp_hw |= ((uint64_t)gsi_readl(gsi_ctx->base + rp_hw |= ((uint64_t)gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_5,
GSI_EE_n_GSI_CH_k_CNTXT_5_OFFS(ctx->props.ch_id, ee))) ee, ctx->props.ch_id)) << 32;
<< 32;
wp_hw = gsi_readl(gsi_ctx->base + wp_hw = gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_6,
GSI_EE_n_GSI_CH_k_CNTXT_6_OFFS(ctx->props.ch_id, ee)); ee, ctx->props.ch_id);
wp_hw |= ((uint64_t)gsi_readl(gsi_ctx->base + wp_hw |= ((uint64_t)gsihal_read_reg_nk(GSI_EE_n_GSI_CH_k_CNTXT_7,
GSI_EE_n_GSI_CH_k_CNTXT_7_OFFS(ctx->props.ch_id, ee))) ee, ctx->props.ch_id)) << 32;
<< 32;
start_hw = gsi_find_idx_from_addr(&ctx->ring, rp_hw); start_hw = gsi_find_idx_from_addr(&ctx->ring, rp_hw);
end_hw = gsi_find_idx_from_addr(&ctx->ring, wp_hw); end_hw = gsi_find_idx_from_addr(&ctx->ring, wp_hw);

1
drivers/platform/msm/gsi/gsi_emulation.h
View File

@@ -9,7 +9,6 @@
# include <linux/interrupt.h> # include <linux/interrupt.h>
# include "gsi.h" # include "gsi.h"
# include "gsi_reg.h"
#if defined(CONFIG_IPA_EMULATION) #if defined(CONFIG_IPA_EMULATION)
# include "gsi_emulation_stubs.h" # include "gsi_emulation_stubs.h"

30
drivers/platform/msm/gsi/gsi_reg.h
View File

@@ -1,30 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
*/
#ifndef __GSI_REG_H__
#define __GSI_REG_H__
enum gsi_register_ver {
GSI_REGISTER_VER_1 = 0,
GSI_REGISTER_VER_2 = 1,
GSI_REGISTER_MAX,
};
#ifdef GSI_REGISTER_VER_CURRENT
#error GSI_REGISTER_VER_CURRENT already defined
#endif
#ifdef CONFIG_GSI_REGISTER_VERSION_2
#include "gsi_reg_v2.h"
#define GSI_REGISTER_VER_CURRENT GSI_REGISTER_VER_2
#endif
/* The default is V1 */
#ifndef GSI_REGISTER_VER_CURRENT
#include "gsi_reg_v1.h"
#define GSI_REGISTER_VER_CURRENT GSI_REGISTER_VER_1
#endif
#endif /* __GSI_REG_H__ */

1098
drivers/platform/msm/gsi/gsi_reg_v1.h
View File

File diff suppressed because it is too large Load Diff

1197
drivers/platform/msm/gsi/gsi_reg_v2.h
View File

File diff suppressed because it is too large Load Diff

71
drivers/platform/msm/gsi/gsihal/gsihal.c Normal file
View File

@@ -0,0 +1,71 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include "gsihal_i.h"
#include "gsihal_reg.h"
struct gsihal_context *gsihal_ctx;
int gsihal_init(enum gsi_ver gsi_ver, void __iomem *base)
{
int result = 0;
GSIDBG("initializing GSI HAL, GSI ver %d, base = %pK\n",
gsi_ver, base);
if (gsihal_ctx) {
GSIDBG("gsihal already initialized\n");
if (base != gsihal_ctx->base) {
GSIERR(
"base address of early init is differnet (%pK - %pK)\n"
);
WARN_ON(1);
}
result = -EEXIST;
goto bail_err_exit;
}
if (gsi_ver < GSI_VER_1_0 || gsi_ver >= GSI_VER_MAX) {
GSIERR("invalid GSI version %d\n", gsi_ver);
result = -EINVAL;
goto bail_err_exit;
}
if (!base) {
GSIERR("invalid memory io mapping addr\n");
result = -EINVAL;
goto bail_err_exit;
}
gsihal_ctx = kzalloc(sizeof(*gsihal_ctx), GFP_KERNEL);
if (!gsihal_ctx) {
GSIERR("kzalloc err for gsihal_ctx\n");
result = -ENOMEM;
goto bail_err_exit;
}
gsihal_ctx->gsi_ver = gsi_ver;
gsihal_ctx->base = base;
if (gsihal_reg_init(gsi_ver)) {
GSIERR("failed to initialize gsihal regs\n");
result = -EINVAL;
goto bail_free_ctx;
}
return 0;
bail_free_ctx:
kfree(gsihal_ctx);
gsihal_ctx = NULL;
bail_err_exit:
return result;
}
void gsihal_destroy(void)
{
GSIDBG("Entry\n");
kfree(gsihal_ctx);
gsihal_ctx = NULL;
}

14
drivers/platform/msm/gsi/gsihal/gsihal.h Normal file
View File

@@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2030, The Linux Foundation. All rights reserved.
*/
#ifndef _GSIHAL_H_
#define _GSIHAL_H_
#include "gsihal_reg.h"
int gsihal_init(enum gsi_ver gsi_ver, void __iomem *base);
void gsihal_destroy(void);
#endif /* _GSIHAL_H_ */

19
drivers/platform/msm/gsi/gsihal/gsihal_i.h Normal file
View File

@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef _GSIHAL_I_H_
#define _GSIHAL_I_H_
#include "../gsi.h"
#include <linux/slab.h>
#include <linux/io.h>
struct gsihal_context {
enum gsi_ver gsi_ver;
void __iomem *base;
};
extern struct gsihal_context *gsihal_ctx;
#endif /* _GSIHAL_I_H_ */

1811
drivers/platform/msm/gsi/gsihal/gsihal_reg.c Normal file
View File

File diff suppressed because it is too large Load Diff

406
drivers/platform/msm/gsi/gsihal/gsihal_reg.h Normal file
View File

@@ -0,0 +1,406 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2030, The Linux Foundation. All rights reserved.
*/
#ifndef _GSIHAL_REG_H_
#define _GSIHAL_REG_H_
/*
* Registers names
*
* NOTE:: Any change to this enum, need to change to gsireg_name_to_str
* array as well.
*/
enum gsihal_reg_name {
GSI_EE_n_CNTXT_TYPE_IRQ_MSK,
GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK,
GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK,
GSI_EE_n_CNTXT_SRC_IEOB_IRQ_MSK,
GSI_EE_n_CNTXT_GLOB_IRQ_EN,
GSI_EE_n_CNTXT_GSI_IRQ_EN,
GSI_EE_n_CNTXT_TYPE_IRQ,
GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ,
GSI_EE_n_GSI_CH_k_CNTXT_0,
GSI_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR,
GSI_EE_n_CNTXT_SRC_EV_CH_IRQ,
GSI_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR,
GSI_EE_n_EV_CH_k_CNTXT_0,
GSI_EE_n_CNTXT_GLOB_IRQ_STTS,
GSI_EE_n_ERROR_LOG,
GSI_EE_n_ERROR_LOG_CLR,
GSI_EE_n_CNTXT_GLOB_IRQ_CLR,
GSI_EE_n_EV_CH_k_DOORBELL_0,
GSI_EE_n_GSI_CH_k_DOORBELL_0,
GSI_EE_n_CNTXT_SRC_IEOB_IRQ,
GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR,
GSI_INTER_EE_n_SRC_GSI_CH_IRQ,
GSI_INTER_EE_n_SRC_GSI_CH_IRQ_CLR,
GSI_INTER_EE_n_SRC_EV_CH_IRQ,
GSI_INTER_EE_n_SRC_EV_CH_IRQ_CLR,
GSI_EE_n_CNTXT_GSI_IRQ_STTS,
GSI_EE_n_CNTXT_GSI_IRQ_CLR,
GSI_EE_n_GSI_HW_PARAM,
GSI_EE_n_GSI_HW_PARAM_0,
GSI_EE_n_GSI_HW_PARAM_2,
GSI_EE_n_GSI_SW_VERSION,
GSI_EE_n_CNTXT_INTSET,
GSI_EE_n_CNTXT_MSI_BASE_LSB,
GSI_EE_n_CNTXT_MSI_BASE_MSB,
GSI_EE_n_GSI_STATUS,
GSI_EE_n_CNTXT_SCRATCH_0,
GSI_EE_n_EV_CH_k_CNTXT_1,
GSI_EE_n_EV_CH_k_CNTXT_2,
GSI_EE_n_EV_CH_k_CNTXT_3,
GSI_EE_n_EV_CH_k_CNTXT_8,
GSI_EE_n_EV_CH_k_CNTXT_9,
GSI_EE_n_EV_CH_k_CNTXT_10,
GSI_EE_n_EV_CH_k_CNTXT_11,
GSI_EE_n_EV_CH_k_CNTXT_12,
GSI_EE_n_EV_CH_k_CNTXT_13,
GSI_EE_n_EV_CH_k_DOORBELL_1,
GSI_EE_n_EV_CH_CMD,
GSI_EE_n_EV_CH_k_SCRATCH_0,
GSI_EE_n_EV_CH_k_SCRATCH_1,
GSI_EE_n_GSI_CH_k_DOORBELL_1,
GSI_EE_n_GSI_CH_k_QOS,
GSI_EE_n_GSI_CH_k_CNTXT_1,
GSI_EE_n_GSI_CH_k_CNTXT_2,
GSI_EE_n_GSI_CH_k_CNTXT_3,
GSI_EE_n_GSI_CH_CMD,
GSI_EE_n_GSI_CH_k_SCRATCH_0,
GSI_EE_n_GSI_CH_k_SCRATCH_1,
GSI_EE_n_GSI_CH_k_SCRATCH_2,
GSI_EE_n_GSI_CH_k_SCRATCH_3,
GSI_EE_n_GSI_CH_k_CNTXT_4,
GSI_EE_n_GSI_CH_k_CNTXT_5,
GSI_EE_n_GSI_CH_k_CNTXT_6,
GSI_EE_n_GSI_CH_k_CNTXT_7,
GSI_EE_n_EV_CH_k_CNTXT_4,
GSI_EE_n_EV_CH_k_CNTXT_5,
GSI_EE_n_EV_CH_k_CNTXT_6,
GSI_EE_n_EV_CH_k_CNTXT_7,
GSI_GSI_IRAM_PTR_CH_CMD,
GSI_GSI_IRAM_PTR_CH_DB,
GSI_GSI_IRAM_PTR_CH_DIS_COMP,
GSI_GSI_IRAM_PTR_CH_EMPTY,
GSI_GSI_IRAM_PTR_EE_GENERIC_CMD,
GSI_GSI_IRAM_PTR_EVENT_GEN_COMP,
GSI_GSI_IRAM_PTR_INT_MOD_STOPPED,
GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0,
GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2,
GSI_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1,
GSI_GSI_IRAM_PTR_NEW_RE,
GSI_GSI_IRAM_PTR_READ_ENG_COMP,
GSI_GSI_IRAM_PTR_TIMER_EXPIRED,
GSI_GSI_IRAM_PTR_EV_DB,
GSI_GSI_IRAM_PTR_UC_GP_INT,
GSI_GSI_IRAM_PTR_WRITE_ENG_COMP,
GSI_GSI_IRAM_PTR_TLV_CH_NOT_FULL,
GSI_IC_DISABLE_CHNL_BCK_PRS_LSB,
GSI_IC_DISABLE_CHNL_BCK_PRS_MSB,
GSI_IC_GEN_EVNT_BCK_PRS_LSB,
GSI_IC_GEN_EVNT_BCK_PRS_MSB,
GSI_IC_GEN_INT_BCK_PRS_LSB,
GSI_IC_GEN_INT_BCK_PRS_MSB,
GSI_IC_STOP_INT_MOD_BCK_PRS_LSB,
GSI_IC_STOP_INT_MOD_BCK_PRS_MSB,
GSI_IC_PROCESS_DESC_BCK_PRS_LSB,
GSI_IC_PROCESS_DESC_BCK_PRS_MSB,
GSI_IC_TLV_STOP_BCK_PRS_LSB,
GSI_IC_TLV_STOP_BCK_PRS_MSB,
GSI_IC_TLV_RESET_BCK_PRS_LSB,
GSI_IC_TLV_RESET_BCK_PRS_MSB,
GSI_IC_RGSTR_TIMER_BCK_PRS_LSB,
GSI_IC_RGSTR_TIMER_BCK_PRS_MSB,
GSI_IC_READ_BCK_PRS_LSB,
GSI_IC_READ_BCK_PRS_MSB,
GSI_IC_WRITE_BCK_PRS_LSB,
GSI_IC_WRITE_BCK_PRS_MSB,
GSI_IC_UCONTROLLER_GPR_BCK_PRS_LSB,
GSI_IC_UCONTROLLER_GPR_BCK_PRS_MSB,
GSI_GSI_PERIPH_BASE_ADDR_MSB,
GSI_GSI_PERIPH_BASE_ADDR_LSB,
GSI_GSI_MCS_CFG,
GSI_GSI_CFG,
GSI_EE_n_GSI_EE_GENERIC_CMD,
GSI_MAP_EE_n_CH_k_VP_TABLE,
GSI_EE_n_GSI_CH_k_RE_FETCH_READ_PTR,
GSI_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR,
GSI_GSI_INST_RAM_n,
GSI_GSI_IRAM_PTR_MSI_DB,
GSI_REG_MAX
};
struct gsihal_reg_ctx_type_irq {
uint32_t general;
uint32_t inter_ee_ev_ctrl;
uint32_t inter_ee_ch_ctrl;
uint32_t ieob;
uint32_t glob_ee;
uint32_t ev_ctrl;
uint32_t ch_ctrl;
};
struct gsihal_reg_ch_k_cntxt_0 {
uint32_t element_size;
uint32_t chstate;
uint32_t erindex;
uint32_t chtype_protocol_msb;
uint32_t chid;
uint32_t ee;
uint32_t chtype_dir;
uint32_t chtype_protocol;
};
struct gsihal_reg_cntxt_glob_irq_stts {
uint8_t gp_int3;
uint8_t gp_int2;
uint8_t gp_int1;
uint8_t error_int;
};
struct gsihal_reg_cntxt_gsi_irq_stts {
uint8_t gsi_mcs_stack_ovrflow;
uint8_t gsi_cmd_fifo_ovrflow;
uint8_t gsi_bus_error;
uint8_t gsi_break_point;
};
struct gsihal_reg_hw_param {
uint32_t periph_sec_grp;
uint32_t use_axi_m;
uint32_t periph_conf_addr_bus_w;
uint32_t num_ees;
uint32_t gsi_ch_num;
uint32_t gsi_ev_ch_num;
};
struct gsihal_reg_hw_param2 {
uint32_t gsi_use_inter_ee;
uint32_t gsi_use_rd_wr_eng;
uint32_t gsi_sdma_n_iovec;
uint32_t gsi_sdma_max_burst;
uint32_t gsi_sdma_n_int;
uint32_t gsi_use_sdma;
uint32_t gsi_ch_full_logic;
uint32_t gsi_ch_pend_translate;
uint32_t gsi_num_ev_per_ee;
uint32_t gsi_num_ch_per_ee;
uint32_t gsi_iram_size;
};
struct gsihal_reg_gsi_status {
uint8_t enabled;
};
struct gsihal_reg_ev_ch_k_cntxt_0 {
uint32_t element_size;
uint32_t chstate;
uint32_t intype;
uint32_t evchid;
uint32_t ee;
uint32_t chtype;
};
struct gsihal_reg_ev_ch_k_cntxt_1 {
uint32_t r_length;
};
struct gsihal_reg_ev_ch_k_cntxt_2 {
uint32_t r_base_addr_lsbs;
};
struct gsihal_reg_ev_ch_k_cntxt_3 {
uint32_t r_base_addr_msbs;
};
struct gsihal_reg_ev_ch_k_cntxt_8 {
uint32_t int_mod_cnt;
uint32_t int_modc;
uint32_t int_modt;
};
struct gsihal_reg_ev_ch_k_cntxt_9 {
uint32_t intvec;
};
struct gsihal_reg_ev_ch_k_cntxt_10 {
uint32_t msi_addr_lsb;
};
struct gsihal_reg_ev_ch_k_cntxt_11 {
uint32_t msi_addr_msb;
};
struct gsihal_reg_ev_ch_k_cntxt_12 {
uint32_t rp_update_addr_lsb;
};
struct gsihal_reg_ev_ch_k_cntxt_13 {
uint32_t rp_update_addr_msb;
};
struct gsihal_reg_gsi_ee_n_ev_ch_k_doorbell_1 {
uint32_t write_ptr_msb;
};
struct gsihal_reg_ee_n_ev_ch_cmd {
uint32_t opcode;
uint32_t chid;
};
struct gsihal_reg_ee_n_gsi_ch_cmd {
uint32_t opcode;
uint32_t chid;
};
struct gsihal_reg_gsi_ee_n_gsi_ch_k_qos {
uint32_t db_in_bytes; //2.9
uint32_t empty_lvl_thrshold;
uint32_t prefetch_mode;
uint32_t use_escape_buf_only; //stringray
uint32_t use_db_eng; //mclaren
uint32_t max_prefetch;
uint32_t wrr_weight;
};
struct gsihal_reg_ch_k_cntxt_1 {
uint32_t r_length;
};
struct gsihal_reg_gsi_cfg {
uint32_t sleep_clk_div;
uint32_t bp_mtrix_disable;
uint32_t gsi_pwr_clps;
uint32_t uc_is_mcs;
uint32_t double_mcs_clk_freq;
uint32_t mcs_enable;
uint32_t gsi_enable;
};
struct gsihal_reg_gsi_ee_generic_cmd {
uint32_t opcode;
uint32_t virt_chan_idx;
uint32_t ee;
};
struct gsihal_reg_gsi_ee_n_cntxt_gsi_irq {
uint8_t gsi_mcs_stack_ovrflow;
uint8_t gsi_cmd_fifo_ovrflow;
uint8_t gsi_bus_error;
uint8_t gsi_break_point;
};
/*
* gsihal_reg_init() - intialize gsihal regsiters module
*/
int gsihal_reg_init(enum gsi_ver gsi_ver);
/*
* gsihal_read_reg_nk() - Get nk parameterized reg value
*/
u32 gsihal_read_reg_nk(enum gsihal_reg_name reg, u32 n, u32 k);
/*
* gsihal_read_reg_n() - Get n parameterized reg value
*/
static inline u32 gsihal_read_reg_n(enum gsihal_reg_name reg, u32 n)
{
return gsihal_read_reg_nk(reg, n, 0);
}
/*
* gsihal_read_reg() - Get reg value
*/
static inline u32 gsihal_read_reg(enum gsihal_reg_name reg)
{
return gsihal_read_reg_nk(reg, 0, 0);
}
/*
* gsihal_write_reg_nk() - Write to n/k parameterized reg a raw value
*/
void gsihal_write_reg_nk(enum gsihal_reg_name reg, u32 n, u32 k, u32 val);
/*
* gsihal_write_reg_n() - Write to n parameterized reg a raw value
*/
static inline void gsihal_write_reg_n(enum gsihal_reg_name reg, u32 n, u32 val)
{
gsihal_write_reg_nk(reg, n, 0, val);
}
/*
* gsihal_write_reg() - Write to reg a raw value
*/
static inline void gsihal_write_reg(enum gsihal_reg_name reg, u32 val)
{
gsihal_write_reg_nk(reg, 0, 0, val);
}
/*
* gsihal_read_reg_nk_fields() - Get the parsed value of nk parameterized reg
*/
u32 gsihal_read_reg_nk_fields(enum gsihal_reg_name reg,
u32 n, u32 k, void *fields);
/*
* gsihal_write_reg_nk_fields() - Write to nk parameterized reg a prased value
*/
void gsihal_write_reg_nk_fields(enum gsihal_reg_name reg, u32 n, u32 k,
const void *fields);
/*
* gsihal_read_reg_n_fields() - Get the parsed value of n parameterized reg
*/
u32 gsihal_read_reg_n_fields(enum gsihal_reg_name reg, u32 n, void *fields);
/*
* gsihal_write_reg_n_fields() - Write to n parameterized reg a prased value
*/
void gsihal_write_reg_n_fields(enum gsihal_reg_name reg, u32 n,
const void *fields);
/*
* gsihal_write_reg_fields() - Write to reg a prased value
*/
void gsihal_write_reg_fields(enum gsihal_reg_name reg, const void *fields);
/*
* gsihal_read_reg_fields() - Get the parsed value of reg
*/
u32 gsihal_read_reg_fields(enum gsihal_reg_name reg, void *fields);
/*
* Get the offset of a nk parameterized register
*/
u32 gsihal_get_reg_nk_ofst(enum gsihal_reg_name reg, u32 n, u32 k);
/*
* Get the offset of a n parameterized register
*/
static inline u32 gsihal_get_reg_n_ofst(enum gsihal_reg_name reg, u32 n)
{
return gsihal_get_reg_nk_ofst(reg, n, 0);
}
/*
* Get the offset of a register
*/
static inline u32 gsihal_get_reg_ofst(enum gsihal_reg_name reg)
{
return gsihal_get_reg_nk_ofst(reg, 0, 0);
}
/*
* Get GSI instruction ram MAX size
*/
unsigned long gsihal_get_inst_ram_size(void);
/*
* Get mask for GP_int1
*/
u32 gsihal_get_glob_irq_en_gp_int1_mask(void);
#endif /* _GSIHAL_REG_H_ */

298
drivers/platform/msm/gsi/gsihal/gsihal_reg_i.h Normal file
View File

@@ -0,0 +1,298 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef _GSIHAL_REG_I_H_
#define _GSIHAL_REG_I_H_
#define GSI_SETFIELD(val, shift, mask) (((val) << (shift)) & (mask))
#define GSI_SETFIELD_IN_REG(reg, val, shift, mask) \
(reg |= ((val) << (shift)) & (mask))
#define GSI_GETFIELD_FROM_REG(reg, shift, mask) \
(((reg) & (mask)) >> (shift))
/* GSI_GSI_INST_RAM_n */
#define GSI_GSI_INST_RAM_n_WORD_SZ 0x4
#define GSI_GSI_INST_RAM_n_MAXn 4095
#define GSI_V2_0_GSI_INST_RAM_n_MAXn 6143
#define GSI_V2_2_GSI_INST_RAM_n_MAXn 4095
#define GSI_V2_5_GSI_INST_RAM_n_MAXn 8191
#define GSI_V2_7_GSI_INST_RAM_n_MAXn 5119
#define GSI_V2_9_GSI_INST_RAM_n_MAXn 6143
/* GSI_EE_n_CNTXT_TYPE_IRQ */
#define GSI_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK 0x40
#define GSI_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT 0x6
#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK 0x20
#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT 0x5
#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK 0x10
#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT 0x4
#define GSI_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK 0x8
#define GSI_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT 0x3
#define GSI_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK 0x4
#define GSI_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT 0x2
#define GSI_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK 0x2
#define GSI_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT 0x1
#define GSI_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK 0x1
#define GSI_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT 0x0
/* GSI_EE_n_GSI_CH_k_CNTXT_0 */
#define GSI_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000
#define GSI_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18
#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000
#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT 0x14
#define GSI_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_BMSK 0x7c000
#define GSI_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_SHFT 0xe
#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK 0x1f00
#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT 0x8
#define GSI_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK 0xf0
#define GSI_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT 0x4
#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK 0x8
#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT 0x3
#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK 0x7
#define GSI_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT 0x0
#define GSI_V2_5_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MSB_BMSK 0x2000
#define GSI_V2_5_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MSB_SHFT 0xd
/* GSI_EE_n_EV_CH_k_CNTXT_0 */
#define GSI_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000
#define GSI_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18
#define GSI_EE_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000
#define GSI_EE_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT 0x14
#define GSI_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK 0x10000
#define GSI_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT 0x10
#define GSI_EE_n_EV_CH_k_CNTXT_0_EVCHID_BMSK 0xff00
#define GSI_EE_n_EV_CH_k_CNTXT_0_EVCHID_SHFT 0x8
#define GSI_EE_n_EV_CH_k_CNTXT_0_EE_BMSK 0xf0
#define GSI_EE_n_EV_CH_k_CNTXT_0_EE_SHFT 0x4
#define GSI_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK 0xf
#define GSI_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT 0x0
/* GSI_EE_n_CNTXT_GLOB_IRQ_STTS */
#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_BMSK 0x8
#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_SHFT 0x3
#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_BMSK 0x4
#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_SHFT 0x2
#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_BMSK 0x2
#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_SHFT 0x1
#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_BMSK 0x1
#define GSI_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_SHFT 0x0
/* GSI_EE_n_CNTXT_GLOB_IRQ_EN */
#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT3_BMSK 0x8
#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT3_SHFT 0x3
#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT2_BMSK 0x4
#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT2_SHFT 0x2
#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT1_BMSK 0x2
#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_GP_INT1_SHFT 0x1
#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_ERROR_INT_BMSK 0x1
#define GSI_EE_n_CNTXT_GLOB_IRQ_EN_ERROR_INT_SHFT 0x0
/* GSI_EE_n_CNTXT_GSI_IRQ_STTS */
#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_BMSK 0x8
#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_SHFT 0x3
#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4
#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2
#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_BMSK 0x2
#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_SHFT 0x1
#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_BMSK 0x1
#define GSI_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_SHFT 0x0
/* GSI_EE_n_CNTXT_TYPE_IRQ */
#define GSI_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK 0x40
#define GSI_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT 0x6
#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK 0x20
#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT 0x5
#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK 0x10
#define GSI_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT 0x4
#define GSI_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK 0x8
#define GSI_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT 0x3
#define GSI_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK 0x4
#define GSI_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT 0x2
#define GSI_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK 0x2
#define GSI_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT 0x1
#define GSI_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK 0x1
#define GSI_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT 0x0
/* GSI_EE_n_GSI_HW_PARAM */
#define GSI_V1_0_EE_n_GSI_HW_PARAM_PERIPH_SEC_GRP_BMSK 0x7c000000
#define GSI_V1_0_EE_n_GSI_HW_PARAM_PERIPH_SEC_GRP_SHFT 0x1a
#define GSI_V1_0_EE_n_GSI_HW_PARAM_USE_AXI_M_BMSK 0x2000000
#define GSI_V1_0_EE_n_GSI_HW_PARAM_USE_AXI_M_SHFT 0x19
#define GSI_V1_0_EE_n_GSI_HW_PARAM_PERIPH_CONF_ADDR_BUS_W_BMSK 0x1f00000
#define GSI_V1_0_EE_n_GSI_HW_PARAM_PERIPH_CONF_ADDR_BUS_W_SHFT 0x14
#define GSI_V1_0_EE_n_GSI_HW_PARAM_NUM_EES_BMSK 0xf0000
#define GSI_V1_0_EE_n_GSI_HW_PARAM_NUM_EES_SHFT 0x10
#define GSI_V1_0_EE_n_GSI_HW_PARAM_GSI_CH_NUM_BMSK 0xff00
#define GSI_V1_0_EE_n_GSI_HW_PARAM_GSI_CH_NUM_SHFT 0x8
#define GSI_V1_0_EE_n_GSI_HW_PARAM_GSI_EV_CH_NUM_BMSK 0xff
#define GSI_V1_0_EE_n_GSI_HW_PARAM_GSI_EV_CH_NUM_SHFT 0x0
/* GSI_EE_n_GSI_HW_PARAM_0 */
#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_USE_AXI_M_BMSK 0x80000000
#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_USE_AXI_M_SHFT 0x1f
#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_PERIPH_SEC_GRP_BMSK 0x7c000000
#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_PERIPH_SEC_GRP_SHFT 0x1a
#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_PERIPH_CONF_ADDR_BUS_W_BMSK 0x3e00000
#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_PERIPH_CONF_ADDR_BUS_W_SHFT 0x15
#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_NUM_EES_BMSK 0x1f0000
#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_NUM_EES_SHFT 0x10
#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_GSI_CH_NUM_BMSK 0xff00
#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_GSI_CH_NUM_SHFT 0x8
#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_GSI_EV_CH_NUM_BMSK 0xff
#define GSI_V1_2_EE_n_GSI_HW_PARAM_0_GSI_EV_CH_NUM_SHFT 0x0
/* GSI_EE_n_GSI_HW_PARAM_2 */
#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_BMSK 0x4000
#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_SHFT 0xe
#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_BMSK 0x2000
#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_SHFT 0xd
#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK 0x1f00
#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT 0x8
#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK 0xf8
#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT 0x3
#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK 0x7
#define GSI_V1_3_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT 0x0
#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_BMSK 0x38000000
#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_SHFT 0x1b
#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_BMSK 0x7F80000
#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_SHFT 0x13
#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_BMSK 0x70000
#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_SHFT 0x10
#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_BMSK 0x8000
#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_SHFT 0xf
#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_BMSK 0x80000000
#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_SHFT 0x1f
#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_BMSK 0x40000000
#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_SHFT 0x1E
/* GSI_EE_n_GSI_STATUS */
#define GSI_EE_n_GSI_STATUS_ENABLED_BMSK 0x1
#define GSI_EE_n_GSI_STATUS_ENABLED_SHFT 0x0
/* GSI_EE_n_EV_CH_k_CNTXT_1 */
#define GSI_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff
#define GSI_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0
#define GSI_V2_9_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xfffff
#define GSI_V2_9_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0
/* GSI_EE_n_EV_CH_k_CNTXT_2 */
#define GSI_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff
#define GSI_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0
/* GSI_EE_n_EV_CH_k_CNTXT_3 */
#define GSI_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff
#define GSI_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0
/* GSI_EE_n_EV_CH_k_CNTXT_8 */
#define GSI_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_BMSK 0xff000000
#define GSI_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_SHFT 0x18
#define GSI_EE_n_EV_CH_k_CNTXT_8_INT_MODC_BMSK 0xff0000
#define GSI_EE_n_EV_CH_k_CNTXT_8_INT_MODC_SHFT 0x10
#define GSI_EE_n_EV_CH_k_CNTXT_8_INT_MODT_BMSK 0xffff
#define GSI_EE_n_EV_CH_k_CNTXT_8_INT_MODT_SHFT 0x0
/* GSI_EE_n_EV_CH_k_CNTXT_9 */
#define GSI_EE_n_EV_CH_k_CNTXT_9_INTVEC_BMSK 0xffffffff
#define GSI_EE_n_EV_CH_k_CNTXT_9_INTVEC_SHFT 0x0
/* GSI_EE_n_EV_CH_k_CNTXT_10 */
#define GSI_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_BMSK 0xffffffff
#define GSI_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_SHFT 0x0
/* GSI_EE_n_EV_CH_k_CNTXT_11 */
#define GSI_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_BMSK 0xffffffff
#define GSI_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_SHFT 0x0
/* GSI_EE_n_EV_CH_k_CNTXT_12 */
#define GSI_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_BMSK 0xffffffff
#define GSI_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_SHFT 0x0
/* GSI_EE_n_EV_CH_k_CNTXT_13 */
#define GSI_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_BMSK 0xffffffff
#define GSI_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_SHFT 0x0
/* GSI_EE_n_EV_CH_k_DOORBELL_1 */
#define GSI_EE_n_EV_CH_k_DOORBELL_1_WRITE_PTR_MSB_BMSK 0xffffffff
#define GSI_EE_n_EV_CH_k_DOORBELL_1_WRITE_PTR_MSB_SHFT 0x0
/* GSI_EE_n_EV_CH_CMD */
#define GSI_EE_n_EV_CH_CMD_OPCODE_BMSK 0xff000000
#define GSI_EE_n_EV_CH_CMD_OPCODE_SHFT 0x18
#define GSI_EE_n_EV_CH_CMD_CHID_BMSK 0xff
#define GSI_EE_n_EV_CH_CMD_CHID_SHFT 0x0
/* GSI_EE_n_GSI_CH_k_QOS */
#define GSI_EE_n_GSI_CH_k_QOS_USE_DB_ENG_BMSK 0x200
#define GSI_EE_n_GSI_CH_k_QOS_USE_DB_ENG_SHFT 0x9
#define GSI_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_BMSK 0x100
#define GSI_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_SHFT 0x8
#define GSI_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK 0xf
#define GSI_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT 0x0
#define GSI_V2_0_EE_n_GSI_CH_k_QOS_USE_ESCAPE_BUF_ONLY_BMSK 0x400
#define GSI_V2_0_EE_n_GSI_CH_k_QOS_USE_ESCAPE_BUF_ONLY_SHFT 0xa
#define GSI_V2_5_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_SHFT 0x10
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_EMPTY_LVL_THRSHOLD_BMSK 0xff0000
#define GSI_V2_5_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_BMSK 0x3c00
#define GSI_V2_5_EE_n_GSI_CH_k_QOS_PREFETCH_MODE_SHFT 0xa
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_BMSK 0x1000000
#define GSI_V2_9_EE_n_GSI_CH_k_QOS_DB_IN_BYTES_SHFT 0x18
/* GSI_EE_n_GSI_CH_k_CNTXT_1 */
#define GSI_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff
#define GSI_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0
#define GSI_V2_9_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xfffff
#define GSI_V2_9_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0
/* GSI_EE_n_GSI_CH_CMD */
#define GSI_EE_n_GSI_CH_CMD_OPCODE_BMSK 0xff000000
#define GSI_EE_n_GSI_CH_CMD_OPCODE_SHFT 0x18
#define GSI_EE_n_GSI_CH_CMD_CHID_BMSK 0xff
#define GSI_EE_n_GSI_CH_CMD_CHID_SHFT 0x0
/* GSI_GSI_CFG */
#define GSI_GSI_CFG_BP_MTRIX_DISABLE_BMSK 0x20
#define GSI_GSI_CFG_BP_MTRIX_DISABLE_SHFT 0x5
#define GSI_GSI_CFG_GSI_PWR_CLPS_BMSK 0x10
#define GSI_GSI_CFG_GSI_PWR_CLPS_SHFT 0x4
#define GSI_GSI_CFG_UC_IS_MCS_BMSK 0x8
#define GSI_GSI_CFG_UC_IS_MCS_SHFT 0x3
#define GSI_GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK 0x4
#define GSI_GSI_CFG_DOUBLE_MCS_CLK_FREQ_SHFT 0x2
#define GSI_GSI_CFG_MCS_ENABLE_BMSK 0x2
#define GSI_GSI_CFG_MCS_ENABLE_SHFT 0x1
#define GSI_GSI_CFG_GSI_ENABLE_BMSK 0x1
#define GSI_GSI_CFG_GSI_ENABLE_SHFT 0x0
#define GSI_V2_5_GSI_CFG_SLEEP_CLK_DIV_BMSK 0xf00
#define GSI_V2_5_GSI_CFG_SLEEP_CLK_DIV_SHFT 0x8
/* GSI_EE_n_GSI_EE_GENERIC_CMD */
#define GSI_EE_n_GSI_EE_GENERIC_CMD_OPCODE_BMSK 0x1f
#define GSI_EE_n_GSI_EE_GENERIC_CMD_OPCODE_SHFT 0x0
#define GSI_EE_n_GSI_EE_GENERIC_CMD_VIRT_CHAN_IDX_BMSK 0x3e0
#define GSI_EE_n_GSI_EE_GENERIC_CMD_VIRT_CHAN_IDX_SHFT 0x5
#define GSI_EE_n_GSI_EE_GENERIC_CMD_EE_BMSK 0x3c00
#define GSI_EE_n_GSI_EE_GENERIC_CMD_EE_SHFT 0xa
/* GSI_EE_n_CNTXT_GSI_IRQ_EN */
#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_MCS_STACK_OVRFLOW_BMSK 0x8
#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_MCS_STACK_OVRFLOW_SHFT 0x3
#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4
#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2
#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_BUS_ERROR_BMSK 0x2
#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_BUS_ERROR_SHFT 0x1
#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_BREAK_POINT_BMSK 0x1
#define GSI_EE_n_CNTXT_GSI_IRQ_EN_GSI_BREAK_POINT_SHFT 0x0
#endif /* _GSIHAL_REG_I_H_ */

31
drivers/platform/msm/ipa/ipa_v3/ipa.c
View File

@@ -6050,9 +6050,6 @@ static enum gsi_ver ipa3_get_gsi_ver(enum ipa_hw_type ipa_hw_type)
case IPA_HW_v4_11: case IPA_HW_v4_11:
gsi_ver = GSI_VER_2_11; gsi_ver = GSI_VER_2_11;
break; break;
case IPA_HW_v5_0:
gsi_ver = GSI_VER_3_0;
break;
default: default:
IPAERR("No GSI version for ipa type %d\n", ipa_hw_type); IPAERR("No GSI version for ipa type %d\n", ipa_hw_type);
WARN_ON(1); WARN_ON(1);
@@ -7288,20 +7285,6 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p,
goto fail_gsi_map; goto fail_gsi_map;
} }
/*
* Since we now know where the transport's registers live,
* let's set up access to them. This is done since subseqent
* functions, that deal with the transport, require the
* access.
*/
if (gsi_map_base(
ipa3_res.transport_mem_base,
ipa3_res.transport_mem_size) != 0) {
IPAERR("Allocation of gsi base failed\n");
result = -EFAULT;
goto fail_gsi_map;
}
mutex_init(&ipa3_ctx->ipa3_active_clients.mutex); mutex_init(&ipa3_ctx->ipa3_active_clients.mutex);
IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log_info, "PROXY_CLK_VOTE"); IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log_info, "PROXY_CLK_VOTE");
@@ -9014,6 +8997,20 @@ int ipa3_plat_drv_probe(struct platform_device *pdev_p)
return result; return result;
} }
/*
* Since we now know where the transport's registers live,
* let's set up access to them. This is done since subsequent
* functions, that deal with the transport, require the
* access.
*/
if (gsi_map_base(
ipa3_res.transport_mem_base,
ipa3_res.transport_mem_size,
ipa3_get_gsi_ver(ipa3_res.ipa_hw_type)) != 0) {
IPAERR("Allocation of gsi base failed\n");
return -EFAULT;
}
/* Get GSI version */ /* Get GSI version */
ipa3_ctx->gsi_ver = ipa3_get_gsi_ver(ipa3_res.ipa_hw_type); ipa3_ctx->gsi_ver = ipa3_get_gsi_ver(ipa3_res.ipa_hw_type);

42
drivers/platform/msm/ipa/test/ipa_test_mhi.c
View File

@@ -8,7 +8,7 @@
#include <linux/ipa.h> #include <linux/ipa.h>
#include "ipa_i.h" #include "ipa_i.h"
#include "gsi.h" #include "gsi.h"
#include "gsi_reg.h" #include "gsihal.h"
#include "ipa_ut_framework.h" #include "ipa_ut_framework.h"
#define IPA_MHI_TEST_NUM_CHANNELS 8 #define IPA_MHI_TEST_NUM_CHANNELS 8
@@ -322,7 +322,6 @@ struct ipa_mhi_transfer_ring_element {
* struct ipa_test_mhi_context - MHI test context * struct ipa_test_mhi_context - MHI test context
*/ */
struct ipa_test_mhi_context { struct ipa_test_mhi_context {
void __iomem *gsi_mmio;
struct ipa_mem_buffer msi; struct ipa_mem_buffer msi;
struct ipa_mem_buffer ch_ctx_array; struct ipa_mem_buffer ch_ctx_array;
struct ipa_mem_buffer ev_ctx_array; struct ipa_mem_buffer ev_ctx_array;
@@ -809,20 +808,10 @@ static int ipa_test_mhi_suite_setup(void **ppriv)
goto fail_free_ctx; goto fail_free_ctx;
} }
test_mhi_ctx->gsi_mmio =
ioremap(test_mhi_ctx->transport_phys_addr,
test_mhi_ctx->transport_size);
if (!test_mhi_ctx->gsi_mmio) {
IPA_UT_ERR("failed to remap GSI HW size=%lu\n",
test_mhi_ctx->transport_size);
rc = -EFAULT;
goto fail_free_ctx;
}
rc = ipa_test_mhi_alloc_mmio_space(); rc = ipa_test_mhi_alloc_mmio_space();
if (rc) { if (rc) {
IPA_UT_ERR("failed to alloc mmio space"); IPA_UT_ERR("failed to alloc mmio space");
goto fail_iounmap; goto fail_free_ctx;
} }
rc = ipa_mhi_test_setup_data_structures(); rc = ipa_mhi_test_setup_data_structures();
@@ -849,8 +838,6 @@ fail_destroy_data_structures:
ipa_mhi_test_destroy_data_structures(); ipa_mhi_test_destroy_data_structures();
fail_free_mmio_spc: fail_free_mmio_spc:
ipa_test_mhi_free_mmio_space(); ipa_test_mhi_free_mmio_space();
fail_iounmap:
iounmap(test_mhi_ctx->gsi_mmio);
fail_free_ctx: fail_free_ctx:
kfree(test_mhi_ctx); kfree(test_mhi_ctx);
test_mhi_ctx = NULL; test_mhi_ctx = NULL;
@@ -870,7 +857,6 @@ static int ipa_test_mhi_suite_teardown(void *priv)
ipa_teardown_sys_pipe(test_mhi_ctx->test_prod_hdl); ipa_teardown_sys_pipe(test_mhi_ctx->test_prod_hdl);
ipa_mhi_test_destroy_data_structures(); ipa_mhi_test_destroy_data_structures();
ipa_test_mhi_free_mmio_space(); ipa_test_mhi_free_mmio_space();
iounmap(test_mhi_ctx->gsi_mmio);
kfree(test_mhi_ctx); kfree(test_mhi_ctx);
test_mhi_ctx = NULL; test_mhi_ctx = NULL;
@@ -1399,12 +1385,11 @@ static int ipa_mhi_test_q_transfer_re(struct ipa_mem_buffer *mmio,
IPA_UT_LOG("DB to event 0x%llx: base %pa ofst 0x%x\n", IPA_UT_LOG("DB to event 0x%llx: base %pa ofst 0x%x\n",
p_events[event_ring_index].wp, p_events[event_ring_index].wp,
&(test_mhi_ctx->transport_phys_addr), &(test_mhi_ctx->transport_phys_addr),
GSI_EE_n_EV_CH_k_DOORBELL_0_OFFS( gsihal_get_reg_nk_ofst(GSI_EE_n_EV_CH_k_DOORBELL_0, 0,
event_ring_index + ipa3_ctx->mhi_evid_limits[0], 0)); event_ring_index + ipa3_ctx->mhi_evid_limits[0]));
iowrite32(p_events[event_ring_index].wp, gsihal_write_reg_nk(GSI_EE_n_EV_CH_k_DOORBELL_0, 0,
test_mhi_ctx->gsi_mmio + event_ring_index + ipa3_ctx->mhi_evid_limits[0],
GSI_EE_n_EV_CH_k_DOORBELL_0_OFFS( p_events[event_ring_index].wp);
event_ring_index + ipa3_ctx->mhi_evid_limits[0], 0));
} }
for (i = 0; i < buf_array_size; i++) { for (i = 0; i < buf_array_size; i++) {
@@ -1446,12 +1431,13 @@ static int ipa_mhi_test_q_transfer_re(struct ipa_mem_buffer *mmio,
"DB to channel 0x%llx: base %pa ofst 0x%x\n" "DB to channel 0x%llx: base %pa ofst 0x%x\n"
, p_channels[channel_idx].wp , p_channels[channel_idx].wp
, &(test_mhi_ctx->transport_phys_addr) , &(test_mhi_ctx->transport_phys_addr)
, GSI_EE_n_GSI_CH_k_DOORBELL_0_OFFS( , gsihal_get_reg_nk_ofst(
channel_idx, 0)); GSI_EE_n_GSI_CH_k_DOORBELL_0,
iowrite32(p_channels[channel_idx].wp, 0, channel_idx));
test_mhi_ctx->gsi_mmio + gsihal_write_reg_nk(
GSI_EE_n_GSI_CH_k_DOORBELL_0_OFFS( GSI_EE_n_GSI_CH_k_DOORBELL_0,
channel_idx, 0)); 0, channel_idx,
p_channels[channel_idx].wp);
} }
} else { } else {
curr_re->word_C.bits.chain = 1; curr_re->word_C.bits.chain = 1;