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@@ -118,6 +118,11 @@ enum cnss_vreg_type {
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CNSS_VREG_PRIM,
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};
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+enum cnss_pci_switch_type {
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+ PCIE_DIRECT_ATTACH = 0,
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+ PCIE_SWITCH_NTN3,
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+};
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+
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struct cnss_clk_cfg {
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const char *name;
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u32 freq;
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@@ -650,6 +655,7 @@ struct cnss_plat_data {
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bool sleep_clk;
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struct wlchip_serial_id_v01 serial_id;
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bool ipa_shared_cb_enable;
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+ u32 pcie_switch_type;
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};
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#if IS_ENABLED(CONFIG_ARCH_QCOM)
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@@ -741,6 +747,7 @@ void cnss_aop_interface_deinit(struct cnss_plat_data *plat_priv);
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int cnss_aop_pdc_reconfig(struct cnss_plat_data *plat_priv);
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int cnss_aop_send_msg(struct cnss_plat_data *plat_priv, char *msg);
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void cnss_power_misc_params_init(struct cnss_plat_data *plat_priv);
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+void cnss_pci_of_switch_type_init(struct cnss_plat_data *plat_priv);
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int cnss_aop_ol_cpr_cfg_setup(struct cnss_plat_data *plat_priv,
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struct wlfw_pmu_cfg_v01 *fw_pmu_cfg);
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int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
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