qcacmn: Support RX 2K jump/OOR frame handling from REO2TCL ring
Support RX 2K jump/OOR frame handling from REO2TCL ring. (a) configure REO error destination ring register to route 2K jump /OOR frame to REO2TCL ring. (b) for 2K jump RX frame, only accept ARP frame and drop others, meanwhile, send delba action frame to remote peer once receive first 2K jump data. (c) for OOR RX frame, accept ARP/EAPOL/DHCP/IPV6_DHCP frame, otherwise drop it. Change-Id: I7cb33279a8ba543686da4eba547e40f86813e057 CRs-Fixed: 2631949
このコミットが含まれているのは:
@@ -815,6 +815,15 @@ extern void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
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#define REO_REMAP_FW 6
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#define REO_REMAP_UNUSED 7
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/*
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* Macro to access HWIO_REO_R0_ERROR_DESTINATION_RING_CTRL_IX_0
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* to map destination to rings
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*/
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#define HAL_REO_ERR_REMAP_IX0(_VALUE, _OFFSET) \
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((_VALUE) << \
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(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_ ## \
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DESTINATION_RING_ ## _OFFSET ## _SHFT))
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/*
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* Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0
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* to map destination to rings
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@@ -2052,4 +2061,20 @@ hal_rx_sw_mon_desc_info_get(struct hal_soc *hal,
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{
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return hal->ops->hal_rx_sw_mon_desc_info_get(ring_desc, desc_info);
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}
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/**
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* hal_reo_set_err_dst_remap() - Set REO error destination ring remap
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* register value.
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*
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* @hal_soc_hdl: Opaque HAL soc handle
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*
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* Return: None
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*/
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static inline void hal_reo_set_err_dst_remap(hal_soc_handle_t hal_soc_hdl)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (hal_soc->ops->hal_reo_set_err_dst_remap)
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hal_soc->ops->hal_reo_set_err_dst_remap(hal_soc);
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}
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#endif /* _HAL_APIH_ */
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@@ -1630,7 +1630,6 @@ static void hal_reo_setup_generic(struct hal_soc *soc,
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SEQ_WCSS_UMAC_REO_REG_OFFSET)));
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}
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/* TODO: Check if the following registers shoould be setup by host:
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* AGING_CONTROL
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* HIGH_MEMORY_THRESHOLD
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@@ -469,6 +469,7 @@ struct hal_hw_txrx_ops {
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uint32_t num_entries);
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qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc,
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qdf_iomem_t addr);
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void (*hal_reo_set_err_dst_remap)(void *hal_soc);
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/* tx */
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void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id);
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@@ -2121,6 +2121,22 @@ static inline bool hal_rx_reo_is_2k_jump(hal_ring_desc_t rx_desc)
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true : false;
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}
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/**
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* hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR
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*
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* @ring_desc: opaque pointer used by HAL to get the REO destination entry
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*
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* Return: true: error caused by OOR, false: other error
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*/
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static inline bool hal_rx_reo_is_oor_error(void *rx_desc)
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{
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struct reo_destination_ring *reo_desc =
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(struct reo_destination_ring *)rx_desc;
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return (HAL_RX_REO_ERROR_GET(reo_desc) ==
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HAL_REO_ERR_REGULAR_FRAME_OOR) ? true : false;
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}
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#define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING)
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/**
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* hal_dump_wbm_rel_desc() - dump wbm release descriptor
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@@ -3656,4 +3672,63 @@ hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl,
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return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr);
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}
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/**
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* hal_rx_buffer_addr_info_get_paddr(): get paddr/sw_cookie from
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* <struct buffer_addr_info> structure
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* @buf_addr_info: pointer to <struct buffer_addr_info> structure
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* @buf_info: structure to return the buffer information including
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* paddr/cookie
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*
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* return: None
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*/
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static inline
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void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info,
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struct hal_buf_info *buf_info)
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{
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buf_info->paddr =
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(HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
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((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
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buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
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}
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/**
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* hal_rx_get_next_msdu_link_desc_buf_addr_info(): get next msdu link desc
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* buffer addr info
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* @link_desc_va: pointer to current msdu link Desc
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* @next_addr_info: buffer to save next msdu link Desc buffer addr info
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*
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* return: None
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*/
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static inline
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void hal_rx_get_next_msdu_link_desc_buf_addr_info(
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void *link_desc_va,
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struct buffer_addr_info *next_addr_info)
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{
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struct rx_msdu_link *msdu_link = link_desc_va;
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if (!msdu_link) {
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qdf_mem_zero(next_addr_info,
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sizeof(struct buffer_addr_info));
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return;
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}
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*next_addr_info = msdu_link->next_msdu_link_desc_addr_info;
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}
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/**
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* hal_rx_is_buf_addr_info_valid(): check is the buf_addr_info valid
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*
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* @buf_addr_info: pointer to buf_addr_info structure
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*
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* return: true: has valid paddr, false: not.
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*/
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static inline
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bool hal_rx_is_buf_addr_info_valid(
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struct buffer_addr_info *buf_addr_info)
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{
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return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ?
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false : true;
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}
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#endif /* _HAL_RX_H */
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@@ -1352,6 +1352,7 @@ struct hal_hw_txrx_ops qca5018_hal_hw_txrx_ops = {
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hal_reo_setup_generic,
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hal_setup_link_idle_list_generic,
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hal_get_window_address_5018,
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NULL,
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/* tx */
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hal_tx_desc_set_dscp_tid_table_id_5018,
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@@ -1000,6 +1000,7 @@ struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
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hal_reo_setup_generic,
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hal_setup_link_idle_list_generic,
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hal_get_window_address_6290,
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NULL,
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/* tx */
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hal_tx_desc_set_dscp_tid_table_id_6290,
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@@ -988,6 +988,44 @@ static inline qdf_iomem_t hal_get_window_address_6390(struct hal_soc *hal_soc,
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return addr;
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}
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/**
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* hal_reo_set_err_dst_remap_6390(): Function to set REO error destination
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* ring remap register
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* @hal_soc: Pointer to hal_soc
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*
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* Return: none.
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*/
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static void
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hal_reo_set_err_dst_remap_6390(void *hal_soc)
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{
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/*
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* Set REO error 2k jump (error code 5) / OOR (error code 7)
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* frame routed to REO2TCL ring.
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*/
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uint32_t dst_remap_ix0 =
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 6) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 8) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 9);
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HAL_REG_WRITE(hal_soc,
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HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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dst_remap_ix0);
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hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x",
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HAL_REG_READ(
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hal_soc,
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HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET)));
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}
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struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
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/* init and setup */
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hal_srng_dst_hw_init_generic,
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@@ -996,6 +1034,7 @@ struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
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hal_reo_setup_generic,
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hal_setup_link_idle_list_generic,
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hal_get_window_address_6390,
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hal_reo_set_err_dst_remap_6390,
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/* tx */
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hal_tx_desc_set_dscp_tid_table_id_6390,
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@@ -1411,6 +1411,42 @@ bool hal_rx_get_fisa_timeout_6490(uint8_t *buf)
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return HAL_RX_TLV_GET_FISA_TIMEOUT(buf);
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}
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/**
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* hal_reo_set_err_dst_remap_6490(): Function to set REO error destination
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* ring remap register
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* @hal_soc: Pointer to hal_soc
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*
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* Return: none.
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*/
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static void
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hal_reo_set_err_dst_remap_6490(void *hal_soc)
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{
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/*
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* Set REO error 2k jump (error code 5) / OOR (error code 7)
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* frame routed to REO2TCL ring.
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*/
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uint32_t dst_remap_ix0 =
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 6) |
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HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7);
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HAL_REG_WRITE(hal_soc,
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HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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dst_remap_ix0);
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hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x",
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HAL_REG_READ(
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hal_soc,
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HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET)));
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}
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struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
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/* init and setup */
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hal_srng_dst_hw_init_generic,
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@@ -1419,6 +1455,7 @@ struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
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hal_reo_setup_generic,
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hal_setup_link_idle_list_generic,
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hal_get_window_address_6490,
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hal_reo_set_err_dst_remap_6490,
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/* tx */
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hal_tx_desc_set_dscp_tid_table_id_6490,
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@@ -1330,6 +1330,7 @@ struct hal_hw_txrx_ops qca6750_hal_hw_txrx_ops = {
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hal_reo_setup_generic,
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hal_setup_link_idle_list_generic,
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hal_get_window_address_6750,
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NULL,
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/* tx */
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hal_tx_desc_set_dscp_tid_table_id_6750,
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@@ -1021,6 +1021,7 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
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hal_reo_setup_generic,
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hal_setup_link_idle_list_generic,
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hal_get_window_address_8074,
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NULL,
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/* tx */
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hal_tx_desc_set_dscp_tid_table_id_8074,
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@@ -1018,6 +1018,7 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
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hal_reo_setup_generic,
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hal_setup_link_idle_list_generic,
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hal_get_window_address_8074v2,
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NULL,
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/* tx */
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hal_tx_desc_set_dscp_tid_table_id_8074v2,
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@@ -1473,6 +1473,7 @@ struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
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hal_reo_setup_generic,
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hal_setup_link_idle_list_generic,
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hal_get_window_address_9000,
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NULL,
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/* tx */
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hal_tx_desc_set_dscp_tid_table_id_9000,
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