qcacld-3.0: Add changes to support DP memory profile

Introduce DP memory profile selection based on H.W
capabilities supported. Based on H.W capabilities
decide kind of memory profile required for DP operations
and select that profile for resource allocation, so that
resource/memory allocation will be done effectively.

Change-Id: Iffbea0cfd9e6b79f0c1ad9526217ba6922f6cdb6
CRs-Fixed: 3504128

components/dp/core/inc/wlan_dp_main.h

@@ -808,4 +808,45 @@ __wlan_dp_update_peer_map_unmap_version(uint8_t *version)
 {
 }
 #endif
+
+#ifdef WLAN_DP_PROFILE_SUPPORT
+/**
+ * wlan_dp_get_profile_info() - Get DP memory profile info
+ *
+ * Return: None
+ */
+struct wlan_dp_memory_profile_info *wlan_dp_get_profile_info(void);
+
+/**
+ * wlan_dp_select_profile_cfg() - Select DP profile configuration
+ * @psoc: psoc context
+ *
+ * Return: QDF_STATUS
+ */
+QDF_STATUS wlan_dp_select_profile_cfg(struct wlan_objmgr_psoc *psoc);
+
+/**
+ * wlan_dp_soc_cfg_sync_profile() - Sync DP soc cfg items with profile
+ * @cdp_soc: cdp soc context
+ *
+ * Return: None
+ */
+void wlan_dp_soc_cfg_sync_profile(struct cdp_soc_t *cdp_soc);
+
+/**
+ * wlan_dp_pdev_cfg_sync_profile() - Sync DP pdev cfg items with profile
+ * @cdp_soc: cdp soc context
+ * @pdev_id: pdev id
+ *
+ * Return: QDF_STATUS
+ */
+void wlan_dp_pdev_cfg_sync_profile(struct cdp_soc_t *cdp_soc, uint8_t pdev_id);
+#else
+
+static inline
+QDF_STATUS wlan_dp_select_profile_cfg(struct wlan_objmgr_psoc *psoc)
+{
+	return QDF_STATUS_E_NOSUPPORT;
+}
+#endif
 #endif

components/dp/core/inc/wlan_dp_priv.h

@@ -603,4 +603,52 @@ struct wlan_dp_psoc_context {
 #endif
 };
 
+#ifdef WLAN_DP_PROFILE_SUPPORT
+/**
+ * enum wlan_dp_cfg_param_type - param context type
+ * @DP_TX_DESC_NUM_CFG: Number of TX desc
+ * @DP_TX_EXT_DESC_NUM_CFG: Number of TX ext desc
+ * @DP_TX_RING_SIZE_CFG: TX ring size
+ * @DP_TX_COMPL_RING_SIZE_CFG: TX completion ring size
+ * @DP_RX_SW_DESC_NUM_CFG: Number of RX S.W descriptors
+ * @DP_REO_DST_RING_SIZE_CFG: RX ring size
+ * @DP_RXDMA_BUF_RING_SIZE_CFG: RXDMA BUF ring size
+ * @DP_RXDMA_REFILL_RING_SIZE_CFG: RXDMA refill ring size
+ * @DP_RX_REFILL_POOL_NUM_CFG: Refill buffer pool size
+ */
+enum wlan_dp_cfg_param_type {
+	DP_TX_DESC_NUM_CFG,
+	DP_TX_EXT_DESC_NUM_CFG,
+	DP_TX_RING_SIZE_CFG,
+	DP_TX_COMPL_RING_SIZE_CFG,
+	DP_RX_SW_DESC_NUM_CFG,
+	DP_REO_DST_RING_SIZE_CFG,
+	DP_RXDMA_BUF_RING_SIZE_CFG,
+	DP_RXDMA_REFILL_RING_SIZE_CFG,
+	DP_RX_REFILL_POOL_NUM_CFG,
+};
+
+/**
+ * struct wlan_dp_memory_profile_ctx - element representing DP config param info
+ * @param_type: DP config param type
+ * @size: size/length of the param to be selected
+ */
+struct wlan_dp_memory_profile_ctx {
+	enum wlan_dp_cfg_param_type param_type;
+	uint32_t size;
+};
+
+/**
+ * struct wlan_dp_memory_profile_info - Current memory profile info
+ * @is_selected: profile is selected or not
+ * @ctx: DP memory profile context
+ * @size: size of profile
+ */
+struct wlan_dp_memory_profile_info {
+	bool is_selected;
+	struct wlan_dp_memory_profile_ctx *ctx;
+	int size;
+};
+#endif
+
 #endif /* end  of _WLAN_DP_PRIV_STRUCT_H_ */

components/dp/core/src/wlan_dp_main.c

@@ -38,9 +38,29 @@
 #include <htc_api.h>
 #include <cdp_txrx_cmn_reg.h>
 #include <cdp_txrx_bus.h>
+#if defined(WLAN_DP_PROFILE_SUPPORT) || defined(FEATURE_DIRECT_LINK)
+#include "cdp_txrx_ctrl.h"
+#endif
 #ifdef FEATURE_DIRECT_LINK
 #include "dp_internal.h"
-#include "cdp_txrx_ctrl.h"
+#endif
+
+#ifdef WLAN_DP_PROFILE_SUPPORT
+/* Memory profile table based on supported caps */
+static struct wlan_dp_memory_profile_ctx wlan_dp_1x1_he80_1kqam[] = {
+	{DP_TX_DESC_NUM_CFG, 1024},
+	{DP_TX_EXT_DESC_NUM_CFG, 1024},
+	{DP_TX_RING_SIZE_CFG, 1024},
+	{DP_TX_COMPL_RING_SIZE_CFG, 1024},
+	{DP_RX_SW_DESC_NUM_CFG, 1024},
+	{DP_REO_DST_RING_SIZE_CFG, 1024},
+	{DP_RXDMA_BUF_RING_SIZE_CFG, 1024},
+	{DP_RXDMA_REFILL_RING_SIZE_CFG, 1024},
+	{DP_RX_REFILL_POOL_NUM_CFG, 1024},
+};
+
+/* Global data structure to save profile info */
+static struct wlan_dp_memory_profile_info g_dp_profile_info;
 #endif
 
 /* Global DP context */
@@ -1944,3 +1964,247 @@ QDF_STATUS dp_config_direct_link(struct wlan_dp_intf *dp_intf,
 	return status;
 }
 #endif
+
+#ifdef WLAN_DP_PROFILE_SUPPORT
+struct wlan_dp_memory_profile_info *
+wlan_dp_get_profile_info(void)
+{
+	return &g_dp_profile_info;
+}
+
+QDF_STATUS wlan_dp_select_profile_cfg(struct wlan_objmgr_psoc *psoc)
+{
+	struct pld_soc_info info = {0};
+	struct pld_wlan_hw_cap_info *hw_cap_info;
+	qdf_device_t qdf_dev;
+	bool apply_profile = false;
+	int ret;
+
+	apply_profile = cfg_get(psoc,
+				CFG_DP_APPLY_MEM_PROFILE);
+	if (!apply_profile)
+		return QDF_STATUS_E_NOSUPPORT;
+
+	qdf_dev = wlan_psoc_get_qdf_dev(psoc);
+	if (!qdf_dev)
+		return QDF_STATUS_E_FAILURE;
+
+	ret = pld_get_soc_info(qdf_dev->dev, &info);
+	if (ret) {
+		dp_err("profile selection failed unable to H.W caps reason:%u",
+		       qdf_status_from_os_return(ret));
+		return qdf_status_from_os_return(ret);
+	}
+
+	hw_cap_info = &info.hw_cap_info;
+	/* Based on supported H.W caps select required memory profile */
+	if (hw_cap_info->nss == PLD_WLAN_HW_CAP_NSS_1x1 &&
+	    hw_cap_info->bw == PLD_WLAN_HW_CHANNEL_BW_80MHZ &&
+	    hw_cap_info->qam == PLD_WLAN_HW_QAM_1K) {
+		g_dp_profile_info.is_selected = true;
+		g_dp_profile_info.ctx = wlan_dp_1x1_he80_1kqam;
+		g_dp_profile_info.size = QDF_ARRAY_SIZE(wlan_dp_1x1_he80_1kqam);
+		dp_info("DP profile selected is 1x1_HE80_1KQAM based");
+	}
+
+	return QDF_STATUS_SUCCESS;
+}
+
+#ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL
+static void
+wlan_dp_rx_refill_pool_cfg_sync_profile(struct cdp_soc_t *cdp_soc,
+				struct wlan_dp_memory_profile_ctx *profile_ctx)
+{
+	cdp_config_param_type val;
+	QDF_STATUS status;
+	int cur_val;
+
+	status = cdp_txrx_get_psoc_param(cdp_soc, CDP_CFG_RX_REFILL_POOL_NUM,
+					 &val);
+	if (QDF_IS_STATUS_SUCCESS(status) &&
+	    val.cdp_rx_refill_buf_pool_size != profile_ctx->size) {
+		cur_val = val.cdp_rx_refill_buf_pool_size;
+		val.cdp_rx_refill_buf_pool_size = profile_ctx->size;
+		if (cdp_txrx_set_psoc_param(cdp_soc,
+					    CDP_CFG_RX_REFILL_POOL_NUM, val)) {
+			dp_err("unable to sync param type:%u", profile_ctx->param_type);
+			return;
+		}
+		dp_info("current Rx refill pool size:%u synced with profile:%u",
+			cur_val, profile_ctx->size);
+	}
+}
+#else
+static inline void
+wlan_dp_rx_refill_pool_cfg_sync_profile(struct cdp_soc_t *cdp_soc,
+				struct wlan_dp_memory_profile_ctx *profile_ctx)
+{
+}
+#endif
+
+void wlan_dp_soc_cfg_sync_profile(struct cdp_soc_t *cdp_soc)
+{
+	struct wlan_dp_memory_profile_info *profile_info;
+	struct wlan_dp_memory_profile_ctx *profile_ctx;
+	cdp_config_param_type val = {0};
+	QDF_STATUS status;
+	int cur_val, i;
+
+	profile_info = wlan_dp_get_profile_info();
+	if (!profile_info->is_selected)
+		return;
+
+	for (i = 0; i < profile_info->size; i++) {
+		profile_ctx = &profile_info->ctx[i];
+	       qdf_mem_zero(&val, sizeof(cdp_config_param_type));
+
+		switch (profile_ctx->param_type) {
+		case DP_TX_DESC_NUM_CFG:
+			status = cdp_txrx_get_psoc_param(cdp_soc,
+						CDP_CFG_TX_DESC_NUM, &val);
+			if (QDF_IS_STATUS_SUCCESS(status) &&
+			    val.cdp_tx_desc_num != profile_ctx->size) {
+				cur_val = val.cdp_tx_desc_num;
+				val.cdp_tx_desc_num = profile_ctx->size;
+				if (cdp_txrx_set_psoc_param(cdp_soc,
+						CDP_CFG_TX_DESC_NUM, val)) {
+					dp_err("unable to sync param type:%u", profile_ctx->param_type);
+					break;
+				}
+				dp_info("current Tx desc num:%u synced with profile:%u", cur_val, profile_ctx->size);
+			}
+			break;
+		case DP_TX_EXT_DESC_NUM_CFG:
+			status = cdp_txrx_get_psoc_param(cdp_soc,
+						CDP_CFG_TX_EXT_DESC_NUM, &val);
+			if (QDF_IS_STATUS_SUCCESS(status) &&
+			    val.cdp_tx_ext_desc_num != profile_ctx->size) {
+				cur_val = val.cdp_tx_ext_desc_num;
+				val.cdp_tx_ext_desc_num = profile_ctx->size;
+				if (cdp_txrx_set_psoc_param(cdp_soc,
+						CDP_CFG_TX_EXT_DESC_NUM, val)) {
+					dp_err("unable to sync param type:%u", profile_ctx->param_type);
+					break;
+				}
+				dp_info("current Ext Tx desc num:%u synced with profile:%u", cur_val, profile_ctx->size);
+			}
+			break;
+		case DP_TX_RING_SIZE_CFG:
+			status = cdp_txrx_get_psoc_param(cdp_soc,
+						CDP_CFG_TX_RING_SIZE, &val);
+			if (QDF_IS_STATUS_SUCCESS(status) &&
+			    val.cdp_tx_ring_size != profile_ctx->size) {
+				cur_val = val.cdp_tx_ring_size;
+				val.cdp_tx_ring_size = profile_ctx->size;
+				if (cdp_txrx_set_psoc_param(cdp_soc,
+						CDP_CFG_TX_RING_SIZE, val)) {
+					dp_err("unable to sync param type:%u", profile_ctx->param_type);
+					break;
+				}
+				dp_info("current Tx Ring size:%u synced with profile:%u", cur_val, profile_ctx->size);
+			}
+			break;
+		case DP_TX_COMPL_RING_SIZE_CFG:
+			status = cdp_txrx_get_psoc_param(cdp_soc,
+						CDP_CFG_TX_COMPL_RING_SIZE, &val);
+			if (QDF_IS_STATUS_SUCCESS(status) &&
+			    val.cdp_tx_comp_ring_size != profile_ctx->size) {
+				cur_val = val.cdp_tx_comp_ring_size;
+				val.cdp_tx_comp_ring_size = profile_ctx->size;
+				if (cdp_txrx_set_psoc_param(cdp_soc,
+							    CDP_CFG_TX_COMPL_RING_SIZE, val)) {
+					dp_err("unable to sync param type:%u", profile_ctx->param_type);
+					break;
+				}
+				dp_info("current Tx Comp Ring size:%u synced with profile:%u", cur_val, profile_ctx->size);
+			}
+			break;
+		case DP_RX_SW_DESC_NUM_CFG:
+			status = cdp_txrx_get_psoc_param(cdp_soc,
+						CDP_CFG_RX_SW_DESC_NUM, &val);
+			if (QDF_IS_STATUS_SUCCESS(status) &&
+			    val.cdp_rx_sw_desc_num != profile_ctx->size) {
+				cur_val = val.cdp_rx_sw_desc_num;
+				val.cdp_rx_sw_desc_num = profile_ctx->size;
+				if (cdp_txrx_set_psoc_param(cdp_soc,
+							    CDP_CFG_RX_SW_DESC_NUM, val)) {
+					dp_err("unable to sync param type:%u", profile_ctx->param_type);
+					break;
+				}
+				dp_info("current Rx desc num:%u synced with profile:%u", cur_val, profile_ctx->size);
+			}
+			break;
+		case DP_REO_DST_RING_SIZE_CFG:
+			status = cdp_txrx_get_psoc_param(cdp_soc,
+						CDP_CFG_REO_DST_RING_SIZE, &val);
+			if (QDF_IS_STATUS_SUCCESS(status) &&
+			    val.cdp_reo_dst_ring_size != profile_ctx->size) {
+				cur_val = val.cdp_reo_dst_ring_size;
+				val.cdp_reo_dst_ring_size = profile_ctx->size;
+				if (cdp_txrx_set_psoc_param(cdp_soc,
+							    CDP_CFG_REO_DST_RING_SIZE, val)) {
+					dp_err("unable to sync param type:%u", profile_ctx->param_type);
+					break;
+				}
+				dp_info("current Rx Ring size:%u synced with profile:%u", cur_val, profile_ctx->size);
+			}
+			break;
+		case DP_RXDMA_REFILL_RING_SIZE_CFG:
+			status = cdp_txrx_get_psoc_param(cdp_soc,
+						CDP_CFG_RXDMA_REFILL_RING_SIZE, &val);
+			if (QDF_IS_STATUS_SUCCESS(status) &&
+			    val.cdp_rxdma_refill_ring_size != profile_ctx->size) {
+				cur_val = val.cdp_rxdma_refill_ring_size;
+				val.cdp_rxdma_refill_ring_size = profile_ctx->size;
+				if (cdp_txrx_set_psoc_param(cdp_soc,
+							    CDP_CFG_RXDMA_REFILL_RING_SIZE, val)) {
+					dp_err("unable to sync param type:%u", profile_ctx->param_type);
+					break;
+				}
+				dp_info("current RXDMA refill ring size:%u synced with profile:%u", cur_val, profile_ctx->size);
+			}
+		case DP_RX_REFILL_POOL_NUM_CFG:
+			wlan_dp_rx_refill_pool_cfg_sync_profile(cdp_soc,
+								profile_ctx);
+		default:
+			dp_debug("Unknown profile param type:%u", profile_ctx->param_type);
+			break;
+		}
+	}
+}
+
+void wlan_dp_pdev_cfg_sync_profile(struct cdp_soc_t *cdp_soc, uint8_t pdev_id)
+{
+	struct wlan_dp_memory_profile_info *profile_info;
+	struct wlan_dp_memory_profile_ctx *profile_ctx;
+	cdp_config_param_type val = {0};
+	QDF_STATUS status;
+	int cur_val, i;
+
+	profile_info = wlan_dp_get_profile_info();
+	if (!profile_info->is_selected)
+		return;
+
+	for (i = 0; i < profile_info->size; i++) {
+		profile_ctx = &profile_info->ctx[i];
+		if (profile_ctx->param_type == DP_RXDMA_BUF_RING_SIZE_CFG) {
+			status = cdp_txrx_get_pdev_param(cdp_soc, pdev_id,
+					CDP_CONFIG_RXDMA_BUF_RING_SIZE, &val);
+			if (QDF_IS_STATUS_SUCCESS(status) &&
+			    val.cdp_rxdma_buf_ring_size != profile_ctx->size) {
+				cur_val = val.cdp_rxdma_buf_ring_size;
+				val.cdp_rxdma_buf_ring_size = profile_ctx->size;
+				if (cdp_txrx_set_pdev_param(cdp_soc, pdev_id,
+							    CDP_CONFIG_RXDMA_BUF_RING_SIZE, val)) {
+					dp_err("unable to sync param type:%u", profile_ctx->param_type);
+					return;
+				}
+				dp_info("current RXDMA buf ring size:%u synced with profile:%u", cur_val, profile_ctx->size);
+			}
+			return;
+		}
+	}
+
+	dp_err("pdev based config item not found in profile table");
+}
+#endif

components/dp/core/src/wlan_dp_prealloc.c

@@ -17,6 +17,7 @@
  */
 
 #include <wlan_objmgr_pdev_obj.h>
+#include <wlan_dp_main.h>
 #include <wlan_dp_prealloc.h>
 #include <dp_types.h>
 #include <dp_internal.h>
@@ -395,8 +396,7 @@ static struct  dp_multi_page_prealloc g_dp_multi_page_allocs[] = {
 
 	/* DP RX DESCs BUF pools */
 	{QDF_DP_RX_DESC_BUF_TYPE, sizeof(union dp_rx_desc_list_elem_t),
-	 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE * WLAN_CFG_RXDMA_REFILL_RING_SIZE, 0,
-	 CACHEABLE, { 0 } },
+	 0, 0, CACHEABLE, { 0 } },
 
 #ifdef DISABLE_MON_CONFIG
 	/* no op */
@@ -684,11 +684,65 @@ dp_update_num_elements_by_desc_type(struct wlan_dp_prealloc_cfg *cfg,
 	case QDF_DP_TX_TSO_NUM_SEG_TYPE:
 		*num_elements = cfg->num_tx_ext_desc;
 		return;
+	case QDF_DP_RX_DESC_BUF_TYPE:
+		*num_elements = cfg->num_rx_sw_desc * WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE;
+		return;
 	default:
 		return;
 	}
 }
 
+#ifdef WLAN_DP_PROFILE_SUPPORT
+static void
+wlan_dp_sync_prealloc_with_profile_cfg(struct wlan_dp_prealloc_cfg *cfg)
+{
+	struct wlan_dp_memory_profile_info *profile_info;
+	struct wlan_dp_memory_profile_ctx *profile_ctx;
+	int i;
+
+	profile_info = wlan_dp_get_profile_info();
+	if (!profile_info->is_selected)
+		return;
+
+	for (i = 0; i < profile_info->size; i++) {
+		profile_ctx = &profile_info->ctx[i];
+
+		switch (profile_ctx->param_type) {
+		case DP_TX_DESC_NUM_CFG:
+			cfg->num_tx_desc = profile_ctx->size;
+			break;
+		case DP_TX_EXT_DESC_NUM_CFG:
+			cfg->num_tx_ext_desc = profile_ctx->size;
+			break;
+		case DP_TX_RING_SIZE_CFG:
+			cfg->num_tx_ring_entries = profile_ctx->size;
+			break;
+		case DP_TX_COMPL_RING_SIZE_CFG:
+			cfg->num_tx_comp_ring_entries = profile_ctx->size;
+			break;
+		case DP_RX_SW_DESC_NUM_CFG:
+			cfg->num_rx_sw_desc = profile_ctx->size;
+			break;
+		case DP_REO_DST_RING_SIZE_CFG:
+			cfg->num_reo_dst_ring_entries = profile_ctx->size;
+			break;
+		case DP_RXDMA_BUF_RING_SIZE_CFG:
+			cfg->num_rxdma_buf_ring_entries = profile_ctx->size;
+			break;
+		case DP_RXDMA_REFILL_RING_SIZE_CFG:
+			cfg->num_rxdma_refill_ring_entries = profile_ctx->size;
+			break;
+		default:
+			break;
+		}
+	}
+}
+#else
+
+static inline void
+wlan_dp_sync_prealloc_with_profile_cfg(struct wlan_dp_prealloc_cfg *cfg) {}
+#endif
+
 QDF_STATUS dp_prealloc_init(struct cdp_ctrl_objmgr_psoc *ctrl_psoc)
 {
 	int i;
@@ -705,6 +759,7 @@ QDF_STATUS dp_prealloc_init(struct cdp_ctrl_objmgr_psoc *ctrl_psoc)
 	}
 
 	wlan_cfg_get_prealloc_cfg(ctrl_psoc, &cfg);
+	wlan_dp_sync_prealloc_with_profile_cfg(&cfg);
 
 	/*Context pre-alloc*/
 	for (i = 0; i < QDF_ARRAY_SIZE(g_dp_context_allocs); i++) {

components/dp/dispatcher/src/wlan_dp_ucfg_api.c

@@ -2328,6 +2328,7 @@ end:
 
 QDF_STATUS ucfg_dp_prealloc_init(struct cdp_ctrl_objmgr_psoc *ctrl_psoc)
 {
+	wlan_dp_select_profile_cfg((struct wlan_objmgr_psoc *)ctrl_psoc);
 	return dp_prealloc_init(ctrl_psoc);
 }