Video Driver: fix frame freeze for HEVC 10bit all intra decoding

1. Allow turbo for HEVC 10bit all intra decoding;
2. Add 25 percent extra to VSP cycle for HEVC
   10bit all intra decoding;

Change-Id: I794b2a896f7e9444c8979abdb15b8e673a5270ee
Signed-off-by: Zhongbo Shi <quic_zhongbos@quicinc.com>
Signed-off-by: Ankush Mitra <quic_ankumitr@quicinc.com>
这个提交包含在:
Ankush Mitra
2022-09-01 14:13:46 +08:00
提交者 Gerrit - the friendly Code Review server
父节点 dc39a04e6e
当前提交 b35fde25c4
修改 7 个文件,包含 48 行新增7 行删除

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@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "msm_vidc_power_iris3.h"
@@ -213,6 +213,11 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
if (fps >= 960)
vsp_cycles += div_u64(vpp_cycles * 25, 100);
/* Add 25 percent extra for HEVC 10bit all intra use case */
if (inst->iframe && is_hevc_10bit_decode_session(inst)) {
vsp_cycles += div_u64(vsp_cycles * 25, 100);
}
if (inst->codec == MSM_VIDC_VP9 &&
inst->capabilities->cap[STAGE].value ==
MSM_VIDC_STAGE_2 &&
@@ -228,11 +233,14 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
freq = max(vpp_cycles, vsp_cycles);
freq = max(freq, fw_cycles);
if (inst->codec != MSM_VIDC_AV1) {
if (inst->codec == MSM_VIDC_AV1 ||
(inst->iframe && is_hevc_10bit_decode_session(inst))) {
/*
* for non-AV1 codecs limit the frequency to NOM only
* index 0 is TURBO, index 1 is NOM clock rate
* for AV1 or HEVC 10bit and iframe case only allow TURBO and
* limit to NOM for all other cases
*/
} else {
/* limit to NOM, index 0 is TURBO, index 1 is NOM clock rate */
if (core->resource->freq_set.count >= 2 &&
freq > core->resource->freq_set.freq_tbl[1].freq)
freq = core->resource->freq_set.freq_tbl[1].freq;

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@@ -212,6 +212,11 @@ u64 msm_vidc_calc_freq_iris33(struct msm_vidc_inst *inst, u32 data_size)
if (fps >= 960)
vsp_cycles += div_u64(vpp_cycles * 25, 100);
/* Add 25 percent extra for HEVC 10bit all intra use case */
if (inst->iframe && is_hevc_10bit_decode_session(inst)) {
vsp_cycles += div_u64(vsp_cycles * 25, 100);
}
if (inst->codec == MSM_VIDC_VP9 &&
inst->capabilities->cap[STAGE].value ==
MSM_VIDC_STAGE_2 &&
@@ -227,11 +232,14 @@ u64 msm_vidc_calc_freq_iris33(struct msm_vidc_inst *inst, u32 data_size)
freq = max(vpp_cycles, vsp_cycles);
freq = max(freq, fw_cycles);
if (inst->codec != MSM_VIDC_AV1) {
if (inst->codec == MSM_VIDC_AV1 ||
(inst->iframe && is_hevc_10bit_decode_session(inst))) {
/*
* for non-AV1 codecs limit the frequency to NOM only
* index 0 is TURBO, index 1 is NOM clock rate
* for AV1 or HEVC 10bit and iframe case only allow TURBO and
* limit to NOM for all other cases
*/
} else {
/* limit to NOM, index 0 is TURBO, index 1 is NOM clock rate */
if (core->resource->freq_set.count >= 2 &&
freq > core->resource->freq_set.freq_tbl[1].freq)
freq = core->resource->freq_set.freq_tbl[1].freq;