qcacmn: Fixes for IPA datapath
1. Disable host processing of REO2SW4 when IPA is enabled. 2. Change buffer memory location provide to IPA TX transfer ring from consistent to non-consistent memory. Change-Id: Ibb62d9faf5dc9adb5ee8a2e113d10a2912269cbd CRs-Fixed: 2315889
This commit is contained in:
@@ -45,37 +45,19 @@
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static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
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static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
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{
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{
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int idx;
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int idx;
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uint32_t ring_base_align = 8;
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/*
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* Uncomment when dp_ops_cfg.cfg_attach is implemented
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* unsigned int uc_tx_buf_sz =
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* dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
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*/
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unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
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unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
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for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
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for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
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if (soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx]) {
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if (soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx]) {
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qdf_mem_free_consistent(
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qdf_nbuf_free((qdf_nbuf_t)
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soc->osdev, soc->osdev->dev,
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(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx]));
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alloc_size,
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soc->ipa_uc_tx_rsc.
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tx_buf_pool_vaddr_unaligned[idx],
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soc->ipa_uc_tx_rsc.
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tx_buf_pool_paddr_unaligned[idx],
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0);
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soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx] =
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soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx] =
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(void *)NULL;
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(void *)NULL;
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soc->ipa_uc_tx_rsc.tx_buf_pool_paddr_unaligned[idx] =
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(qdf_dma_addr_t)NULL;
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}
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}
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}
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}
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qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
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qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
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soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
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soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
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qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_paddr_unaligned);
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soc->ipa_uc_tx_rsc.tx_buf_pool_paddr_unaligned = NULL;
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}
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}
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/**
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/**
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@@ -117,9 +99,6 @@ static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
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{
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{
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uint32_t tx_buffer_count;
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uint32_t tx_buffer_count;
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uint32_t ring_base_align = 8;
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uint32_t ring_base_align = 8;
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void *buffer_vaddr_unaligned;
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void *buffer_vaddr;
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qdf_dma_addr_t buffer_paddr_unaligned;
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qdf_dma_addr_t buffer_paddr;
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qdf_dma_addr_t buffer_paddr;
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struct hal_srng *wbm_srng =
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struct hal_srng *wbm_srng =
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soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
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soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
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@@ -128,6 +107,7 @@ static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
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uint32_t paddr_hi;
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uint32_t paddr_hi;
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void *ring_entry;
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void *ring_entry;
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int num_entries;
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int num_entries;
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qdf_nbuf_t nbuf;
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int retval = QDF_STATUS_SUCCESS;
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int retval = QDF_STATUS_SUCCESS;
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/*
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/*
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* Uncomment when dp_ops_cfg.cfg_attach is implemented
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* Uncomment when dp_ops_cfg.cfg_attach is implemented
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@@ -154,17 +134,6 @@ static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
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return -ENOMEM;
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return -ENOMEM;
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}
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}
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soc->ipa_uc_tx_rsc.tx_buf_pool_paddr_unaligned =
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qdf_mem_malloc(num_entries *
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sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_paddr_unaligned));
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if (!soc->ipa_uc_tx_rsc.tx_buf_pool_paddr_unaligned) {
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QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
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"%s: IPA WBM Ring Tx buf pool paddr alloc fail",
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__func__);
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qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
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return -ENOMEM;
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}
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hal_srng_access_start(soc->hal_soc, (void *)wbm_srng);
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hal_srng_access_start(soc->hal_soc, (void *)wbm_srng);
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/*
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/*
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@@ -175,9 +144,8 @@ static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
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*/
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*/
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for (tx_buffer_count = 0;
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for (tx_buffer_count = 0;
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tx_buffer_count < num_entries - 1; tx_buffer_count++) {
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tx_buffer_count < num_entries - 1; tx_buffer_count++) {
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buffer_vaddr_unaligned = qdf_mem_alloc_consistent(soc->osdev,
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nbuf = qdf_nbuf_alloc(soc->osdev, alloc_size, 0, 256, FALSE);
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soc->osdev->dev, alloc_size, &buffer_paddr_unaligned);
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if (!nbuf)
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if (!buffer_vaddr_unaligned)
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break;
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break;
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ring_entry = hal_srng_dst_get_next_hp(soc->hal_soc,
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ring_entry = hal_srng_dst_get_next_hp(soc->hal_soc,
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@@ -186,27 +154,23 @@ static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
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QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
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QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
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"%s: Failed to get WBM ring entry",
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"%s: Failed to get WBM ring entry",
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__func__);
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__func__);
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qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
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qdf_nbuf_free(nbuf);
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alloc_size, buffer_vaddr_unaligned,
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buffer_paddr_unaligned, 0);
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break;
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break;
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}
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}
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buffer_vaddr = (void *)qdf_align((unsigned long)
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qdf_nbuf_map_single(soc->osdev, nbuf,
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buffer_vaddr_unaligned, ring_base_align);
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QDF_DMA_BIDIRECTIONAL);
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buffer_paddr = buffer_paddr_unaligned +
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buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
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((unsigned long)(buffer_vaddr) -
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(unsigned long)buffer_vaddr_unaligned);
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paddr_lo = ((u64)buffer_paddr & 0x00000000ffffffff);
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paddr_lo = ((u64)buffer_paddr & 0x00000000ffffffff);
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paddr_hi = ((u64)buffer_paddr & 0x0000001f00000000) >> 32;
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paddr_hi = ((u64)buffer_paddr & 0x0000001f00000000) >> 32;
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HAL_WBM_PADDR_LO_SET(ring_entry, paddr_lo);
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HAL_RXDMA_PADDR_LO_SET(ring_entry, paddr_lo);
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HAL_WBM_PADDR_HI_SET(ring_entry, paddr_hi);
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HAL_RXDMA_PADDR_HI_SET(ring_entry, paddr_hi);
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HAL_RXDMA_MANAGER_SET(ring_entry, (IPA_TCL_DATA_RING_IDX +
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HAL_WBM_SW0_BM_ID));
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soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[tx_buffer_count]
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soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[tx_buffer_count]
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= buffer_vaddr_unaligned;
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= (void *)nbuf;
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soc->ipa_uc_tx_rsc.tx_buf_pool_paddr_unaligned[tx_buffer_count]
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= buffer_paddr_unaligned;
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}
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}
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hal_srng_access_end(soc->hal_soc, wbm_srng);
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hal_srng_access_end(soc->hal_soc, wbm_srng);
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@@ -223,8 +187,6 @@ static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
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__func__);
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__func__);
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qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
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qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
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soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
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soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
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qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_paddr_unaligned);
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soc->ipa_uc_tx_rsc.tx_buf_pool_paddr_unaligned = NULL;
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retval = -ENOMEM;
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retval = -ENOMEM;
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}
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}
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@@ -195,26 +195,6 @@ enum hal_rx_ret_buf_manager {
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(cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \
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(cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \
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BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK)
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BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK)
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/*
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* macro to set the LSW of the nbuf data physical address
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* to the WBM ring entry
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*/
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#define HAL_WBM_PADDR_LO_SET(buff_addr_info, paddr_lo) \
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((*(((unsigned int *) buff_addr_info) + \
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(BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \
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(paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \
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BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK)
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/*
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* macro to set the LSB of MSW of the nbuf data physical address
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* to the WBM ring entry
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*/
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#define HAL_WBM_PADDR_HI_SET(buff_addr_info, paddr_hi) \
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((*(((unsigned int *) buff_addr_info) + \
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(BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \
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(paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \
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BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK)
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/*
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/*
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* macro to set the manager into the rxdma ring entry
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* macro to set the manager into the rxdma ring entry
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*/
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*/
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@@ -90,6 +90,7 @@ static const int tx_ring_mask[WLAN_CFG_INT_NUM_CONTEXTS] = {
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0,
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0,
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0};
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0};
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#ifndef IPA_OFFLOAD
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static const int rx_ring_mask[WLAN_CFG_INT_NUM_CONTEXTS] = {
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static const int rx_ring_mask[WLAN_CFG_INT_NUM_CONTEXTS] = {
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0,
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0,
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0,
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0,
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@@ -98,6 +99,16 @@ static const int rx_ring_mask[WLAN_CFG_INT_NUM_CONTEXTS] = {
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WLAN_CFG_RX_RING_MASK_1,
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WLAN_CFG_RX_RING_MASK_1,
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WLAN_CFG_RX_RING_MASK_2,
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WLAN_CFG_RX_RING_MASK_2,
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WLAN_CFG_RX_RING_MASK_3};
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WLAN_CFG_RX_RING_MASK_3};
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#else
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static const int rx_ring_mask[WLAN_CFG_INT_NUM_CONTEXTS] = {
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0,
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0,
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WLAN_CFG_RX_RING_MASK_0,
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0,
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WLAN_CFG_RX_RING_MASK_1,
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WLAN_CFG_RX_RING_MASK_2,
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0};
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#endif
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static const int rx_mon_ring_mask[WLAN_CFG_INT_NUM_CONTEXTS] = {
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static const int rx_mon_ring_mask[WLAN_CFG_INT_NUM_CONTEXTS] = {
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0,
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0,
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