diff --git a/hw/qca6290/v1/HALcomdef.h b/hw/qca6290/v1/HALcomdef.h index cc351b1261..12204c46a7 100644 --- a/hw/qca6290/v1/HALcomdef.h +++ b/hw/qca6290/v1/HALcomdef.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -29,7 +29,7 @@ DESCRIPTION: Edit History -$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/HALcomdef.h,v 1.1.1.1 2012/09/19 22:33:29 rjindal Exp $ +$Header: //depot/prj/qca/lithium/wcss/verif/native/register/include/HALcomdef.h#6 $ when who what, where, why -------- --- ----------------------------------------------------------- diff --git a/hw/qca6290/v1/HALhwio.h b/hw/qca6290/v1/HALhwio.h index 4e51df0143..745ca3fb07 100644 --- a/hw/qca6290/v1/HALhwio.h +++ b/hw/qca6290/v1/HALhwio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/buffer_addr_info.h b/hw/qca6290/v1/buffer_addr_info.h index 433fc6b2be..f48f8c8815 100644 --- a/hw/qca6290/v1/buffer_addr_info.h +++ b/hw/qca6290/v1/buffer_addr_info.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/ce_src_desc.h b/hw/qca6290/v1/ce_src_desc.h index 8dd6bc39c9..c9295ed832 100644 --- a/hw/qca6290/v1/ce_src_desc.h +++ b/hw/qca6290/v1/ce_src_desc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/ce_stat_desc.h b/hw/qca6290/v1/ce_stat_desc.h index 4667d14475..a811644b49 100644 --- a/hw/qca6290/v1/ce_stat_desc.h +++ b/hw/qca6290/v1/ce_stat_desc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/com_dtypes.h b/hw/qca6290/v1/com_dtypes.h index a1c0edccc5..fedb0076c1 100644 --- a/hw/qca6290/v1/com_dtypes.h +++ b/hw/qca6290/v1/com_dtypes.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -50,7 +50,6 @@ DESCRIPTION T_WINNT Software is hosted on an NT platforn, triggers macro and type definitions, unlike definition above which triggers actual OS calls - ===========================================================================*/ @@ -61,7 +60,7 @@ DESCRIPTION This section contains comments describing changes made to this file. Notice that changes are listed in reverse chronological order. -$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/com_dtypes.h,v 1.1.1.1 2012/09/19 22:33:30 rjindal Exp $ +$Header: //depot/prj/qca/lithium/wcss/verif/native/register/include/com_dtypes.h#5 $ when who what, where, why -------- --- ---------------------------------------------------------- diff --git a/hw/qca6290/v1/lithium_top_reg.h b/hw/qca6290/v1/lithium_top_reg.h index 87e1b3d251..47c9bd57c9 100644 --- a/hw/qca6290/v1/lithium_top_reg.h +++ b/hw/qca6290/v1/lithium_top_reg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -32,7 +32,7 @@ #ifndef LITHIUM_TOP_REG_H #define LITHIUM_TOP_REG_H -#define UMAC_CE_COMMON_CE_HOST_IE_0 (0x00A18034) -#define UMAC_CE_COMMON_CE_HOST_IE_1 (0x00A18038) - +#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x00A18034) +#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x00A18038) +////////////////////////////////////////////////////////////////////////// END #endif diff --git a/hw/qca6290/v1/mac_tcl_reg_seq_hwiobase.h b/hw/qca6290/v1/mac_tcl_reg_seq_hwiobase.h index a845897e89..536cfa1218 100644 --- a/hw/qca6290/v1/mac_tcl_reg_seq_hwiobase.h +++ b/hw/qca6290/v1/mac_tcl_reg_seq_hwiobase.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -18,8 +18,8 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 -// User Name:pgohil +// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq 3.1 9/30/2016 +// User Name:kanalas // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. // diff --git a/hw/qca6290/v1/mac_tcl_reg_seq_hwioreg.h b/hw/qca6290/v1/mac_tcl_reg_seq_hwioreg.h index 73f4cc2b36..ad0adfcefa 100644 --- a/hw/qca6290/v1/mac_tcl_reg_seq_hwioreg.h +++ b/hw/qca6290/v1/mac_tcl_reg_seq_hwioreg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -18,8 +18,8 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 -// User Name:pgohil +// mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 9/30/2016 +// User Name:kanalas // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. // @@ -45,8 +45,8 @@ #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) (x+0x00000000) #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) (x+0x00000000) -#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0007ffe1 -#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 5 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask) \ @@ -60,24 +60,18 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 -#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 - #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 -#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_BMSK 0x00000001 -#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_SHFT 0x0 - //// Register TCL_R0_SW2TCL2_RING_CTRL //// #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) (x+0x00000004) #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) (x+0x00000004) -#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0007ffe1 -#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 5 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask) \ @@ -91,24 +85,18 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 -#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 - #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x00000020 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 0x5 -#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_BMSK 0x00000001 -#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_SHFT 0x0 - //// Register TCL_R0_SW2TCL3_RING_CTRL //// #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) (x+0x00000008) #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) (x+0x00000008) -#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0007ffe1 -#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 5 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask) \ @@ -122,24 +110,18 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 -#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 - #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x00000020 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 0x5 -#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_BMSK 0x00000001 -#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_SHFT 0x0 - //// Register TCL_R0_FW2TCL1_RING_CTRL //// #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) (x+0x0000000c) #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) (x+0x0000000c) -#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0007ffe1 -#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 5 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask) \ @@ -153,24 +135,18 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 -#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 - #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 -#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_BMSK 0x00000001 -#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_SHFT 0x0 - //// Register TCL_R0_SW2TCL_CMD_RING_CTRL //// #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x) (x+0x00000010) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_PHYS(x) (x+0x00000010) -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK 0x0007ffe1 -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_SHFT 5 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_INM(x, mask) \ @@ -184,23 +160,17 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 - #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_BMSK 0x00000020 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_SHFT 0x5 -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_BMSK 0x00000001 -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_SHFT 0x0 - //// Register TCL_R0_CONS_RING_CMN_CTRL_REG //// #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) (x+0x00000014) #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) (x+0x00000014) -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x00000007 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x00001fff #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT 0 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK) @@ -215,6 +185,36 @@ HWIO_INTFREE();\ } while (0) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_STAT_BMSK 0x00001000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_STAT_SHFT 0xc + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_BMSK 0x00000800 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_SHFT 0xb + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_BMSK 0x00000400 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_SHFT 0xa + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_BMSK 0x00000200 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_SHFT 0x9 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_BMSK 0x00000100 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_SHFT 0x8 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_BMSK 0x00000080 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_SHFT 0x7 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_BMSK 0x00000040 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_SHFT 0x6 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_BMSK 0x00000020 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_SHFT 0x5 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_BMSK 0x00000010 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_SHFT 0x4 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_BMSK 0x00000008 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_SHFT 0x3 + #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x00000004 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 0x2 @@ -316,7 +316,7 @@ #define HWIO_TCL_R0_GEN_CTRL_ADDR(x) (x+0x00000028) #define HWIO_TCL_R0_GEN_CTRL_PHYS(x) (x+0x00000028) -#define HWIO_TCL_R0_GEN_CTRL_RMSK 0xffff7e1d +#define HWIO_TCL_R0_GEN_CTRL_RMSK 0xffff7ffd #define HWIO_TCL_R0_GEN_CTRL_SHFT 0 #define HWIO_TCL_R0_GEN_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK) @@ -346,6 +346,18 @@ #define HWIO_TCL_R0_GEN_CTRL_MAC_ID_BMSK 0x00000e00 #define HWIO_TCL_R0_GEN_CTRL_MAC_ID_SHFT 0x9 +#define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_BMSK 0x00000100 +#define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_SHFT 0x8 + +#define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_BMSK 0x00000080 +#define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_SHFT 0x7 + +#define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_BMSK 0x00000040 +#define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_SHFT 0x6 + +#define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_BMSK 0x00000020 +#define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_SHFT 0x5 + #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x00000010 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 0x4 @@ -1635,7 +1647,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x000000cc) #define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x000000cc) -#define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK) @@ -1650,9 +1662,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL1_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_TCL_R0_SW2TCL1_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -1844,7 +1853,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000100) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000100) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -1859,7 +1868,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// @@ -1982,7 +1991,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000118) #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000118) -#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) @@ -1997,7 +2006,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_SW2TCL2_RING_BASE_LSB //// @@ -2051,7 +2060,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x00000124) #define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x00000124) -#define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK) @@ -2066,9 +2075,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL2_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_TCL_R0_SW2TCL2_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2260,7 +2266,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000158) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000158) -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -2275,7 +2281,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER //// @@ -2398,7 +2404,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000170) #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000170) -#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK) @@ -2413,7 +2419,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_SW2TCL3_RING_BASE_LSB //// @@ -2467,7 +2473,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x0000017c) #define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x0000017c) -#define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK) @@ -2482,9 +2488,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL3_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_TCL_R0_SW2TCL3_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2676,7 +2679,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001b0) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001b0) -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -2691,7 +2694,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER //// @@ -2814,7 +2817,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001c8) #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001c8) -#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK) @@ -2829,7 +2832,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_SW2TCL_CMD_RING_BASE_LSB //// @@ -2883,7 +2886,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x) (x+0x000001d4) #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_PHYS(x) (x+0x000001d4) -#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK) @@ -2898,9 +2901,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -3092,7 +3092,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000208) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000208) -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -3107,7 +3107,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER //// @@ -3230,7 +3230,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000220) #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000220) -#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK) @@ -3245,7 +3245,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_FW2TCL1_RING_BASE_LSB //// @@ -3299,7 +3299,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x0000022c) #define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x0000022c) -#define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK) @@ -3314,9 +3314,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_FW2TCL1_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_TCL_R0_FW2TCL1_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -3508,7 +3505,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000260) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000260) -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -3523,7 +3520,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// @@ -3646,7 +3643,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000278) #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000278) -#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) @@ -3661,7 +3658,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_TCL2TQM_RING_BASE_LSB //// @@ -3902,7 +3899,7 @@ #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002a8) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002a8) -#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -3917,14 +3914,14 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET //// #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002d0) #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002d0) -#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK) @@ -3939,7 +3936,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB //// @@ -4180,7 +4177,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000300) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000300) -#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -4195,7 +4192,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB //// @@ -4271,7 +4268,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000328) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000328) -#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK) @@ -4286,7 +4283,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB //// @@ -4527,7 +4524,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000358) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000358) -#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -4542,7 +4539,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB //// @@ -4618,7 +4615,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000380) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000380) -#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK) @@ -4633,7 +4630,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_TCL2FW_RING_BASE_LSB //// @@ -4874,7 +4871,7 @@ #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003b0) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003b0) -#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -4889,14 +4886,14 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET //// #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003d8) #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003d8) -#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK) @@ -4911,7 +4908,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_GXI_TESTBUS_LOWER //// diff --git a/hw/qca6290/v1/msmhwio.h b/hw/qca6290/v1/msmhwio.h index 23223cfdc9..9825c9672f 100644 --- a/hw/qca6290/v1/msmhwio.h +++ b/hw/qca6290/v1/msmhwio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/reo_destination_ring.h b/hw/qca6290/v1/reo_destination_ring.h index fd6900d858..1e7121cf26 100644 --- a/hw/qca6290/v1/reo_destination_ring.h +++ b/hw/qca6290/v1/reo_destination_ring.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/reo_entrance_ring.h b/hw/qca6290/v1/reo_entrance_ring.h index 8b3f4e9fcc..692ea3d31c 100644 --- a/hw/qca6290/v1/reo_entrance_ring.h +++ b/hw/qca6290/v1/reo_entrance_ring.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -269,7 +269,8 @@ rxdma_error_code CRYPTO reported a decryption - error + error or CRYPTO received an encrypted frame, but did not get + a valid corresponding key id in the peer entry. CRYPTO reported a TKIP MIC error @@ -604,7 +605,8 @@ looping_count CRYPTO reported a decryption - error + error or CRYPTO received an encrypted frame, but did not get + a valid corresponding key id in the peer entry. CRYPTO reported a TKIP MIC error diff --git a/hw/qca6290/v1/reo_get_queue_stats.h b/hw/qca6290/v1/reo_get_queue_stats.h index 6cc4b0728e..cf1e23c791 100644 --- a/hw/qca6290/v1/reo_get_queue_stats.h +++ b/hw/qca6290/v1/reo_get_queue_stats.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/reo_get_queue_stats_status.h b/hw/qca6290/v1/reo_get_queue_stats_status.h index cf89d0d4d6..3e15f56c0a 100644 --- a/hw/qca6290/v1/reo_get_queue_stats_status.h +++ b/hw/qca6290/v1/reo_get_queue_stats_status.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/reo_reg_seq_hwiobase.h b/hw/qca6290/v1/reo_reg_seq_hwiobase.h index 2120cf611a..c1acb9f53e 100644 --- a/hw/qca6290/v1/reo_reg_seq_hwiobase.h +++ b/hw/qca6290/v1/reo_reg_seq_hwiobase.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -18,8 +18,8 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// reo_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 -// User Name:pgohil +// reo_reg_seq_hwiobase.h : automatically generated by Autoseq 3.1 9/30/2016 +// User Name:kanalas // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. // diff --git a/hw/qca6290/v1/reo_reg_seq_hwioreg.h b/hw/qca6290/v1/reo_reg_seq_hwioreg.h index 263123e3a5..39cf6929eb 100644 --- a/hw/qca6290/v1/reo_reg_seq_hwioreg.h +++ b/hw/qca6290/v1/reo_reg_seq_hwioreg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -18,8 +18,8 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 -// User Name:pgohil +// reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 9/30/2016 +// User Name:kanalas // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. // @@ -651,7 +651,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x) (x+0x0000003c) #define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x) (x+0x0000003c) -#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO0_RING_ID_SHFT 0 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK) @@ -666,9 +666,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -860,7 +857,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000070) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000070) -#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -875,7 +872,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER //// @@ -998,7 +995,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000088) #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000088) -#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK) @@ -1013,7 +1010,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_RXDMA2REO1_RING_BASE_LSB //// @@ -1067,7 +1064,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x) (x+0x00000094) #define HWIO_REO_R0_RXDMA2REO1_RING_ID_PHYS(x) (x+0x00000094) -#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO1_RING_ID_SHFT 0 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK) @@ -1082,9 +1079,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -1276,7 +1270,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000000c8) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000000c8) -#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -1291,7 +1285,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER //// @@ -1414,7 +1408,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000e0) #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000e0) -#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK) @@ -1429,7 +1423,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_RXDMA2REO2_RING_BASE_LSB //// @@ -1483,7 +1477,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x) (x+0x000000ec) #define HWIO_REO_R0_RXDMA2REO2_RING_ID_PHYS(x) (x+0x000000ec) -#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO2_RING_ID_SHFT 0 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK) @@ -1498,9 +1492,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -1692,7 +1683,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000120) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000120) -#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -1707,7 +1698,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER //// @@ -1830,7 +1821,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000138) #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000138) -#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK) @@ -1845,7 +1836,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_WBM2REO_LINK_RING_BASE_LSB //// @@ -1899,7 +1890,7 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x00000144) #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x00000144) -#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0x000000ff #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_SHFT 0 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK) @@ -1914,9 +1905,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2108,7 +2096,7 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178) -#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -2123,7 +2111,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER //// @@ -2177,7 +2165,7 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000190) #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000190) -#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) @@ -2192,7 +2180,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO_CMD_RING_BASE_LSB //// @@ -2246,7 +2234,7 @@ #define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) (x+0x0000019c) #define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) (x+0x0000019c) -#define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0x000000ff #define HWIO_REO_R0_REO_CMD_RING_ID_SHFT 0 #define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), HWIO_REO_R0_REO_CMD_RING_ID_RMSK) @@ -2261,9 +2249,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO_CMD_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_REO_R0_REO_CMD_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2455,7 +2440,7 @@ #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001d0) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001d0) -#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -2470,7 +2455,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER //// @@ -2593,7 +2578,7 @@ #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001e8) #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001e8) -#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK) @@ -2608,7 +2593,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_SW2REO_RING_BASE_LSB //// @@ -2662,7 +2647,7 @@ #define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) (x+0x000001f4) #define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) (x+0x000001f4) -#define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0x000000ff #define HWIO_REO_R0_SW2REO_RING_ID_SHFT 0 #define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO_RING_ID_RMSK) @@ -2677,9 +2662,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_SW2REO_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_REO_R0_SW2REO_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2871,7 +2853,7 @@ #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000228) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000228) -#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -2886,7 +2868,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER //// @@ -3009,7 +2991,7 @@ #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000240) #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000240) -#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK) @@ -3024,7 +3006,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO2SW1_RING_BASE_LSB //// @@ -3265,7 +3247,7 @@ #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000270) #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000270) -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -3280,7 +3262,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO2SW1_RING_MSI1_BASE_LSB //// @@ -3356,7 +3338,7 @@ #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000298) #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000298) -#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK) @@ -3371,7 +3353,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO2SW2_RING_BASE_LSB //// @@ -3612,7 +3594,7 @@ #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002c8) #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002c8) -#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -3627,7 +3609,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO2SW2_RING_MSI1_BASE_LSB //// @@ -3703,7 +3685,7 @@ #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002f0) #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002f0) -#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK) @@ -3718,7 +3700,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO2SW3_RING_BASE_LSB //// @@ -3959,7 +3941,7 @@ #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000320) #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000320) -#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -3974,7 +3956,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO2SW3_RING_MSI1_BASE_LSB //// @@ -4050,7 +4032,7 @@ #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000348) #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000348) -#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK) @@ -4065,7 +4047,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO2SW4_RING_BASE_LSB //// @@ -4306,7 +4288,7 @@ #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000378) #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000378) -#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -4321,7 +4303,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO2SW4_RING_MSI1_BASE_LSB //// @@ -4397,7 +4379,7 @@ #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003a0) #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003a0) -#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK) @@ -4412,7 +4394,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO2TCL_RING_BASE_LSB //// @@ -4653,7 +4635,7 @@ #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003d0) #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003d0) -#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -4668,7 +4650,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO2TCL_RING_MSI1_BASE_LSB //// @@ -4744,7 +4726,7 @@ #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003f8) #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003f8) -#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK) @@ -4759,7 +4741,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO2FW_RING_BASE_LSB //// @@ -5000,7 +4982,7 @@ #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000428) #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000428) -#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -5015,7 +4997,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO2FW_RING_MSI1_BASE_LSB //// @@ -5091,7 +5073,7 @@ #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000450) #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000450) -#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK) @@ -5106,7 +5088,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO_RELEASE_RING_BASE_LSB //// @@ -5347,7 +5329,7 @@ #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000480) #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000480) -#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -5362,14 +5344,14 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET //// #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004a8) #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004a8) -#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) @@ -5384,7 +5366,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO_STATUS_RING_BASE_LSB //// @@ -5625,7 +5607,7 @@ #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004d8) #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004d8) -#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -5640,7 +5622,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO_STATUS_RING_MSI1_BASE_LSB //// @@ -5716,7 +5698,7 @@ #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000500) #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000500) -#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK) @@ -5731,14 +5713,14 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_WATCHDOG_TIMEOUT //// #define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x00000504) #define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x00000504) -#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0x0fff0fff +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0x00000fff #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SHFT 0 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x) \ in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK) @@ -5753,9 +5735,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_REO_R0_WATCHDOG_TIMEOUT_GXI_TIMEOUT_BMSK 0x0fff0000 -#define HWIO_REO_R0_WATCHDOG_TIMEOUT_GXI_TIMEOUT_SHFT 0x10 - #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_BMSK 0x00000fff #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_SHFT 0x0 diff --git a/hw/qca6290/v1/rx_attention.h b/hw/qca6290/v1/rx_attention.h index bc5f09901a..938f3752e3 100644 --- a/hw/qca6290/v1/rx_attention.h +++ b/hw/qca6290/v1/rx_attention.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -411,6 +411,8 @@ tkip_mic_err decrypt_err Indicates that the MPDU decrypt integrity check failed + or CRYPTO received an encrypted frame, but did not get a + valid corresponding key id in the peer entry. unencrypted_frame_err @@ -979,6 +981,8 @@ msdu_done /* Description RX_ATTENTION_1_DECRYPT_ERR Indicates that the MPDU decrypt integrity check failed + or CRYPTO received an encrypted frame, but did not get a + valid corresponding key id in the peer entry. */ #define RX_ATTENTION_1_DECRYPT_ERR_OFFSET 0x00000004 #define RX_ATTENTION_1_DECRYPT_ERR_LSB 29 diff --git a/hw/qca6290/v1/rx_mpdu_desc_info.h b/hw/qca6290/v1/rx_mpdu_desc_info.h index bb9cfdeee1..09c2c139be 100644 --- a/hw/qca6290/v1/rx_mpdu_desc_info.h +++ b/hw/qca6290/v1/rx_mpdu_desc_info.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/rx_mpdu_details.h b/hw/qca6290/v1/rx_mpdu_details.h index 279420a43f..bb87511d2d 100644 --- a/hw/qca6290/v1/rx_mpdu_details.h +++ b/hw/qca6290/v1/rx_mpdu_details.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/rx_mpdu_end.h b/hw/qca6290/v1/rx_mpdu_end.h index 924c06be26..a3eb9543fb 100644 --- a/hw/qca6290/v1/rx_mpdu_end.h +++ b/hw/qca6290/v1/rx_mpdu_end.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -239,7 +239,8 @@ tkip_mic_err decrypt_err Set by RX CRYPTO when CRYPTO detected a decrypt error - for this MPDU. + for this MPDU or CRYPTO received an encrypted frame, but did + not get a valid corresponding key id in the peer entry. unencrypted_frame_err @@ -583,7 +584,8 @@ reserved_1b /* Description RX_MPDU_END_1_DECRYPT_ERR Set by RX CRYPTO when CRYPTO detected a decrypt error - for this MPDU. + for this MPDU or CRYPTO received an encrypted frame, but did + not get a valid corresponding key id in the peer entry. */ #define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004 #define RX_MPDU_END_1_DECRYPT_ERR_LSB 16 diff --git a/hw/qca6290/v1/rx_mpdu_info.h b/hw/qca6290/v1/rx_mpdu_info.h index de155604a2..739132670e 100644 --- a/hw/qca6290/v1/rx_mpdu_info.h +++ b/hw/qca6290/v1/rx_mpdu_info.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -833,6 +833,9 @@ pre_delim_err_warning + In case of ndp or phy_err, this field will indicate at + least one of delimiters located after the last MPDU in the + previous PPDU has been corrupted. first_delim_err @@ -972,7 +975,28 @@ pre_delim_count - In case of ndp or phy_err, this field will be set to 0 + Note that this number is cleared at PPDU start. + + + + If this MPDU is the first received MPDU in the PPDU and + this MPDU gets filtered-in, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + + + + If this MPDU is located after the first received MPDU in + an PPDU, this field will indicate the number of delimiters + located between the previous MPDU and this MPDU. + + + + In case of ndp or phy_err, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + + ampdu_flag @@ -2180,6 +2204,9 @@ mpdu_ht_control_field + In case of ndp or phy_err, this field will indicate at + least one of delimiters located after the last MPDU in the + previous PPDU has been corrupted. */ #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_OFFSET 0x0000002c #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_LSB 24 @@ -2363,7 +2390,28 @@ mpdu_ht_control_field - In case of ndp or phy_err, this field will be set to 0 + Note that this number is cleared at PPDU start. + + + + If this MPDU is the first received MPDU in the PPDU and + this MPDU gets filtered-in, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + + + + If this MPDU is located after the first received MPDU in + an PPDU, this field will indicate the number of delimiters + located between the previous MPDU and this MPDU. + + + + In case of ndp or phy_err, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + + */ #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 diff --git a/hw/qca6290/v1/rx_mpdu_link_ptr.h b/hw/qca6290/v1/rx_mpdu_link_ptr.h index afd9d7bfeb..5a3de783f2 100644 --- a/hw/qca6290/v1/rx_mpdu_link_ptr.h +++ b/hw/qca6290/v1/rx_mpdu_link_ptr.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/rx_mpdu_start.h b/hw/qca6290/v1/rx_mpdu_start.h index be5ddfcdc4..f9a2ff65cf 100644 --- a/hw/qca6290/v1/rx_mpdu_start.h +++ b/hw/qca6290/v1/rx_mpdu_start.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/rx_msdu_desc_info.h b/hw/qca6290/v1/rx_msdu_desc_info.h index 1a05ac150c..94faae151c 100644 --- a/hw/qca6290/v1/rx_msdu_desc_info.h +++ b/hw/qca6290/v1/rx_msdu_desc_info.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/rx_msdu_details.h b/hw/qca6290/v1/rx_msdu_details.h index 02e52e2d4e..b1eccc5203 100644 --- a/hw/qca6290/v1/rx_msdu_details.h +++ b/hw/qca6290/v1/rx_msdu_details.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/rx_msdu_end.h b/hw/qca6290/v1/rx_msdu_end.h index 6a148102f5..dcc7e8a14d 100644 --- a/hw/qca6290/v1/rx_msdu_end.h +++ b/hw/qca6290/v1/rx_msdu_end.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -36,11 +36,11 @@ // 2 key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], ext_wapi_pn_63_48[31:16] // 3 ext_wapi_pn_95_64[31:0] // 4 ext_wapi_pn_127_96[31:0] -// 5 reported_mpdu_length[13:0], first_msdu[14], last_msdu[15], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], reserved_5a[31:26] +// 5 reported_mpdu_length[13:0], first_msdu[14], last_msdu[15], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], l3_header_padding[27:26], reserved_5a[31:28] // 6 ipv6_options_crc[31:0] // 7 tcp_seq_number[31:0] // 8 tcp_ack_number[31:0] -// 9 tcp_flag[8:0], lro_eligible[9], l3_header_padding[12:10], reserved_9a[15:13], window_size[31:16] +// 9 tcp_flag[8:0], lro_eligible[9], reserved_9a[15:10], window_size[31:16] // 10 da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], type_offset[20:14], reserved_10a[31:21] // 11 rule_indication_31_0[31:0] // 12 rule_indication_63_32[31:0] @@ -80,14 +80,14 @@ struct rx_msdu_end { sa_is_valid : 1, //[23] da_is_valid : 1, //[24] da_is_mcbc : 1, //[25] - reserved_5a : 6; //[31:26] + l3_header_padding : 2, //[27:26] + reserved_5a : 4; //[31:28] uint32_t ipv6_options_crc : 32; //[31:0] uint32_t tcp_seq_number : 32; //[31:0] uint32_t tcp_ack_number : 32; //[31:0] uint32_t tcp_flag : 9, //[8:0] lro_eligible : 1, //[9] - l3_header_padding : 3, //[12:10] - reserved_9a : 3, //[15:13] + reserved_9a : 6, //[15:10] window_size : 16; //[31:16] uint32_t da_offset : 6, //[5:0] sa_offset : 6, //[11:6] @@ -368,6 +368,11 @@ da_is_mcbc Indicates the DA address was a Multicast of Broadcast address. +l3_header_padding + + Number of bytes padded to make sure that the L3 header + will always start of a Dword boundary + reserved_5a @@ -395,13 +400,11 @@ lro_eligible Computed out of TCP and IP fields to indicate that this MSDU is eligible for LRO -l3_header_padding - - Number of bytes padded to make sure that the L3 header - will always start of a Dword boundary - reserved_9a + NOTE: DO not assign a field... Internally used in + RXOLE.. + window_size @@ -931,13 +934,22 @@ sa_sw_peer_id #define RX_MSDU_END_5_DA_IS_MCBC_LSB 25 #define RX_MSDU_END_5_DA_IS_MCBC_MASK 0x02000000 +/* Description RX_MSDU_END_5_L3_HEADER_PADDING + + Number of bytes padded to make sure that the L3 header + will always start of a Dword boundary +*/ +#define RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET 0x00000014 +#define RX_MSDU_END_5_L3_HEADER_PADDING_LSB 26 +#define RX_MSDU_END_5_L3_HEADER_PADDING_MASK 0x0c000000 + /* Description RX_MSDU_END_5_RESERVED_5A */ #define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 -#define RX_MSDU_END_5_RESERVED_5A_LSB 26 -#define RX_MSDU_END_5_RESERVED_5A_MASK 0xfc000000 +#define RX_MSDU_END_5_RESERVED_5A_LSB 28 +#define RX_MSDU_END_5_RESERVED_5A_MASK 0xf0000000 /* Description RX_MSDU_END_6_IPV6_OPTIONS_CRC @@ -982,22 +994,16 @@ sa_sw_peer_id #define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 #define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 -/* Description RX_MSDU_END_9_L3_HEADER_PADDING - - Number of bytes padded to make sure that the L3 header - will always start of a Dword boundary -*/ -#define RX_MSDU_END_9_L3_HEADER_PADDING_OFFSET 0x00000024 -#define RX_MSDU_END_9_L3_HEADER_PADDING_LSB 10 -#define RX_MSDU_END_9_L3_HEADER_PADDING_MASK 0x00001c00 - /* Description RX_MSDU_END_9_RESERVED_9A + NOTE: DO not assign a field... Internally used in + RXOLE.. + */ #define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 -#define RX_MSDU_END_9_RESERVED_9A_LSB 13 -#define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000e000 +#define RX_MSDU_END_9_RESERVED_9A_LSB 10 +#define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00 /* Description RX_MSDU_END_9_WINDOW_SIZE diff --git a/hw/qca6290/v1/rx_msdu_link.h b/hw/qca6290/v1/rx_msdu_link.h index 8f7cc6d7dd..9aee7b880d 100644 --- a/hw/qca6290/v1/rx_msdu_link.h +++ b/hw/qca6290/v1/rx_msdu_link.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/rx_msdu_start.h b/hw/qca6290/v1/rx_msdu_start.h index 0be1a43d5b..dcddc58d75 100644 --- a/hw/qca6290/v1/rx_msdu_start.h +++ b/hw/qca6290/v1/rx_msdu_start.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -33,17 +33,16 @@ // Dword Fields // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] // 1 msdu_length[13:0], reserved_1a[14], ipsec_esp[15], l3_offset[22:16], ipsec_ah[23], l4_offset[31:24] -// 2 msdu_number[7:0], decap_format[9:8], ipv4_proto[10], ipv6_proto[11], tcp_proto[12], udp_proto[13], ip_frag[14], tcp_only_ack[15], reserved_2a[31:16] -// 3 reserved_3a[10:0], da_is_bcast_mcast[11], reserved_3b[15:12], ip4_protocol_ip6_next_header[23:16], reserved_3c[30:24], toeplitz_hash[31] -// 4 toeplitz_hash_2_or_4[31:0] -// 5 flow_id_toeplitz[31:0] -// 6 user_rssi[7:0], pkt_type[11:8], stbc[12], sgi[14:13], rate_mcs[18:15], receive_bandwidth[20:19], reception_type[22:21], nss[25:23], reserved_6[31:26] -// 7 ppdu_start_timestamp[31:0] -// 8 sw_phy_meta_data[31:0] +// 2 msdu_number[7:0], decap_format[9:8], ipv4_proto[10], ipv6_proto[11], tcp_proto[12], udp_proto[13], ip_frag[14], tcp_only_ack[15], da_is_bcast_mcast[16], toeplitz_hash[17], reserved_2a[23:18], ip4_protocol_ip6_next_header[31:24] +// 3 toeplitz_hash_2_or_4[31:0] +// 4 flow_id_toeplitz[31:0] +// 5 user_rssi[7:0], pkt_type[11:8], stbc[12], sgi[14:13], rate_mcs[18:15], receive_bandwidth[20:19], reception_type[22:21], nss[25:23], reserved_5[31:26] +// 6 ppdu_start_timestamp[31:0] +// 7 sw_phy_meta_data[31:0] // // ################ END SUMMARY ################# -#define NUM_OF_DWORDS_RX_MSDU_START 9 +#define NUM_OF_DWORDS_RX_MSDU_START 8 struct rx_msdu_start { uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] @@ -64,13 +63,10 @@ struct rx_msdu_start { udp_proto : 1, //[13] ip_frag : 1, //[14] tcp_only_ack : 1, //[15] - reserved_2a : 16; //[31:16] - uint32_t reserved_3a : 11, //[10:0] - da_is_bcast_mcast : 1, //[11] - reserved_3b : 4, //[15:12] - ip4_protocol_ip6_next_header : 8, //[23:16] - reserved_3c : 7, //[30:24] - toeplitz_hash : 1; //[31] + da_is_bcast_mcast : 1, //[16] + toeplitz_hash : 1, //[17] + reserved_2a : 6, //[23:18] + ip4_protocol_ip6_next_header : 8; //[31:24] uint32_t toeplitz_hash_2_or_4 : 32; //[31:0] uint32_t flow_id_toeplitz : 32; //[31:0] uint32_t user_rssi : 8, //[7:0] @@ -81,7 +77,7 @@ struct rx_msdu_start { receive_bandwidth : 2, //[20:19] reception_type : 2, //[22:21] nss : 3, //[25:23] - reserved_6 : 6; //[31:26] + reserved_5 : 6; //[31:26] uint32_t ppdu_start_timestamp : 32; //[31:0] uint32_t sw_phy_meta_data : 32; //[31:0] }; @@ -274,9 +270,10 @@ decap_format - Ethernet 2 (DIX) + Ethernet 2 (DIX) or 802.3 (uses + SNAP/LLC) - 802.3 (uses SNAP/LLC) + DO NOT USE. Indicate Ethernet @@ -309,32 +306,10 @@ tcp_only_ack Set if only the TCP Ack bit is set in the TCP flags and if the TCP payload is 0. -reserved_2a - - - -reserved_3a - - - da_is_bcast_mcast The destination address is broadcast or multicast. -reserved_3b - - - -ip4_protocol_ip6_next_header - - For IPv4 this is the 8 bit protocol field (when - ipv4_proto is set). For IPv6 this is the 8 bit next_header - field (when ipv6_proto is set). - -reserved_3c - - - toeplitz_hash Actual choosen Hash. @@ -346,6 +321,16 @@ toeplitz_hash address, IP destination address, L4 (TCP/UDP) source port, L4 (TCP/UDP) destination port) +reserved_2a + + + +ip4_protocol_ip6_next_header + + For IPv4 this is the 8 bit protocol field (when + ipv4_proto is set). For IPv6 this is the 8 bit next_header + field (when ipv6_proto is set). + toeplitz_hash_2_or_4 Controlled by RxOLE register - If register bit set to 0, @@ -406,9 +391,11 @@ sgi - Legacy normal GI + Legacy normal GI. Can also be + used for HE - Legacy short GI + Legacy short GI. Can also be + used for HE HE related GI @@ -481,7 +468,7 @@ nss 8 spatial streams -reserved_6 +reserved_5 @@ -735,21 +722,17 @@ sw_phy_meta_data - Ethernet 2 (DIX) + Ethernet 2 (DIX) or 802.3 (uses + SNAP/LLC) - 802.3 (uses SNAP/LLC) + DO NOT USE. Indicate Ethernet */ -#ifndef RX_MSDU_START_2_DECAP_FORMAT_OFFSET #define RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008 -#endif -#ifndef RX_MSDU_START_2_DECAP_FORMAT_LSB #define RX_MSDU_START_2_DECAP_FORMAT_LSB 8 -#endif -#ifndef RX_MSDU_START_2_DECAP_FORMAT_MASK #define RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300 -#endif + /* Description RX_MSDU_START_2_IPV4_PROTO Set if L2 layer indicates IPv4 protocol. @@ -803,57 +786,15 @@ sw_phy_meta_data #define RX_MSDU_START_2_TCP_ONLY_ACK_LSB 15 #define RX_MSDU_START_2_TCP_ONLY_ACK_MASK 0x00008000 -/* Description RX_MSDU_START_2_RESERVED_2A - - -*/ -#define RX_MSDU_START_2_RESERVED_2A_OFFSET 0x00000008 -#define RX_MSDU_START_2_RESERVED_2A_LSB 16 -#define RX_MSDU_START_2_RESERVED_2A_MASK 0xffff0000 - -/* Description RX_MSDU_START_3_RESERVED_3A - - -*/ -#define RX_MSDU_START_3_RESERVED_3A_OFFSET 0x0000000c -#define RX_MSDU_START_3_RESERVED_3A_LSB 0 -#define RX_MSDU_START_3_RESERVED_3A_MASK 0x000007ff - -/* Description RX_MSDU_START_3_DA_IS_BCAST_MCAST +/* Description RX_MSDU_START_2_DA_IS_BCAST_MCAST The destination address is broadcast or multicast. */ -#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_OFFSET 0x0000000c -#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_LSB 11 -#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_MASK 0x00000800 +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_OFFSET 0x00000008 +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_MASK 0x00010000 -/* Description RX_MSDU_START_3_RESERVED_3B - - -*/ -#define RX_MSDU_START_3_RESERVED_3B_OFFSET 0x0000000c -#define RX_MSDU_START_3_RESERVED_3B_LSB 12 -#define RX_MSDU_START_3_RESERVED_3B_MASK 0x0000f000 - -/* Description RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER - - For IPv4 this is the 8 bit protocol field (when - ipv4_proto is set). For IPv6 this is the 8 bit next_header - field (when ipv6_proto is set). -*/ -#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000c -#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 16 -#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00ff0000 - -/* Description RX_MSDU_START_3_RESERVED_3C - - -*/ -#define RX_MSDU_START_3_RESERVED_3C_OFFSET 0x0000000c -#define RX_MSDU_START_3_RESERVED_3C_LSB 24 -#define RX_MSDU_START_3_RESERVED_3C_MASK 0x7f000000 - -/* Description RX_MSDU_START_3_TOEPLITZ_HASH +/* Description RX_MSDU_START_2_TOEPLITZ_HASH Actual choosen Hash. @@ -864,22 +805,40 @@ sw_phy_meta_data address, IP destination address, L4 (TCP/UDP) source port, L4 (TCP/UDP) destination port) */ -#define RX_MSDU_START_3_TOEPLITZ_HASH_OFFSET 0x0000000c -#define RX_MSDU_START_3_TOEPLITZ_HASH_LSB 31 -#define RX_MSDU_START_3_TOEPLITZ_HASH_MASK 0x80000000 +#define RX_MSDU_START_2_TOEPLITZ_HASH_OFFSET 0x00000008 +#define RX_MSDU_START_2_TOEPLITZ_HASH_LSB 17 +#define RX_MSDU_START_2_TOEPLITZ_HASH_MASK 0x00020000 -/* Description RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4 +/* Description RX_MSDU_START_2_RESERVED_2A + + +*/ +#define RX_MSDU_START_2_RESERVED_2A_OFFSET 0x00000008 +#define RX_MSDU_START_2_RESERVED_2A_LSB 18 +#define RX_MSDU_START_2_RESERVED_2A_MASK 0x00fc0000 + +/* Description RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER + + For IPv4 this is the 8 bit protocol field (when + ipv4_proto is set). For IPv6 this is the 8 bit next_header + field (when ipv6_proto is set). +*/ +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000 + +/* Description RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4 Controlled by RxOLE register - If register bit set to 0, Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest addresses; otherwise, toeplitz hash is computed over 4-tuple IPv4 or IPv6 src/dest addresses and src/dest ports */ -#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_OFFSET 0x00000010 -#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_LSB 0 -#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000c +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_LSB 0 +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff -/* Description RX_MSDU_START_5_FLOW_ID_TOEPLITZ +/* Description RX_MSDU_START_4_FLOW_ID_TOEPLITZ Toeplitz hash of 5-tuple @@ -902,21 +861,21 @@ sw_phy_meta_data */ -#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_OFFSET 0x00000014 -#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_LSB 0 -#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_MASK 0xffffffff +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET 0x00000010 +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK 0xffffffff -/* Description RX_MSDU_START_6_USER_RSSI +/* Description RX_MSDU_START_5_USER_RSSI RSSI for this user */ -#define RX_MSDU_START_6_USER_RSSI_OFFSET 0x00000018 -#define RX_MSDU_START_6_USER_RSSI_LSB 0 -#define RX_MSDU_START_6_USER_RSSI_MASK 0x000000ff +#define RX_MSDU_START_5_USER_RSSI_OFFSET 0x00000014 +#define RX_MSDU_START_5_USER_RSSI_LSB 0 +#define RX_MSDU_START_5_USER_RSSI_MASK 0x000000ff -/* Description RX_MSDU_START_6_PKT_TYPE +/* Description RX_MSDU_START_5_PKT_TYPE Packet type: @@ -930,27 +889,29 @@ sw_phy_meta_data 802.11ax PPDU type */ -#define RX_MSDU_START_6_PKT_TYPE_OFFSET 0x00000018 -#define RX_MSDU_START_6_PKT_TYPE_LSB 8 -#define RX_MSDU_START_6_PKT_TYPE_MASK 0x00000f00 +#define RX_MSDU_START_5_PKT_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_5_PKT_TYPE_LSB 8 +#define RX_MSDU_START_5_PKT_TYPE_MASK 0x00000f00 -/* Description RX_MSDU_START_6_STBC +/* Description RX_MSDU_START_5_STBC When set, use STBC transmission rates */ -#define RX_MSDU_START_6_STBC_OFFSET 0x00000018 -#define RX_MSDU_START_6_STBC_LSB 12 -#define RX_MSDU_START_6_STBC_MASK 0x00001000 +#define RX_MSDU_START_5_STBC_OFFSET 0x00000014 +#define RX_MSDU_START_5_STBC_LSB 12 +#define RX_MSDU_START_5_STBC_MASK 0x00001000 -/* Description RX_MSDU_START_6_SGI +/* Description RX_MSDU_START_5_SGI Field only valid when pkt type is HT, VHT or HE. - Legacy normal GI + Legacy normal GI. Can also be + used for HE - Legacy short GI + Legacy short GI. Can also be + used for HE HE related GI @@ -958,21 +919,21 @@ sw_phy_meta_data */ -#define RX_MSDU_START_6_SGI_OFFSET 0x00000018 -#define RX_MSDU_START_6_SGI_LSB 13 -#define RX_MSDU_START_6_SGI_MASK 0x00006000 +#define RX_MSDU_START_5_SGI_OFFSET 0x00000014 +#define RX_MSDU_START_5_SGI_LSB 13 +#define RX_MSDU_START_5_SGI_MASK 0x00006000 -/* Description RX_MSDU_START_6_RATE_MCS +/* Description RX_MSDU_START_5_RATE_MCS For details, refer to MCS_TYPE description */ -#define RX_MSDU_START_6_RATE_MCS_OFFSET 0x00000018 -#define RX_MSDU_START_6_RATE_MCS_LSB 15 -#define RX_MSDU_START_6_RATE_MCS_MASK 0x00078000 +#define RX_MSDU_START_5_RATE_MCS_OFFSET 0x00000014 +#define RX_MSDU_START_5_RATE_MCS_LSB 15 +#define RX_MSDU_START_5_RATE_MCS_MASK 0x00078000 -/* Description RX_MSDU_START_6_RECEIVE_BANDWIDTH +/* Description RX_MSDU_START_5_RECEIVE_BANDWIDTH Full receive Bandwidth @@ -990,11 +951,11 @@ sw_phy_meta_data */ -#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_OFFSET 0x00000018 -#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_LSB 19 -#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_MASK 0x00180000 +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET 0x00000014 +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB 19 +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK 0x00180000 -/* Description RX_MSDU_START_6_RECEPTION_TYPE +/* Description RX_MSDU_START_5_RECEPTION_TYPE Indicates what type of reception this is. @@ -1008,11 +969,11 @@ sw_phy_meta_data */ -#define RX_MSDU_START_6_RECEPTION_TYPE_OFFSET 0x00000018 -#define RX_MSDU_START_6_RECEPTION_TYPE_LSB 21 -#define RX_MSDU_START_6_RECEPTION_TYPE_MASK 0x00600000 +#define RX_MSDU_START_5_RECEPTION_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_5_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_START_5_RECEPTION_TYPE_MASK 0x00600000 -/* Description RX_MSDU_START_6_NSS +/* Description RX_MSDU_START_5_NSS Field only valid when Reception_type = reception_type_MU_MIMO or reception_type_MU_OFDMA_MIMO @@ -1039,30 +1000,30 @@ sw_phy_meta_data 8 spatial streams */ -#define RX_MSDU_START_6_NSS_OFFSET 0x00000018 -#define RX_MSDU_START_6_NSS_LSB 23 -#define RX_MSDU_START_6_NSS_MASK 0x03800000 +#define RX_MSDU_START_5_NSS_OFFSET 0x00000014 +#define RX_MSDU_START_5_NSS_LSB 23 +#define RX_MSDU_START_5_NSS_MASK 0x03800000 -/* Description RX_MSDU_START_6_RESERVED_6 +/* Description RX_MSDU_START_5_RESERVED_5 */ -#define RX_MSDU_START_6_RESERVED_6_OFFSET 0x00000018 -#define RX_MSDU_START_6_RESERVED_6_LSB 26 -#define RX_MSDU_START_6_RESERVED_6_MASK 0xfc000000 +#define RX_MSDU_START_5_RESERVED_5_OFFSET 0x00000014 +#define RX_MSDU_START_5_RESERVED_5_LSB 26 +#define RX_MSDU_START_5_RESERVED_5_MASK 0xfc000000 -/* Description RX_MSDU_START_7_PPDU_START_TIMESTAMP +/* Description RX_MSDU_START_6_PPDU_START_TIMESTAMP Timestamp that indicates when the PPDU that contained this MPDU started on the medium. */ -#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_OFFSET 0x0000001c -#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_LSB 0 -#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_MASK 0xffffffff +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_OFFSET 0x00000018 +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_LSB 0 +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_MASK 0xffffffff -/* Description RX_MSDU_START_8_SW_PHY_META_DATA +/* Description RX_MSDU_START_7_SW_PHY_META_DATA SW programmed Meta data provided by the PHY. @@ -1073,9 +1034,9 @@ sw_phy_meta_data */ -#define RX_MSDU_START_8_SW_PHY_META_DATA_OFFSET 0x00000020 -#define RX_MSDU_START_8_SW_PHY_META_DATA_LSB 0 -#define RX_MSDU_START_8_SW_PHY_META_DATA_MASK 0xffffffff +#define RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET 0x0000001c +#define RX_MSDU_START_7_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_7_SW_PHY_META_DATA_MASK 0xffffffff #endif // _RX_MSDU_START_H_ diff --git a/hw/qca6290/v1/rx_reo_queue.h b/hw/qca6290/v1/rx_reo_queue.h index a3f2eebcb0..2e7df0a471 100644 --- a/hw/qca6290/v1/rx_reo_queue.h +++ b/hw/qca6290/v1/rx_reo_queue.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/rx_reo_queue_ext.h b/hw/qca6290/v1/rx_reo_queue_ext.h index f829fac9a3..7365daecb8 100644 --- a/hw/qca6290/v1/rx_reo_queue_ext.h +++ b/hw/qca6290/v1/rx_reo_queue_ext.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/rxpt_classify_info.h b/hw/qca6290/v1/rxpt_classify_info.h index 216c2dd9e4..5cf0992271 100644 --- a/hw/qca6290/v1/rxpt_classify_info.h +++ b/hw/qca6290/v1/rxpt_classify_info.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/seq_hwio.h b/hw/qca6290/v1/seq_hwio.h index fd489f20d8..069735e698 100644 --- a/hw/qca6290/v1/seq_hwio.h +++ b/hw/qca6290/v1/seq_hwio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/sw_xml_headers.h b/hw/qca6290/v1/sw_xml_headers.h index f263386f85..f651ef5b00 100644 --- a/hw/qca6290/v1/sw_xml_headers.h +++ b/hw/qca6290/v1/sw_xml_headers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -28,7 +28,9 @@ #include "addr_search_entry.h" #include "buffer_addr_info.h" #include "cce_rule.h" +#include "ce_dst_desc.h" #include "ce_src_desc.h" +#include "ce_stat_desc.h" #include "he_sig_a_mu_dl_info.h" #include "he_sig_a_mu_ul_info.h" #include "he_sig_a_su_info.h" @@ -125,7 +127,6 @@ #include "who_classify_info.h" #include "macrx_abort_request_info.h" #include "phytx_abort_request_info.h" -#include "ce_stat_desc.h" #include "coex_mac_nap.h" #include "coex_rx_status.h" #include "coex_status_broadcast.h" @@ -139,6 +140,7 @@ #include "mactx_bf_params_common.h" #include "mactx_coex_phy_ctrl.h" #include "mactx_delete_cv.h" +#include "mactx_expect_cbf_common.h" #include "mactx_he_sig_a_mu_dl.h" #include "mactx_he_sig_a_mu_ul.h" #include "mactx_he_sig_a_su.h" @@ -275,7 +277,6 @@ #include "who_terminate.h" #include "data_to_time_config.h" #include "mactx_bf_params_per_user.h" -#include "mactx_expect_cbf_common.h" #include "mactx_expect_cbf_per_user.h" #include "mactx_mu_uplink_user_setup.h" #include "mactx_service.h" @@ -312,7 +313,6 @@ #include "tqm_acked_mpdu.h" #include "tqm_update_tx_mpdu_count.h" #include "tx_11ah_setup.h" -#include "tx_cv_start.h" #include "tx_fes_status_ack_or_ba.h" #include "tx_fes_status_user_ppdu.h" #include "tx_fes_status_user_response.h" diff --git a/hw/qca6290/v1/tcl_data_cmd.h b/hw/qca6290/v1/tcl_data_cmd.h index dd4920945c..2b5ad34ba3 100644 --- a/hw/qca6290/v1/tcl_data_cmd.h +++ b/hw/qca6290/v1/tcl_data_cmd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -118,9 +118,10 @@ encap_type - Ethernet 2 (DIX) + Ethernet 2 (DIX) or 802.3 (uses + SNAP/LLC) - 802.3 (uses SNAP/LLC) + DO NOT USE. Indicate Ethernet Used by the OLE during encapsulation. @@ -235,22 +236,12 @@ data_length ipv4_checksum_en - Field only valid when msdu_buffer_type is set to - MSDU_buffer. - - - OLE related control Enable IPv4 checksum replacement udp_over_ipv4_checksum_en - Field only valid when msdu_buffer_type is set to - MSDU_buffer. - - - OLE related control Enable UDP over IPv4 checksum replacement. UDP checksum @@ -258,11 +249,6 @@ udp_over_ipv4_checksum_en udp_over_ipv6_checksum_en - Field only valid when msdu_buffer_type is set to - MSDU_buffer. - - - OLE related control Enable UDP over IPv6 checksum replacement. UDP checksum @@ -270,22 +256,12 @@ udp_over_ipv6_checksum_en tcp_over_ipv4_checksum_en - Field only valid when msdu_buffer_type is set to - MSDU_buffer. - - - OLE related control Enable TCP checksum over IPv4 replacement tcp_over_ipv6_checksum_en - Field only valid when msdu_buffer_type is set to - MSDU_buffer. - - - OLE related control Enable TCP checksum over IPv6 replacement @@ -468,9 +444,10 @@ looping_count - Ethernet 2 (DIX) + Ethernet 2 (DIX) or 802.3 (uses + SNAP/LLC) - 802.3 (uses SNAP/LLC) + DO NOT USE. Indicate Ethernet Used by the OLE during encapsulation. @@ -621,11 +598,6 @@ looping_count /* Description TCL_DATA_CMD_3_IPV4_CHECKSUM_EN - Field only valid when msdu_buffer_type is set to - MSDU_buffer. - - - OLE related control Enable IPv4 checksum replacement @@ -636,11 +608,6 @@ looping_count /* Description TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN - Field only valid when msdu_buffer_type is set to - MSDU_buffer. - - - OLE related control Enable UDP over IPv4 checksum replacement. UDP checksum @@ -652,11 +619,6 @@ looping_count /* Description TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN - Field only valid when msdu_buffer_type is set to - MSDU_buffer. - - - OLE related control Enable UDP over IPv6 checksum replacement. UDP checksum @@ -668,11 +630,6 @@ looping_count /* Description TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN - Field only valid when msdu_buffer_type is set to - MSDU_buffer. - - - OLE related control Enable TCP checksum over IPv4 replacement @@ -683,11 +640,6 @@ looping_count /* Description TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN - Field only valid when msdu_buffer_type is set to - MSDU_buffer. - - - OLE related control Enable TCP checksum over IPv6 replacement diff --git a/hw/qca6290/v1/tcl_gse_cmd.h b/hw/qca6290/v1/tcl_gse_cmd.h index 56eee91a6c..3875a6d773 100644 --- a/hw/qca6290/v1/tcl_gse_cmd.h +++ b/hw/qca6290/v1/tcl_gse_cmd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/tcl_status_ring.h b/hw/qca6290/v1/tcl_status_ring.h index c4178c93da..8ad5d8806f 100644 --- a/hw/qca6290/v1/tcl_status_ring.h +++ b/hw/qca6290/v1/tcl_status_ring.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/tlv_hdr.h b/hw/qca6290/v1/tlv_hdr.h index 17957c0d89..e9312a772b 100644 --- a/hw/qca6290/v1/tlv_hdr.h +++ b/hw/qca6290/v1/tlv_hdr.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -16,67 +16,67 @@ * PERFORMANCE OF THIS SOFTWARE. */ -// $ATH_LICENSE_HW_HDR_C$ -// -// DO NOT EDIT! This file is automatically generated -// These definitions are tied to a particular hardware layout - -#ifndef _TLV_HDR_H_ -#define _TLV_HDR_H_ -#if !defined(__ASSEMBLER__) -#endif - -struct tlv_usr_16_hdr { - volatile uint16_t tlv_cflg_reserved : 1, - tlv_tag : 5, - tlv_len : 4, - tlv_usrid : 6; -}; - -struct tlv_16_hdr { - volatile uint16_t tlv_cflg_reserved : 1, - tlv_tag : 5, - tlv_len : 4, - tlv_reserved : 6; -}; - -struct tlv_usr_32_hdr { - volatile uint32_t tlv_cflg_reserved : 1, - tlv_tag : 9, - tlv_len : 16, - tlv_usrid : 6; -}; - -struct tlv_32_hdr { - volatile uint32_t tlv_cflg_reserved : 1, - tlv_tag : 9, - tlv_len : 16, - tlv_reserved : 6; -}; - -struct tlv_usr_42_hdr { - volatile uint64_t tlv_compression : 1, - tlv_tag : 9, - tlv_len : 16, - tlv_usrid : 6, - tlv_reserved : 10, - pad_42to64_bit : 22; -}; - -struct tlv_42_hdr { - volatile uint64_t tlv_compression : 1, - tlv_tag : 9, - tlv_len : 16, - tlv_reserved : 16, - pad_42to64_bit : 22; -}; - -struct tlv_usr_c_42_hdr { - volatile uint64_t tlv_compression : 1, - tlv_ctag : 3, - tlv_usrid : 6, - tlv_cdata : 32, - pad_42to64_bit : 22; -}; - -#endif +// $ATH_LICENSE_HW_HDR_C$ +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + +#ifndef _TLV_HDR_H_ +#define _TLV_HDR_H_ +#if !defined(__ASSEMBLER__) +#endif + +struct tlv_usr_16_hdr { + volatile uint16_t tlv_cflg_reserved : 1, + tlv_tag : 5, + tlv_len : 4, + tlv_usrid : 6; +}; + +struct tlv_16_hdr { + volatile uint16_t tlv_cflg_reserved : 1, + tlv_tag : 5, + tlv_len : 4, + tlv_reserved : 6; +}; + +struct tlv_usr_32_hdr { + volatile uint32_t tlv_cflg_reserved : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_usrid : 6; +}; + +struct tlv_32_hdr { + volatile uint32_t tlv_cflg_reserved : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_reserved : 6; +}; + +struct tlv_usr_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_usrid : 6, + tlv_reserved : 10, + pad_42to64_bit : 22; +}; + +struct tlv_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_reserved : 16, + pad_42to64_bit : 22; +}; + +struct tlv_usr_c_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_ctag : 3, + tlv_usrid : 6, + tlv_cdata : 32, + pad_42to64_bit : 22; +}; + +#endif diff --git a/hw/qca6290/v1/tlv_tag_def.h b/hw/qca6290/v1/tlv_tag_def.h index ca0c5aff30..11aadcf52a 100644 --- a/hw/qca6290/v1/tlv_tag_def.h +++ b/hw/qca6290/v1/tlv_tag_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -16,6 +16,7 @@ * PERFORMANCE OF THIS SOFTWARE. */ + /** * Generated file ... Do not hand edit ... */ @@ -178,7 +179,7 @@ typedef enum { WIFIMPDU_INFO_E = 150 /* 0x96 */, WIFIPDG_USER_SETUP_E = 151 /* 0x97 */, WIFITX_11AH_SETUP_E = 152 /* 0x98 */, - WIFITX_CV_START_E = 153 /* 0x99 */, + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 153 /* 0x99 */, WIFITX_PEER_ENTRY_E = 154 /* 0x9a */, WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 155 /* 0x9b */, WIFIEXAMPLE_STRUCT_NAME_E = 156 /* 0x9c */, @@ -445,7 +446,7 @@ typedef enum { WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 417 /* 0x1a1 */, WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 418 /* 0x1a2 */, WIFIREO_UPDATE_RX_REO_QUEUE_E = 419 /* 0x1a3 */, - WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 420 /* 0x1a4 */, + WIFICE_DST_DESC_E = 420 /* 0x1a4 */, WIFITLV_BASE_E = 511 /* 0x1ff */ } tlv_tag_def__e; ///< tlv_tag_def Enum Type diff --git a/hw/qca6290/v1/tx_msdu_extension.h b/hw/qca6290/v1/tx_msdu_extension.h index bf7f00f2da..1a55b4a6bb 100644 --- a/hw/qca6290/v1/tx_msdu_extension.h +++ b/hw/qca6290/v1/tx_msdu_extension.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -113,24 +113,44 @@ tso_enable ipv4_checksum_en + FIELD NOT USED IN HAWKEYE 1.0 + + + Enable IPv4 checksum replacement udp_over_ipv4_checksum_en + FIELD NOT USED IN HAWKEYE 1.0 + + + Enable UDP over IPv4 checksum replacement. UDP checksum over IPv4 is optional for TCP/IP stacks. udp_over_ipv6_checksum_en + FIELD NOT USED IN HAWKEYE 1.0 + + + Enable UDP over IPv6 checksum replacement. UDP checksum over IPv6 is mandatory for TCP/IP stacks. tcp_over_ipv4_checksum_en + FIELD NOT USED IN HAWKEYE 1.0 + + + Enable TCP checksum over IPv4 replacement tcp_over_ipv6_checksum_en + FIELD NOT USED IN HAWKEYE 1.0 + + + Enable TCP checksum over IPv6 eplacement reserved_0a @@ -380,6 +400,10 @@ buf5_len /* Description TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN + FIELD NOT USED IN HAWKEYE 1.0 + + + Enable IPv4 checksum replacement */ #define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_OFFSET 0x00000000 @@ -388,6 +412,10 @@ buf5_len /* Description TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN + FIELD NOT USED IN HAWKEYE 1.0 + + + Enable UDP over IPv4 checksum replacement. UDP checksum over IPv4 is optional for TCP/IP stacks. */ @@ -397,6 +425,10 @@ buf5_len /* Description TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN + FIELD NOT USED IN HAWKEYE 1.0 + + + Enable UDP over IPv6 checksum replacement. UDP checksum over IPv6 is mandatory for TCP/IP stacks. */ @@ -406,6 +438,10 @@ buf5_len /* Description TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN + FIELD NOT USED IN HAWKEYE 1.0 + + + Enable TCP checksum over IPv4 replacement */ #define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000 @@ -414,6 +450,10 @@ buf5_len /* Description TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN + FIELD NOT USED IN HAWKEYE 1.0 + + + Enable TCP checksum over IPv6 eplacement */ #define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000 diff --git a/hw/qca6290/v1/tx_rate_stats_info.h b/hw/qca6290/v1/tx_rate_stats_info.h index d095588498..8dfc2b848c 100644 --- a/hw/qca6290/v1/tx_rate_stats_info.h +++ b/hw/qca6290/v1/tx_rate_stats_info.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -151,9 +151,11 @@ transmit_sgi - Legacy normal GI + Legacy normal GI. Can also be + used for HE - Legacy short GI + Legacy short GI. Can also be + used for HE HE related GI @@ -206,14 +208,6 @@ tones_in_ru The number of tones in the RU used. - - - TODO: not clear yet what the number of tones is for RUs - of 160 or 80 + 80 ??? - - For now assumption is that this value for this scenario - will indicate: 0x7FF - reserved_0a @@ -350,9 +344,11 @@ tsf_directly_after_ppdu_transmission - Legacy normal GI + Legacy normal GI. Can also be + used for HE - Legacy short GI + Legacy short GI. Can also be + used for HE HE related GI @@ -417,14 +413,6 @@ tsf_directly_after_ppdu_transmission The number of tones in the RU used. - - - TODO: not clear yet what the number of tones is for RUs - of 160 or 80 + 80 ??? - - For now assumption is that this value for this scenario - will indicate: 0x7FF - */ #define TX_RATE_STATS_INFO_0_TONES_IN_RU_OFFSET 0x00000000 diff --git a/hw/qca6290/v1/uniform_descriptor_header.h b/hw/qca6290/v1/uniform_descriptor_header.h index bb0214f648..2ae453ab1e 100644 --- a/hw/qca6290/v1/uniform_descriptor_header.h +++ b/hw/qca6290/v1/uniform_descriptor_header.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -100,7 +100,7 @@ buffer_type - + NOT TO BE USED: @@ -189,7 +189,7 @@ reserved_0a - + NOT TO BE USED: diff --git a/hw/qca6290/v1/uniform_reo_cmd_header.h b/hw/qca6290/v1/uniform_reo_cmd_header.h index 843fc4735f..e770f938c4 100644 --- a/hw/qca6290/v1/uniform_reo_cmd_header.h +++ b/hw/qca6290/v1/uniform_reo_cmd_header.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/uniform_reo_status_header.h b/hw/qca6290/v1/uniform_reo_status_header.h index 6f7fd94b86..364fbb1c12 100644 --- a/hw/qca6290/v1/uniform_reo_status_header.h +++ b/hw/qca6290/v1/uniform_reo_status_header.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/wbm_buffer_ring.h b/hw/qca6290/v1/wbm_buffer_ring.h index eaffc26dca..307fa46f51 100644 --- a/hw/qca6290/v1/wbm_buffer_ring.h +++ b/hw/qca6290/v1/wbm_buffer_ring.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/wbm_link_descriptor_ring.h b/hw/qca6290/v1/wbm_link_descriptor_ring.h index 28448c5e24..c3d321f561 100644 --- a/hw/qca6290/v1/wbm_link_descriptor_ring.h +++ b/hw/qca6290/v1/wbm_link_descriptor_ring.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/hw/qca6290/v1/wbm_reg_seq_hwiobase.h b/hw/qca6290/v1/wbm_reg_seq_hwiobase.h index f0d267b67a..27f43398f4 100644 --- a/hw/qca6290/v1/wbm_reg_seq_hwiobase.h +++ b/hw/qca6290/v1/wbm_reg_seq_hwiobase.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -18,8 +18,8 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// wbm_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 -// User Name:pgohil +// wbm_reg_seq_hwiobase.h : automatically generated by Autoseq 3.1 9/30/2016 +// User Name:kanalas // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. // diff --git a/hw/qca6290/v1/wbm_reg_seq_hwioreg.h b/hw/qca6290/v1/wbm_reg_seq_hwioreg.h index 600376c48c..28c8036cee 100644 --- a/hw/qca6290/v1/wbm_reg_seq_hwioreg.h +++ b/hw/qca6290/v1/wbm_reg_seq_hwioreg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -18,8 +18,8 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// wbm_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 -// User Name:pgohil +// wbm_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 9/30/2016 +// User Name:kanalas // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. // @@ -451,7 +451,7 @@ #define HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x) (x+0x00000034) #define HWIO_WBM_R0_MSDU_PARSER_STATUS_PHYS(x) (x+0x00000034) -#define HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK 0x0007ffff +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK 0x000fffff #define HWIO_WBM_R0_MSDU_PARSER_STATUS_SHFT 0 #define HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK) @@ -466,6 +466,9 @@ HWIO_INTFREE();\ } while (0) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_BMSK 0x00080000 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_SHFT 0x13 + #define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_BMSK 0x00078000 #define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_SHFT 0xf @@ -1423,7 +1426,7 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x) (x+0x000000d0) #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_PHYS(x) (x+0x000000d0) -#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK) @@ -1438,9 +1441,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -1632,7 +1632,7 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000104) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000104) -#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -1647,7 +1647,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -1701,7 +1701,7 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000011c) #define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000011c) -#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) @@ -1716,7 +1716,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_TQM_RELEASE_RING_BASE_LSB //// @@ -1770,7 +1770,7 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x) (x+0x00000128) #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_PHYS(x) (x+0x00000128) -#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK) @@ -1785,9 +1785,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -1979,7 +1976,7 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000015c) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000015c) -#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -1994,7 +1991,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -2048,7 +2045,7 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000174) #define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000174) -#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) @@ -2063,7 +2060,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_REO_RELEASE_RING_BASE_LSB //// @@ -2117,7 +2114,7 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x00000180) #define HWIO_WBM_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x00000180) -#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_REO_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK) @@ -2132,9 +2129,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2326,7 +2320,7 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001b4) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001b4) -#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -2341,7 +2335,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -2395,7 +2389,7 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001cc) #define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001cc) -#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) @@ -2410,7 +2404,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_SW_RELEASE_RING_BASE_LSB //// @@ -2464,7 +2458,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x) (x+0x000001d8) #define HWIO_WBM_R0_SW_RELEASE_RING_ID_PHYS(x) (x+0x000001d8) -#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_SW_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK) @@ -2479,9 +2473,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2673,7 +2664,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000020c) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000020c) -#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -2688,7 +2679,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -2811,7 +2802,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000224) #define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000224) -#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) @@ -2826,7 +2817,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_FW_RELEASE_RING_BASE_LSB //// @@ -2880,7 +2871,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x) (x+0x00000230) #define HWIO_WBM_R0_FW_RELEASE_RING_ID_PHYS(x) (x+0x00000230) -#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_FW_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK) @@ -2895,9 +2886,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -3089,7 +3077,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000264) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000264) -#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -3104,7 +3092,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -3227,7 +3215,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000027c) #define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000027c) -#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) @@ -3242,7 +3230,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB //// @@ -3296,7 +3284,7 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x) (x+0x00000288) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_PHYS(x) (x+0x00000288) -#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK) @@ -3311,9 +3299,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -3505,7 +3490,7 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000002bc) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000002bc) -#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -3520,7 +3505,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -3574,7 +3559,7 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002d4) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002d4) -#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) @@ -3589,7 +3574,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB //// @@ -3643,7 +3628,7 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x) (x+0x000002e0) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_PHYS(x) (x+0x000002e0) -#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RMSK) @@ -3658,9 +3643,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -3852,7 +3834,7 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000314) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000314) -#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -3867,7 +3849,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -3921,7 +3903,7 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000032c) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000032c) -#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) @@ -3936,356 +3918,9 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 -//// Register WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB //// - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000330) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000330) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_SHFT 0 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RMSK) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), mask) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_OUT(x, val) \ - out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), val) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 - -//// Register WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB //// - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000334) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000334) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_SHFT 0 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RMSK) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), mask) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_OUT(x, val) \ - out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), val) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 - -//// Register WBM_R0_RXDMA2_RELEASE_RING_ID //// - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x) (x+0x00000338) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_PHYS(x) (x+0x00000338) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RMSK 0x0000ffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_SHFT 0 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RMSK) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), mask) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_OUT(x, val) \ - out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), val) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RING_ID_SHFT 0x8 - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 - -//// Register WBM_R0_RXDMA2_RELEASE_RING_STATUS //// - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x) (x+0x0000033c) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_PHYS(x) (x+0x0000033c) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_SHFT 0 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_RMSK) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), mask) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_OUT(x, val) \ - out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), val) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 - -//// Register WBM_R0_RXDMA2_RELEASE_RING_MISC //// - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x) (x+0x00000340) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_PHYS(x) (x+0x00000340) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RMSK 0x0000003f -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_SHFT 0 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RMSK) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), mask) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_OUT(x, val) \ - out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), val) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 - -//// Register WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB //// - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000034c) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000034c) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_SHFT 0 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_RMSK) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ - out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 - -//// Register WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB //// - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000350) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000350) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_SHFT 0 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_RMSK) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ - out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 - -//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000360) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000360) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ - out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 - -//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000364) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000364) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ - out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 - -//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS //// - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000368) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000368) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ - out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 - -//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000036c) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000036c) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ - out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 - -//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000370) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000370) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ - out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 - -//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000374) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000374) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ - out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 - -//// Register WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET //// - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000384) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000384) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ - out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 - //// Register WBM_R0_WBM2PPE_BUF_RING_BASE_LSB //// #define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000388) @@ -4524,7 +4159,7 @@ #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003b4) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003b4) -#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -4539,14 +4174,14 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003dc) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003dc) -#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK) @@ -4561,7 +4196,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2SW_BUF_RING_BASE_LSB //// @@ -4802,7 +4437,7 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000040c) #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000040c) -#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -4817,7 +4452,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB //// @@ -4893,7 +4528,7 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000434) #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000434) -#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK) @@ -4908,7 +4543,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2FW_BUF_RING_BASE_LSB //// @@ -5149,7 +4784,7 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000464) #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000464) -#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -5164,7 +4799,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB //// @@ -5240,7 +4875,7 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000048c) #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000048c) -#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK) @@ -5255,7 +4890,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB //// @@ -5496,7 +5131,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004bc) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004bc) -#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -5511,14 +5146,14 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004e4) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004e4) -#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK) @@ -5533,7 +5168,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB //// @@ -5774,7 +5409,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000514) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000514) -#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -5789,14 +5424,14 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000053c) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000053c) -#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_RMSK) @@ -5811,287 +5446,9 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 -//// Register WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB //// - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000540) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_PHYS(x) (x+0x00000540) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB //// - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x) (x+0x00000544) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_PHYS(x) (x+0x00000544) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RMSK 0x00ffffff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_BUF_RING_ID //// - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x) (x+0x00000548) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_PHYS(x) (x+0x00000548) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RMSK 0x0000ffff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RING_ID_SHFT 0x8 - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_BUF_RING_STATUS //// - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x) (x+0x0000054c) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_PHYS(x) (x+0x0000054c) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_RMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_BUF_RING_MISC //// - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x) (x+0x00000550) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_PHYS(x) (x+0x00000550) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RMSK 0x0000003f -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB //// - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000554) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000554) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB //// - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000558) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000558) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP //// - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000564) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000564) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS //// - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000568) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000568) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER //// - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000056c) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000056c) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET //// - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000594) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000594) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 - //// Register WBM_R0_WBM2TQM_LINK_RING_BASE_LSB //// #define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000598) @@ -6330,7 +5687,7 @@ #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000005c4) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000005c4) -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -6345,14 +5702,14 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000005ec) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000005ec) -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK) @@ -6367,7 +5724,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2REO_LINK_RING_BASE_LSB //// @@ -6608,7 +5965,7 @@ #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000061c) #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000061c) -#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -6623,14 +5980,14 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000644) #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000644) -#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) @@ -6645,7 +6002,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2SW_LINK_RING_BASE_LSB //// @@ -6886,7 +6243,7 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000674) #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000674) -#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -6901,7 +6258,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB //// @@ -6977,7 +6334,7 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000069c) #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000069c) -#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK) @@ -6992,7 +6349,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2FW_LINK_RING_BASE_LSB //// @@ -7233,7 +6590,7 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000006cc) #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000006cc) -#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -7248,7 +6605,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB //// @@ -7324,7 +6681,7 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006f4) #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006f4) -#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK) @@ -7339,7 +6696,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB //// @@ -7580,7 +6937,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000724) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000724) -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -7595,14 +6952,14 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000074c) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000074c) -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK) @@ -7617,7 +6974,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB //// @@ -7858,7 +7215,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000077c) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000077c) -#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -7873,14 +7230,14 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007a4) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007a4) -#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_RMSK) @@ -7895,287 +7252,9 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 -//// Register WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB //// - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x) (x+0x000007a8) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_PHYS(x) (x+0x000007a8) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB //// - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x) (x+0x000007ac) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_PHYS(x) (x+0x000007ac) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RMSK 0x00ffffff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_LINK_RING_ID //// - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x) (x+0x000007b0) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_PHYS(x) (x+0x000007b0) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RMSK 0x0000ffff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RING_ID_SHFT 0x8 - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_LINK_RING_STATUS //// - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x) (x+0x000007b4) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_PHYS(x) (x+0x000007b4) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_RMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_LINK_RING_MISC //// - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x) (x+0x000007b8) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_PHYS(x) (x+0x000007b8) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RMSK 0x0000003f -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB //// - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x000007bc) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x000007bc) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB //// - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x000007c0) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x000007c0) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP //// - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000007cc) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000007cc) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS //// - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000007d0) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000007d0) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER //// - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000007d4) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000007d4) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 - -//// Register WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET //// - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007fc) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007fc) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_RMSK) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ - out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 - //// Register WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB //// #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000800) @@ -8458,7 +7537,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000082c) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000082c) -#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -8473,7 +7552,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0 //// @@ -8558,7 +7637,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000083c) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000083c) -#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -8573,7 +7652,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER //// @@ -8627,7 +7706,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000854) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000854) -#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK) @@ -8642,7 +7721,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB //// @@ -8927,7 +8006,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000884) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000884) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -8942,7 +8021,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0 //// @@ -9027,7 +8106,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000894) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000894) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -9042,7 +8121,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER //// @@ -9096,7 +8175,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008ac) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008ac) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK) @@ -9111,7 +8190,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB //// @@ -9352,7 +8431,7 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008dc) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008dc) -#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -9367,7 +8446,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB //// @@ -9443,7 +8522,7 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000904) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000904) -#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) @@ -9458,7 +8537,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB //// @@ -9699,7 +8778,7 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000934) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000934) -#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -9714,7 +8793,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB //// @@ -9790,7 +8869,7 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000095c) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000095c) -#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) @@ -9805,7 +8884,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB //// @@ -10046,7 +9125,7 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000098c) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000098c) -#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -10061,7 +9140,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB //// @@ -10137,7 +9216,7 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000009b4) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000009b4) -#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) @@ -10152,7 +9231,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB //// @@ -10393,7 +9472,7 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000009e4) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000009e4) -#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -10408,7 +9487,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB //// @@ -10484,7 +9563,7 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000a0c) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000a0c) -#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) @@ -10499,7 +9578,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB //// @@ -10740,7 +9819,7 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000a3c) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000a3c) -#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -10755,7 +9834,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB //// @@ -10831,7 +9910,7 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000a64) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000a64) -#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) @@ -10846,7 +9925,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R1_END_OF_TEST_CHECK //// @@ -11465,50 +10544,6 @@ #define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 -//// Register WBM_R2_RXDMA2_RELEASE_RING_HP //// - -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x) (x+0x00003038) -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_PHYS(x) (x+0x00003038) -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_RMSK 0x0000ffff -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_SHFT 0 -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_IN(x) \ - in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_RMSK) -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), mask) -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_OUT(x, val) \ - out_dword( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), val) -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 - -//// Register WBM_R2_RXDMA2_RELEASE_RING_TP //// - -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x) (x+0x0000303c) -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_PHYS(x) (x+0x0000303c) -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_RMSK 0x0000ffff -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_SHFT 0 -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_IN(x) \ - in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_RMSK) -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), mask) -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_OUT(x, val) \ - out_dword( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), val) -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff -#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 - //// Register WBM_R2_WBM2PPE_BUF_RING_HP //// #define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x) (x+0x00003040) @@ -11729,50 +10764,6 @@ #define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_TAIL_PTR_SHFT 0x0 -//// Register WBM_R2_WBM2RXDMA2_BUF_RING_HP //// - -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x) (x+0x00003068) -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_PHYS(x) (x+0x00003068) -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_RMSK 0x0000ffff -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_SHFT 0 -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_IN(x) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_RMSK) -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), mask) -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_OUT(x, val) \ - out_dword( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), val) -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_HEAD_PTR_SHFT 0x0 - -//// Register WBM_R2_WBM2RXDMA2_BUF_RING_TP //// - -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x) (x+0x0000306c) -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_PHYS(x) (x+0x0000306c) -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_RMSK 0x0000ffff -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_SHFT 0 -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_IN(x) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_RMSK) -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), mask) -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_OUT(x, val) \ - out_dword( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), val) -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff -#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_TAIL_PTR_SHFT 0x0 - //// Register WBM_R2_WBM2TQM_LINK_RING_HP //// #define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x) (x+0x00003070) @@ -12037,50 +11028,6 @@ #define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_TAIL_PTR_SHFT 0x0 -//// Register WBM_R2_WBM2RXDMA2_LINK_RING_HP //// - -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x) (x+0x000030a0) -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_PHYS(x) (x+0x000030a0) -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_RMSK 0x0000ffff -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_SHFT 0 -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_IN(x) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_RMSK) -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), mask) -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_OUT(x, val) \ - out_dword( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), val) -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_HEAD_PTR_SHFT 0x0 - -//// Register WBM_R2_WBM2RXDMA2_LINK_RING_TP //// - -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x) (x+0x000030a4) -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_PHYS(x) (x+0x000030a4) -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_RMSK 0x0000ffff -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_SHFT 0 -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_IN(x) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_RMSK) -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), mask) -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_OUT(x, val) \ - out_dword( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), val) -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_OUTM(x, mask, val) \ - do {\ - HWIO_INTLOCK(); \ - out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_IN(x)); \ - HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff -#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_TAIL_PTR_SHFT 0x0 - //// Register WBM_R2_WBM_IDLE_BUF_RING_HP //// #define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x) (x+0x000030a8) diff --git a/hw/qca6290/v1/wbm_release_ring.h b/hw/qca6290/v1/wbm_release_ring.h index fb25038ad7..83eba88316 100644 --- a/hw/qca6290/v1/wbm_release_ring.h +++ b/hw/qca6290/v1/wbm_release_ring.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -318,7 +318,8 @@ rxdma_error_code CRYPTO reported a decryption - error + error or CRYPTO received an encrypted frame, but did not get + a valid corresponding key id in the peer entry. CRYPTO reported a TKIP MIC error @@ -636,6 +637,39 @@ sw_peer_id + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 + + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + + buffer_or_desc_type = e_num1 + msdu_link_descriptortqm_release_reason can be:e_num 1 + tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged + + + Sw_peer_id from the TX_MSDU_FLOW descriptor or TX_MPDU_QUEUE descriptor @@ -648,9 +682,47 @@ tid - TID of the flow or MPDU queue + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 - + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + + buffer_or_desc_type = e_num1 + msdu_link_descriptortqm_release_reason can be:e_num 1 + tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged + + + + + + This field represents the TID from the TX_MSDU_FLOW + descriptor or TX_MPDU_QUEUE descriptor + + + + ring_id @@ -960,7 +1032,8 @@ looping_count CRYPTO reported a decryption - error + error or CRYPTO received an encrypted frame, but did not get + a valid corresponding key id in the peer entry. CRYPTO reported a TKIP MIC error @@ -1334,6 +1407,39 @@ looping_count + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 + + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + + buffer_or_desc_type = e_num1 + msdu_link_descriptortqm_release_reason can be:e_num 1 + tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged + + + Sw_peer_id from the TX_MSDU_FLOW descriptor or TX_MPDU_QUEUE descriptor @@ -1350,9 +1456,47 @@ looping_count - TID of the flow or MPDU queue + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 - + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + + buffer_or_desc_type = e_num1 + msdu_link_descriptortqm_release_reason can be:e_num 1 + tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged + + + + + + This field represents the TID from the TX_MSDU_FLOW + descriptor or TX_MPDU_QUEUE descriptor + + + + */ #define WBM_RELEASE_RING_7_TID_OFFSET 0x0000001c #define WBM_RELEASE_RING_7_TID_LSB 16 diff --git a/hw/qca6290/v1/wcss_seq_hwiobase.h b/hw/qca6290/v1/wcss_seq_hwiobase.h index 8efcab08ec..0b65145280 100644 --- a/hw/qca6290/v1/wcss_seq_hwiobase.h +++ b/hw/qca6290/v1/wcss_seq_hwiobase.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -18,8 +18,8 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 -// User Name:pgohil +// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.1 9/30/2016 +// User Name:kanalas // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. // @@ -29,7 +29,7 @@ #define __WCSS_SEQ_BASE_H__ #ifdef SCALE_INCLUDES - #include "HALhwio.h" + #include "../../../include/HALhwio.h" #else #include "msmhwio.h" #endif @@ -39,56 +39,135 @@ // Instance Relative Offsets from Block wcss /////////////////////////////////////////////////////////////////////////////////////////////// -#define SEQ_WCSS_ECAHB_OFFSET 0x00008000 +#define SEQ_WCSS_ECAHB_OFFSET 0x00008400 #define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 -#define SEQ_WCSS_MPSS_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00240000 -#define SEQ_WCSS_MPSS_PCSS_B_REG_MAP_OFFSET 0x00250000 -#define SEQ_WCSS_PHYA0_OFFSET 0x00400000 -#define SEQ_WCSS_PHYA0_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00400000 -#define SEQ_WCSS_PHYA0_WFAX_PCSS_REG_MAP_OFFSET 0x00480000 -#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00480400 -#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00480800 -#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00480c00 -#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00481000 -#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00481400 -#define SEQ_WCSS_PHYA0_WFAX_NOC_REG_MAP_OFFSET 0x00484000 -#define SEQ_WCSS_PHYA0_WFAX_TXTD_REG_MAP_OFFSET 0x00488000 -#define SEQ_WCSS_PHYA0_WFAX_TXFD_REG_MAP_OFFSET 0x00500000 -#define SEQ_WCSS_PHYA0_WFAX_ROBE_REG_MAP_OFFSET 0x00520000 -#define SEQ_WCSS_PHYA0_WFAX_RXTD_REG_MAP_OFFSET 0x00528000 -#define SEQ_WCSS_PHYA0_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00530000 -#define SEQ_WCSS_PHYA0_WFAX_PHYRF_REG_MAP_OFFSET 0x005a0000 -#define SEQ_WCSS_PHYA1_OFFSET 0x00600000 -#define SEQ_WCSS_PHYA1_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00600000 -#define SEQ_WCSS_PHYA1_WFAX_PCSS_REG_MAP_OFFSET 0x00680000 -#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00680400 -#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00680800 -#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00680c00 -#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00681000 -#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00681400 -#define SEQ_WCSS_PHYA1_WFAX_NOC_REG_MAP_OFFSET 0x00684000 -#define SEQ_WCSS_PHYA1_WFAX_TXTD_REG_MAP_OFFSET 0x00688000 -#define SEQ_WCSS_PHYA1_WFAX_TXFD_REG_MAP_OFFSET 0x00700000 -#define SEQ_WCSS_PHYA1_WFAX_ROBE_REG_MAP_OFFSET 0x00720000 -#define SEQ_WCSS_PHYA1_WFAX_RXTD_REG_MAP_OFFSET 0x00728000 -#define SEQ_WCSS_PHYA1_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00730000 -#define SEQ_WCSS_PHYA1_WFAX_PHYRF_REG_MAP_OFFSET 0x007a0000 -#define SEQ_WCSS_PHYB_OFFSET 0x00800000 -#define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00800000 -#define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET 0x00880000 -#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00880400 -#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00880800 -#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00880c00 -#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00881000 -#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00881400 -#define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET 0x00884000 -#define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET 0x00888000 -#define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET 0x00900000 -#define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET 0x00920000 -#define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET 0x00928000 -#define SEQ_WCSS_PHYB_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00930000 -#define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET 0x009a0000 +#define SEQ_WCSS_PHYA_OFFSET 0x00400000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00400000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00480000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00480400 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00480800 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00480c00 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00481000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00481400 +#define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00484000 +#define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x00488000 +#define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00500000 +#define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x00520000 +#define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x00528000 +#define SEQ_WCSS_PHYA_WFAX_DEMFRONT_NPRA_REG_MAP_OFFSET 0x00530000 +#define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x005a0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_DIG_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_DIG_OTP_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_DIG_TLMM_OFFSET 0x005c4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x005c8000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x005d6080 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d60e0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6100 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6140 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d6180 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x005d6880 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d68e0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d6900 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6940 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d6980 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x005e0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e0400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e0800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x005e1000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x005e1200 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x005e2000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x005e8000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x005e8400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x005e8800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x005e9000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x005e9200 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x005ea000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x005f0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x005f0400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x005f0800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET 0x005f1000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET 0x005f1200 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x005f2000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x005f8000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x005f8400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x005f8800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET 0x005f9000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET 0x005f9200 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x005fa000 +#define SEQ_WCSS_PHYB_OFFSET 0x00600000 +#define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00600000 +#define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET 0x00680000 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00680400 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00680800 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00680c00 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00681000 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00681400 +#define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET 0x00684000 +#define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET 0x00688000 +#define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET 0x00700000 +#define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET 0x00720000 +#define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET 0x00728000 +#define SEQ_WCSS_PHYB_WFAX_DEMFRONT_NPRB_B_REG_MAP_OFFSET 0x00730000 +#define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET 0x007a0000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_OFFSET 0x007c0000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET 0x007c0000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OTP_OFFSET 0x007c0000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_TLMM_OFFSET 0x007c4000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x007c8000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x007d4000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x007d4000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x007d4400 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x007d4800 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x007d6000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x007d6040 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x007d6080 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x007d60e0 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x007d6100 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x007d6140 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x007d6180 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x007d6800 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x007d6840 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x007d6880 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x007d68e0 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x007d6900 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x007d6940 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x007d6980 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x007e0000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x007e0000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x007e0400 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x007e0800 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x007e1000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x007e1200 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x007e2000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x007e8000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x007e8400 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x007e8800 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x007e9000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x007e9200 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x007ea000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x007f0000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x007f0400 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x007f0800 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET 0x007f1000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET 0x007f1200 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x007f2000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x007f8000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x007f8400 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x007f8800 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET 0x007f9000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET 0x007f9200 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x007fa000 #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET 0x00a00000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000 @@ -171,156 +250,10 @@ #define SEQ_WCSS_WMAC1_MAC_SFM_REG_OFFSET 0x00af3000 #define SEQ_WCSS_WMAC1_MAC_RXDMA1_REG_OFFSET 0x00af6000 #define SEQ_WCSS_WMAC1_MAC_LPEC_REG_OFFSET 0x00af9000 -#define SEQ_WCSS_WMAC2_OFFSET 0x00b00000 -#define SEQ_WCSS_WMAC2_MAC_PDG_REG_OFFSET 0x00b00000 -#define SEQ_WCSS_WMAC2_MAC_TXDMA_REG_OFFSET 0x00b03000 -#define SEQ_WCSS_WMAC2_MAC_RXDMA_REG_OFFSET 0x00b06000 -#define SEQ_WCSS_WMAC2_MAC_MCMN_REG_OFFSET 0x00b09000 -#define SEQ_WCSS_WMAC2_MAC_RXPCU_REG_OFFSET 0x00b0c000 -#define SEQ_WCSS_WMAC2_MAC_TXPCU_REG_OFFSET 0x00b0f000 -#define SEQ_WCSS_WMAC2_MAC_AMPI_REG_OFFSET 0x00b12000 -#define SEQ_WCSS_WMAC2_MAC_RXOLE_REG_OFFSET 0x00b15000 -#define SEQ_WCSS_WMAC2_MAC_RXOLE_PARSER_REG_OFFSET 0x00b18000 -#define SEQ_WCSS_WMAC2_MAC_CCE_REG_OFFSET 0x00b1b000 -#define SEQ_WCSS_WMAC2_MAC_TXOLE_REG_OFFSET 0x00b1e000 -#define SEQ_WCSS_WMAC2_MAC_TXOLE_PARSER_REG_OFFSET 0x00b21000 -#define SEQ_WCSS_WMAC2_MAC_RRI_REG_OFFSET 0x00b24000 -#define SEQ_WCSS_WMAC2_MAC_CRYPTO_REG_OFFSET 0x00b27000 -#define SEQ_WCSS_WMAC2_MAC_HWSCH_REG_OFFSET 0x00b2a000 -#define SEQ_WCSS_WMAC2_MAC_MXI_REG_OFFSET 0x00b30000 -#define SEQ_WCSS_WMAC2_MAC_SFM_REG_OFFSET 0x00b33000 -#define SEQ_WCSS_WMAC2_MAC_RXDMA1_REG_OFFSET 0x00b36000 -#define SEQ_WCSS_WMAC2_MAC_LPEC_REG_OFFSET 0x00b39000 #define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 #define SEQ_WCSS_WCMN_OFFSET 0x00b50000 #define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 #define SEQ_WCSS_PMM_OFFSET 0x00b70000 -#define SEQ_WCSS_ZINC_RFA_CMN_OFFSET 0x00b80000 -#define SEQ_WCSS_ZINC_RFA_CMN_PLL_A_OFFSET 0x00b80000 -#define SEQ_WCSS_ZINC_RFA_CMN_BIASCLKS_A_OFFSET 0x00b80100 -#define SEQ_WCSS_ZINC_RFA_CMN_PLL_B_OFFSET 0x00b82000 -#define SEQ_WCSS_ZINC_RFA_CMN_BIASCLKS_B_OFFSET 0x00b82100 -#define SEQ_WCSS_ZINC_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET 0x00b84000 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET 0x00b88000 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET 0x00b88100 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET 0x00b88200 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET 0x00b88300 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET 0x00b88400 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET 0x00b88440 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET 0x00b88480 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH0_OFFSET 0x00b884c0 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH0_OFFSET 0x00b88500 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET 0x00b88600 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET 0x00b88800 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET 0x00b88900 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET 0x00b88a00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET 0x00b88b00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET 0x00b88c00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET 0x00b88c40 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET 0x00b88c80 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH1_OFFSET 0x00b88cc0 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH1_OFFSET 0x00b88d00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET 0x00b88e00 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET 0x00b89000 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET 0x00b89100 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET 0x00b89200 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET 0x00b89300 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET 0x00b89400 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET 0x00b89440 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET 0x00b89480 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH2_OFFSET 0x00b894c0 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH2_OFFSET 0x00b89500 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET 0x00b89600 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET 0x00b89800 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET 0x00b89900 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET 0x00b89a00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET 0x00b89b00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET 0x00b89c00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET 0x00b89c40 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET 0x00b89c80 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH3_OFFSET 0x00b89cc0 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH3_OFFSET 0x00b89d00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET 0x00b89e00 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET 0x00b8a000 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET 0x00b8a100 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET 0x00b8a200 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET 0x00b8a300 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET 0x00b8a400 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET 0x00b8a440 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET 0x00b8a480 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH0_OFFSET 0x00b8a4c0 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH0_OFFSET 0x00b8a500 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET 0x00b8a600 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET 0x00b8a800 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET 0x00b8a900 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET 0x00b8aa00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET 0x00b8ab00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET 0x00b8ac00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET 0x00b8ac40 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET 0x00b8ac80 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH1_OFFSET 0x00b8acc0 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH1_OFFSET 0x00b8ad00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET 0x00b8ae00 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET 0x00b8b000 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET 0x00b8b100 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET 0x00b8b200 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET 0x00b8b300 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET 0x00b8b400 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET 0x00b8b440 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET 0x00b8b480 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH2_OFFSET 0x00b8b4c0 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH2_OFFSET 0x00b8b500 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET 0x00b8b600 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET 0x00b8b800 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET 0x00b8b900 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET 0x00b8ba00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET 0x00b8bb00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET 0x00b8bc00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET 0x00b8bc40 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET 0x00b8bc80 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH3_OFFSET 0x00b8bcc0 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH3_OFFSET 0x00b8bd00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET 0x00b8be00 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET 0x00b8c000 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET 0x00b8c100 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET 0x00b8c200 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET 0x00b8c300 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET 0x00b8c400 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET 0x00b8c440 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET 0x00b8c480 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH0_OFFSET 0x00b8c4c0 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH0_OFFSET 0x00b8c500 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET 0x00b8c600 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET 0x00b8c800 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET 0x00b8c900 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET 0x00b8ca00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET 0x00b8cb00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET 0x00b8cc00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET 0x00b8cc40 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET 0x00b8cc80 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH1_OFFSET 0x00b8ccc0 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH1_OFFSET 0x00b8cd00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET 0x00b8ce00 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET 0x00b8d000 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET 0x00b8d100 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET 0x00b8d200 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET 0x00b8d300 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET 0x00b8d400 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET 0x00b8d440 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET 0x00b8d480 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH2_OFFSET 0x00b8d4c0 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH2_OFFSET 0x00b8d500 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET 0x00b8d600 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET 0x00b8d800 -#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET 0x00b8d900 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET 0x00b8da00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET 0x00b8db00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET 0x00b8dc00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET 0x00b8dc40 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET 0x00b8dc80 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH3_OFFSET 0x00b8dcc0 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH3_OFFSET 0x00b8dd00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH3_OFFSET 0x00b8de00 #define SEQ_WCSS_DBG_OFFSET 0x00b90000 #define SEQ_WCSS_DBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00b90000 #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 @@ -342,18 +275,16 @@ #define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00bb1000 #define SEQ_WCSS_DBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00bb6000 #define SEQ_WCSS_DBG_PHYA_CPU0_AHB_AP_OFFSET 0x00bbe000 -#define SEQ_WCSS_DBG_PHYA_CPU1_AHB_AP_OFFSET 0x00bbf000 #define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc0000 #define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00bc1000 #define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00bc6000 #define SEQ_WCSS_DBG_PHYB_CPU0_AHB_AP_OFFSET 0x00bce000 #define SEQ_WCSS_DBG_UMAC_CPU_AHB_AP_OFFSET 0x00bf0000 +#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00bf1000 #define SEQ_WCSS_RET_AHB_OFFSET 0x00c10000 #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00c20000 #define SEQ_WCSS_CC_OFFSET 0x00c30000 #define SEQ_WCSS_ACMT_OFFSET 0x00c40000 -#define SEQ_WCSS_WRAPPER_ACMT_OFFSET 0x00c60000 -#define SEQ_WCSS_WRAPPER_ACMT_WRAPPER_ACMT_OFFSET 0x00c60000 #define SEQ_WCSS_Q6SS_PUBCSR_OFFSET 0x00d00000 #define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET 0x00d00000 #define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET 0x00d80000 @@ -382,8 +313,171 @@ #define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00100000 #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x00120000 #define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x00128000 -#define SEQ_WFAX_TOP_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00130000 +#define SEQ_WFAX_TOP_WFAX_DEMFRONT_NPRA_REG_MAP_OFFSET 0x00130000 #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x001a0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x001c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_OFFSET 0x001c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_OTP_OFFSET 0x001c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_TLMM_OFFSET 0x001c4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x001c8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x001d4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x001d6080 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d60e0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d6100 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6140 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6180 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x001d6880 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d68e0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d6900 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6940 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6980 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x001e0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x001e0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x001e0400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x001e0800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x001e1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x001e1200 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x001e2000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x001e8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x001e8400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x001e8800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x001e9000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x001e9200 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x001ea000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x001f0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x001f0400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x001f0800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET 0x001f1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET 0x001f1200 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x001f2000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x001f8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x001f8400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x001f8800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET 0x001f9000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET 0x001f9200 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x001fa000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block iron2g +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_IRON2G_RFA_DIG_OFFSET 0x00000000 +#define SEQ_IRON2G_RFA_DIG_OTP_OFFSET 0x00000000 +#define SEQ_IRON2G_RFA_DIG_TLMM_OFFSET 0x00004000 +#define SEQ_IRON2G_RFA_DIG_SYSCTRL_OFFSET 0x00008000 +#define SEQ_IRON2G_RFA_CMN_OFFSET 0x00014000 +#define SEQ_IRON2G_RFA_CMN_AON_OFFSET 0x00014000 +#define SEQ_IRON2G_RFA_CMN_CLKGEN_OFFSET 0x00014400 +#define SEQ_IRON2G_RFA_CMN_RFFE_M_OFFSET 0x00014800 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x00016080 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x000160e0 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016100 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016140 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00016180 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00016800 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00016840 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x00016880 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x000168e0 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00016900 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016940 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00016980 +#define SEQ_IRON2G_RFA_WL_OFFSET 0x00020000 +#define SEQ_IRON2G_RFA_WL_WL_MC_CH0_OFFSET 0x00020000 +#define SEQ_IRON2G_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400 +#define SEQ_IRON2G_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800 +#define SEQ_IRON2G_RFA_WL_WL_TXFE_CH0_OFFSET 0x00021000 +#define SEQ_IRON2G_RFA_WL_WL_RXFE_CH0_OFFSET 0x00021200 +#define SEQ_IRON2G_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000 +#define SEQ_IRON2G_RFA_WL_WL_MC_CH1_OFFSET 0x00028000 +#define SEQ_IRON2G_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400 +#define SEQ_IRON2G_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800 +#define SEQ_IRON2G_RFA_WL_WL_TXFE_CH1_OFFSET 0x00029000 +#define SEQ_IRON2G_RFA_WL_WL_RXFE_CH1_OFFSET 0x00029200 +#define SEQ_IRON2G_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000 +#define SEQ_IRON2G_RFA_WL_WL_MC_CH2_OFFSET 0x00030000 +#define SEQ_IRON2G_RFA_WL_WL_RXBB_CH2_OFFSET 0x00030400 +#define SEQ_IRON2G_RFA_WL_WL_TXBB_CH2_OFFSET 0x00030800 +#define SEQ_IRON2G_RFA_WL_WL_TXFE_CH2_OFFSET 0x00031000 +#define SEQ_IRON2G_RFA_WL_WL_RXFE_CH2_OFFSET 0x00031200 +#define SEQ_IRON2G_RFA_WL_WL_TPC_CH2_OFFSET 0x00032000 +#define SEQ_IRON2G_RFA_WL_WL_MC_CH3_OFFSET 0x00038000 +#define SEQ_IRON2G_RFA_WL_WL_RXBB_CH3_OFFSET 0x00038400 +#define SEQ_IRON2G_RFA_WL_WL_TXBB_CH3_OFFSET 0x00038800 +#define SEQ_IRON2G_RFA_WL_WL_TXFE_CH3_OFFSET 0x00039000 +#define SEQ_IRON2G_RFA_WL_WL_RXFE_CH3_OFFSET 0x00039200 +#define SEQ_IRON2G_RFA_WL_WL_TPC_CH3_OFFSET 0x0003a000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block rfa_dig +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_RFA_DIG_OTP_OFFSET 0x00000000 +#define SEQ_RFA_DIG_TLMM_OFFSET 0x00004000 +#define SEQ_RFA_DIG_SYSCTRL_OFFSET 0x00008000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block rfa_cmn +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_RFA_CMN_AON_OFFSET 0x00000000 +#define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000400 +#define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000800 +#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 +#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 +#define SEQ_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x00002080 +#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x000020e0 +#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002100 +#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002140 +#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00002180 +#define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00002800 +#define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00002840 +#define SEQ_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x00002880 +#define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x000028e0 +#define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00002900 +#define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002940 +#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00002980 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block rfa_wl +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000 +#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400 +#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800 +#define SEQ_RFA_WL_WL_TXFE_CH0_OFFSET 0x00001000 +#define SEQ_RFA_WL_WL_RXFE_CH0_OFFSET 0x00001200 +#define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000 +#define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000 +#define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400 +#define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800 +#define SEQ_RFA_WL_WL_TXFE_CH1_OFFSET 0x00009000 +#define SEQ_RFA_WL_WL_RXFE_CH1_OFFSET 0x00009200 +#define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000 +#define SEQ_RFA_WL_WL_MC_CH2_OFFSET 0x00010000 +#define SEQ_RFA_WL_WL_RXBB_CH2_OFFSET 0x00010400 +#define SEQ_RFA_WL_WL_TXBB_CH2_OFFSET 0x00010800 +#define SEQ_RFA_WL_WL_TXFE_CH2_OFFSET 0x00011000 +#define SEQ_RFA_WL_WL_RXFE_CH2_OFFSET 0x00011200 +#define SEQ_RFA_WL_WL_TPC_CH2_OFFSET 0x00012000 +#define SEQ_RFA_WL_WL_MC_CH3_OFFSET 0x00018000 +#define SEQ_RFA_WL_WL_RXBB_CH3_OFFSET 0x00018400 +#define SEQ_RFA_WL_WL_TXBB_CH3_OFFSET 0x00018800 +#define SEQ_RFA_WL_WL_TXFE_CH3_OFFSET 0x00019000 +#define SEQ_RFA_WL_WL_RXFE_CH3_OFFSET 0x00019200 +#define SEQ_RFA_WL_WL_TPC_CH3_OFFSET 0x0001a000 /////////////////////////////////////////////////////////////////////////////////////////////// @@ -402,8 +496,56 @@ #define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET 0x00100000 #define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET 0x00120000 #define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET 0x00128000 -#define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00130000 +#define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_NPRB_B_REG_MAP_OFFSET 0x00130000 #define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET 0x001a0000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_OFFSET 0x001c0000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET 0x001c0000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OTP_OFFSET 0x001c0000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_TLMM_OFFSET 0x001c4000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x001c8000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x001d4000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4400 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4800 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x001d6080 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d60e0 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d6100 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6140 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6180 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x001d6880 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d68e0 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d6900 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6940 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6980 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x001e0000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x001e0000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x001e0400 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x001e0800 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x001e1000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x001e1200 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x001e2000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x001e8000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x001e8400 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x001e8800 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x001e9000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x001e9200 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x001ea000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x001f0000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x001f0400 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x001f0800 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET 0x001f1000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET 0x001f1200 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x001f2000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x001f8000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x001f8400 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x001f8800 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET 0x001f9000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET 0x001f9200 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x001fa000 /////////////////////////////////////////////////////////////////////////////////////////////// @@ -485,203 +627,91 @@ /////////////////////////////////////////////////////////////////////////////////////////////// -// Instance Relative Offsets from Block cxc_top_reg_14lpp +// Instance Relative Offsets from Block cxc_top_reg /////////////////////////////////////////////////////////////////////////////////////////////// -#define SEQ_CXC_TOP_REG_14LPP_CXC_BMH_REG_OFFSET 0x00000000 -#define SEQ_CXC_TOP_REG_14LPP_CXC_LCMH_REG_OFFSET 0x00002000 -#define SEQ_CXC_TOP_REG_14LPP_CXC_MCIBASIC_REG_OFFSET 0x00004000 -#define SEQ_CXC_TOP_REG_14LPP_CXC_LMH_REG_OFFSET 0x00006000 -#define SEQ_CXC_TOP_REG_14LPP_CXC_SMH_REG_OFFSET 0x00008000 -#define SEQ_CXC_TOP_REG_14LPP_CXC_PMH_REG_OFFSET 0x0000a000 +#define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 +#define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 +#define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 +#define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 +#define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 +#define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 /////////////////////////////////////////////////////////////////////////////////////////////// -// Instance Relative Offsets from Block wmac_top_reg +// Instance Relative Offsets from Block wmac_top_reg_28lp /////////////////////////////////////////////////////////////////////////////////////////////// -#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 -#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 -#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 -#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 -#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 -#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 -#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 -#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 -#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 -#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 -#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 -#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 -#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 -#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 -#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 -#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 -#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 -#define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET 0x00036000 -#define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET 0x00039000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_PDG_REG_OFFSET 0x00000000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_TXDMA_REG_OFFSET 0x00003000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA_REG_OFFSET 0x00006000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_MCMN_REG_OFFSET 0x00009000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_RXPCU_REG_OFFSET 0x0000c000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_TXPCU_REG_OFFSET 0x0000f000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_AMPI_REG_OFFSET 0x00012000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_RXOLE_REG_OFFSET 0x00015000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_CCE_REG_OFFSET 0x0001b000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_TXOLE_REG_OFFSET 0x0001e000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_RRI_REG_OFFSET 0x00024000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_CRYPTO_REG_OFFSET 0x00027000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_HWSCH_REG_OFFSET 0x0002a000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_MXI_REG_OFFSET 0x00030000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_SFM_REG_OFFSET 0x00033000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA1_REG_OFFSET 0x00036000 +#define SEQ_WMAC_TOP_REG_28LP_MAC_LPEC_REG_OFFSET 0x00039000 +#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_PDG_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_TXDMA_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_MCMN_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXPCU_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_TXPCU_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_AMPI_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXOLE_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXOLE_PARSER_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_CCE_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_TXOLE_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_TXOLE_PARSER_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RRI_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_CRYPTO_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_HWSCH_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_MXI_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_SFM_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA1_REG_OFFSET +#define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_LPEC_REG_OFFSET /////////////////////////////////////////////////////////////////////////////////////////////// -// Instance Relative Offsets from Block rfa_cmn +// Instance Relative Offsets from Block wcssdbg_napier /////////////////////////////////////////////////////////////////////////////////////////////// -#define SEQ_RFA_CMN_PLL_A_OFFSET 0x00000000 -#define SEQ_RFA_CMN_BIASCLKS_A_OFFSET 0x00000100 -#define SEQ_RFA_CMN_PLL_B_OFFSET 0x00002000 -#define SEQ_RFA_CMN_BIASCLKS_B_OFFSET 0x00002100 -#define SEQ_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET 0x00004000 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET 0x00008000 -#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET 0x00008100 -#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET 0x00008200 -#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET 0x00008300 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET 0x00008400 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET 0x00008440 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET 0x00008480 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH0_OFFSET 0x000084c0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH0_OFFSET 0x00008500 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET 0x00008600 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET 0x00008800 -#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET 0x00008900 -#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET 0x00008a00 -#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET 0x00008b00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET 0x00008c00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET 0x00008c40 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET 0x00008c80 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH1_OFFSET 0x00008cc0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH1_OFFSET 0x00008d00 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET 0x00008e00 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET 0x00009000 -#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET 0x00009100 -#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET 0x00009200 -#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET 0x00009300 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET 0x00009400 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET 0x00009440 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET 0x00009480 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH2_OFFSET 0x000094c0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH2_OFFSET 0x00009500 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET 0x00009600 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET 0x00009800 -#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET 0x00009900 -#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET 0x00009a00 -#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET 0x00009b00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET 0x00009c00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET 0x00009c40 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET 0x00009c80 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH3_OFFSET 0x00009cc0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH3_OFFSET 0x00009d00 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET 0x00009e00 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET 0x0000a000 -#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET 0x0000a100 -#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET 0x0000a200 -#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET 0x0000a300 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET 0x0000a400 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET 0x0000a440 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET 0x0000a480 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH0_OFFSET 0x0000a4c0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH0_OFFSET 0x0000a500 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET 0x0000a600 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET 0x0000a800 -#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET 0x0000a900 -#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET 0x0000aa00 -#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET 0x0000ab00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET 0x0000ac00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET 0x0000ac40 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET 0x0000ac80 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH1_OFFSET 0x0000acc0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH1_OFFSET 0x0000ad00 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET 0x0000ae00 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET 0x0000b000 -#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET 0x0000b100 -#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET 0x0000b200 -#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET 0x0000b300 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET 0x0000b400 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET 0x0000b440 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET 0x0000b480 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH2_OFFSET 0x0000b4c0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH2_OFFSET 0x0000b500 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET 0x0000b600 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET 0x0000b800 -#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET 0x0000b900 -#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET 0x0000ba00 -#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET 0x0000bb00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET 0x0000bc00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET 0x0000bc40 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET 0x0000bc80 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH3_OFFSET 0x0000bcc0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH3_OFFSET 0x0000bd00 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET 0x0000be00 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET 0x0000c000 -#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET 0x0000c100 -#define SEQ_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET 0x0000c200 -#define SEQ_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET 0x0000c300 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET 0x0000c400 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET 0x0000c440 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET 0x0000c480 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH0_OFFSET 0x0000c4c0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH0_OFFSET 0x0000c500 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET 0x0000c600 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET 0x0000c800 -#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET 0x0000c900 -#define SEQ_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET 0x0000ca00 -#define SEQ_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET 0x0000cb00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET 0x0000cc00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET 0x0000cc40 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET 0x0000cc80 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH1_OFFSET 0x0000ccc0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH1_OFFSET 0x0000cd00 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET 0x0000ce00 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET 0x0000d000 -#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET 0x0000d100 -#define SEQ_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET 0x0000d200 -#define SEQ_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET 0x0000d300 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET 0x0000d400 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET 0x0000d440 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET 0x0000d480 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH2_OFFSET 0x0000d4c0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH2_OFFSET 0x0000d500 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET 0x0000d600 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET 0x0000d800 -#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET 0x0000d900 -#define SEQ_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET 0x0000da00 -#define SEQ_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET 0x0000db00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET 0x0000dc00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET 0x0000dc40 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET 0x0000dc80 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH3_OFFSET 0x0000dcc0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH3_OFFSET 0x0000dd00 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH3_OFFSET 0x0000de00 - - -/////////////////////////////////////////////////////////////////////////////////////////////// -// Instance Relative Offsets from Block wcssdbg -/////////////////////////////////////////////////////////////////////////////////////////////// - -#define SEQ_WCSSDBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00000000 -#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 -#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 -#define SEQ_WCSSDBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00004000 -#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 -#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 -#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00008000 -#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00008280 -#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00008000 -#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00009000 -#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00009280 -#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00009000 -#define SEQ_WCSSDBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x0000a000 -#define SEQ_WCSSDBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x0000b000 -#define SEQ_WCSSDBG_TMC_CXTMC_F128W8K_OFFSET 0x0000c000 -#define SEQ_WCSSDBG_UMAC_NOC_UMAC_NOC_OFFSET 0x00010000 -#define SEQ_WCSSDBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00020000 -#define SEQ_WCSSDBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00021000 -#define SEQ_WCSSDBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00026000 -#define SEQ_WCSSDBG_PHYA_CPU0_AHB_AP_OFFSET 0x0002e000 -#define SEQ_WCSSDBG_PHYA_CPU1_AHB_AP_OFFSET 0x0002f000 -#define SEQ_WCSSDBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00030000 -#define SEQ_WCSSDBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00031000 -#define SEQ_WCSSDBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00036000 -#define SEQ_WCSSDBG_PHYB_CPU0_AHB_AP_OFFSET 0x0003e000 -#define SEQ_WCSSDBG_UMAC_CPU_AHB_AP_OFFSET 0x00060000 +#define SEQ_WCSSDBG_NAPIER_ROM_WCSS_DBG_DAPROM_OFFSET 0x00000000 +#define SEQ_WCSSDBG_NAPIER_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 +#define SEQ_WCSSDBG_NAPIER_TSGEN_CXTSGEN_OFFSET 0x00002000 +#define SEQ_WCSSDBG_NAPIER_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00004000 +#define SEQ_WCSSDBG_NAPIER_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 +#define SEQ_WCSSDBG_NAPIER_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 +#define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00008000 +#define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00008280 +#define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00008000 +#define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00009000 +#define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00009280 +#define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00009000 +#define SEQ_WCSSDBG_NAPIER_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x0000a000 +#define SEQ_WCSSDBG_NAPIER_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x0000b000 +#define SEQ_WCSSDBG_NAPIER_TMC_CXTMC_F128W8K_OFFSET 0x0000c000 +#define SEQ_WCSSDBG_NAPIER_UMAC_NOC_UMAC_NOC_OFFSET 0x00010000 +#define SEQ_WCSSDBG_NAPIER_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00020000 +#define SEQ_WCSSDBG_NAPIER_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00021000 +#define SEQ_WCSSDBG_NAPIER_PHYA_NOC_PHYA_NOC_OFFSET 0x00026000 +#define SEQ_WCSSDBG_NAPIER_PHYA_CPU0_AHB_AP_OFFSET 0x0002e000 +#define SEQ_WCSSDBG_NAPIER_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00030000 +#define SEQ_WCSSDBG_NAPIER_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00031000 +#define SEQ_WCSSDBG_NAPIER_PHYB_NOC_PHYB_NOC_OFFSET 0x00036000 +#define SEQ_WCSSDBG_NAPIER_PHYB_CPU0_AHB_AP_OFFSET 0x0003e000 +#define SEQ_WCSSDBG_NAPIER_UMAC_CPU_AHB_AP_OFFSET 0x00060000 +#define SEQ_WCSSDBG_NAPIER_BUS_TIMEOUT_OFFSET 0x00061000 /////////////////////////////////////////////////////////////////////////////////////////////// @@ -700,13 +730,6 @@ #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00000000 -/////////////////////////////////////////////////////////////////////////////////////////////// -// Instance Relative Offsets from Block wrapper_acmt -/////////////////////////////////////////////////////////////////////////////////////////////// - -#define SEQ_WRAPPER_ACMT_WRAPPER_ACMT_OFFSET 0x00000000 - - /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block qdsp6ss_public /////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/hw/qca6290/v1/wfss_ce_reg_seq_hwiobase.h b/hw/qca6290/v1/wfss_ce_reg_seq_hwiobase.h index a27a10d8aa..b642ee0505 100644 --- a/hw/qca6290/v1/wfss_ce_reg_seq_hwiobase.h +++ b/hw/qca6290/v1/wfss_ce_reg_seq_hwiobase.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -18,8 +18,8 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// wfss_ce_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 -// User Name:pgohil +// wfss_ce_reg_seq_hwiobase.h : automatically generated by Autoseq 3.1 9/30/2016 +// User Name:kanalas // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. // diff --git a/hw/qca6290/v1/wfss_ce_reg_seq_hwioreg.h b/hw/qca6290/v1/wfss_ce_reg_seq_hwioreg.h index b66ae4fffd..7324d6ca21 100644 --- a/hw/qca6290/v1/wfss_ce_reg_seq_hwioreg.h +++ b/hw/qca6290/v1/wfss_ce_reg_seq_hwioreg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -18,8 +18,8 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// wfss_ce_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 -// User Name:pgohil +// wfss_ce_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 9/30/2016 +// User Name:kanalas // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. // @@ -92,7 +92,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) (x+0x00000008) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) (x+0x00000008) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0x000000ff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) @@ -107,9 +107,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -301,7 +298,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -316,7 +313,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER //// @@ -439,7 +436,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) @@ -454,7 +451,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB //// @@ -695,7 +692,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000084) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000084) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) @@ -710,7 +707,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB //// @@ -786,7 +783,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000ac) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000ac) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) @@ -801,7 +798,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_CTRL //// @@ -1041,7 +1038,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) (x+0x00000008) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) (x+0x00000008) -#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0x000000ff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) @@ -1056,9 +1053,6 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RING_ID_SHFT 0x8 - #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -1250,7 +1244,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c) -#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) @@ -1265,7 +1259,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER //// @@ -1388,7 +1382,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054) -#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) @@ -1403,7 +1397,7 @@ HWIO_INTFREE();\ } while (0) -#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL //// @@ -2188,6 +2182,28 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_BMSK 0x00000fff #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_SHFT 0x0 +//// Register WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x) (x+0x00000064) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_PHYS(x) (x+0x00000064) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_VALUE_SHFT 0x0 + //// Register WFSS_CE_COMMON_R1_TESTBUS_CTRL //// #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x) (x+0x00000400) diff --git a/hw/qca6290/v1/wfss_pmm_base_struct.h b/hw/qca6290/v1/wfss_pmm_base_struct.h index f8ef472127..4f9ffd0343 100644 --- a/hw/qca6290/v1/wfss_pmm_base_struct.h +++ b/hw/qca6290/v1/wfss_pmm_base_struct.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the