Merge "disp: msm: sde: select vbif QOS LUT based on ddr type"

msm/sde/sde_hw_catalog.c

@@ -221,6 +221,7 @@ enum sde_prop {
 	MACROTILE_MODE,
 	UBWC_BW_CALC_VERSION,
 	PIPE_ORDER_VERSION,
+	DDR_TYPE,
 	SEC_SID_MASK,
 	BASE_LAYER,
 	TRUSTED_VM_ENV,
@@ -632,6 +633,7 @@ static struct sde_prop_type sde_prop[] = {
 			PROP_TYPE_U32},
 	{PIPE_ORDER_VERSION, "qcom,sde-pipe-order-version", false,
 			PROP_TYPE_U32},
+	{DDR_TYPE, "qcom,sde-ddr-type", false, PROP_TYPE_U32_ARRAY},
 	{SEC_SID_MASK, "qcom,sde-secure-sid-mask", false, PROP_TYPE_U32_ARRAY},
 	{BASE_LAYER, "qcom,sde-mixer-stage-base-layer", false, PROP_TYPE_BOOL},
 	{TRUSTED_VM_ENV, "qcom,sde-trusted-vm-env", false, PROP_TYPE_BOOL},
@@ -3793,29 +3795,29 @@ static int _sde_vbif_populate_qos_parsing(struct sde_mdss_cfg *sde_cfg,
 {
 	int i, j, prop_index = VBIF_QOS_RT_REMAP;
 	u32 entries;
+	u32 ddr_list_index;
 
 	for (i = VBIF_RT_CLIENT; ((i < VBIF_MAX_CLIENT) && (prop_index < VBIF_PROP_MAX));
 						i++, prop_index++) {
-		vbif->qos_tbl[i].count = prop_count[prop_index];
-		SDE_DEBUG("qos_tbl[%d].count=%u\n", i, vbif->qos_tbl[i].count);
-
 		entries = 2 * sde_cfg->vbif_qos_nlvl;
-		if (vbif->qos_tbl[i].count == entries) {
-			vbif->qos_tbl[i].priority_lvl = kcalloc(entries, sizeof(u32), GFP_KERNEL);
-			if (!vbif->qos_tbl[i].priority_lvl) {
-				vbif->qos_tbl[i].count = 0;
-				return -ENOMEM;
-			}
-		} else if (vbif->qos_tbl[i].count) {
+		vbif->qos_tbl[i].count = prop_count[prop_index];
+
+		ddr_list_index = (vbif->qos_tbl[i].count == entries) ?
+					0 : sde_cfg->ddr_list_index;
+
+		SDE_DEBUG("qos_tbl[%d].count=%u, ddr_list_index=%u\n",
+				i, vbif->qos_tbl[i].count, ddr_list_index);
+
+		vbif->qos_tbl[i].priority_lvl = kcalloc(entries, sizeof(u32), GFP_KERNEL);
+		if (!vbif->qos_tbl[i].priority_lvl) {
 			vbif->qos_tbl[i].count = 0;
-			vbif->qos_tbl[i].priority_lvl = NULL;
-			SDE_ERROR("invalid qos table for client:%d, prop:%d\n", i, prop_index);
-			continue;
+			return -ENOMEM;
 		}
 
-		for (j = 0; j < vbif->qos_tbl[i].count; j++) {
+		for (j = 0; j < entries; j++) {
 			vbif->qos_tbl[i].priority_lvl[j] =
-					PROP_VALUE_ACCESS(prop_value, prop_index, j);
+					PROP_VALUE_ACCESS(prop_value, prop_index,
+					entries * ddr_list_index + j);
 			SDE_DEBUG("client:%d, prop:%d, lvl[%d]=%u\n", i, prop_index, j,
 					vbif->qos_tbl[i].priority_lvl[j]);
 		}
@@ -4185,6 +4187,16 @@ static void _sde_top_parse_dt_helper(struct sde_mdss_cfg *cfg,
 	if (!cfg->ipcc_protocol_id || !cfg->ipcc_client_phys_id)
 		cfg->hw_fence_rev = 0; /* disable hw fences*/
 
+	if (props->exists[DDR_TYPE]) {
+		for (i = 0; i < props->counts[DDR_TYPE]; i++) {
+			ddr_type = PROP_VALUE_ACCESS(props->values, DDR_TYPE, i);
+			if (ddr_type == of_fdt_get_ddrtype()) {
+				cfg->ddr_list_index = i;
+				break;
+			}
+		}
+	}
+
 	if (props->exists[SEC_SID_MASK]) {
 		cfg->sec_sid_mask_count = props->counts[SEC_SID_MASK];
 		for (i = 0; i < cfg->sec_sid_mask_count; i++)

msm/sde/sde_hw_catalog.h

@@ -1960,7 +1960,8 @@ struct sde_perf_cfg {
  * @max_dsc_width       max dsc line width
  * @max_mixer_width     max layer mixer line width
  * @max_mixer_blendstages       max layer mixer blend stages (z orders)
- * @max_cwb             max number of dcwb/cwb supported
+ * @max_cwb             max number of cwb supported
+ * @ddr_list_index      index of supported ddr type
  * @vbif_qos_nlvl       number of vbif QoS priority levels
  * @qos_target_time_ns  normalized qos target time for line-based qos
  * @macrotile_mode      UBWC parameter for macro tile channel distribution
@@ -2112,6 +2113,7 @@ struct sde_mdss_cfg {
 
 	enum sde_ppb_size_option ppb_sz_program;
 	u32 ppb_buf_max_lines;
+	u32 ddr_list_index;
 };
 
 struct sde_mdss_hw_cfg_handler {