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Merge "Video Driver: fix frame freeze for HEVC 10bit all intra decoding"

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This commit is contained in:
qctecmdr
2022-11-11 13:15:33 -08:00
committed by Gerrit - the friendly Code Review server
parent fe64bbf604 b35fde25c4
commit b1bf3f1148
19 changed files with 88 additions and 171 deletions
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26
driver/platform/anorak/src/msm_vidc_anorak.c
View File

@@ -207,32 +207,6 @@ static struct msm_platform_inst_capability instance_cap_data_anorak[] = {
{SECURE_MBPF, ENC, HEVC, 36, 36864, 1, 36864}, {SECURE_MBPF, ENC, HEVC, 36, 36864, 1, 36864},
/* ((1920 * 1088) / 256) * 480 fps */
{MBPS, ENC, CODECS_ALL, 64, 3916800, 1, 3916800},
{MBPS, ENC, HEVC, 36, 3916800, 1, 3916800},
/* ((16384x16384)/256)@1fps */
{MBPS, ENC, HEIC, 36, 1048576, 1, 1048576},
/* ((3840 * 2176) / 256) * 240 fps */
{MBPS, DEC, CODECS_ALL, 64, 7833600, 1, 7833600},
/* ((4096 * 2304) / 256) * 120 */
{MBPS, DEC, VP9, 36, 4423680, 1, 4423680},
/* ((8192x8192)/256)@1fps */
{MBPS, DEC, HEIC, 64, 262144, 1, 262144 },
/* ((4096 * 2304) / 256) * 60 fps */
{POWER_SAVE_MBPS, ENC, CODECS_ALL, 0, 2211840, 1, 2211840},
/* Enable check mbps for encoder */
{CHECK_MBPS, ENC, CODECS_ALL, 0, 1, 1, 1},
/* Disable check mbps for encoder */
{CHECK_MBPS, DEC, CODECS_ALL, 0, 1, 1, 0},
{FRAME_RATE, ENC, CODECS_ALL, {FRAME_RATE, ENC, CODECS_ALL,
(MINIMUM_FPS << 16), (MAXIMUM_FPS << 16), (MINIMUM_FPS << 16), (MAXIMUM_FPS << 16),
1, (DEFAULT_FPS << 16), 1, (DEFAULT_FPS << 16),

17
driver/platform/kalama/src/kalama.c
View File

@@ -298,23 +298,6 @@ static struct msm_platform_inst_capability instance_cap_data_kalama[] = {
/* (4096 * 2304) / 256 */ /* (4096 * 2304) / 256 */
{BATCH_FPS, DEC, H264|HEVC|VP9, 1, 120, 1, 120}, {BATCH_FPS, DEC, H264|HEVC|VP9, 1, 120, 1, 120},
/* ((1920 * 1088) / 256) * 480 fps */
{MBPS, ENC, CODECS_ALL, 64, 3916800, 1, 3916800},
{MBPS, ENC, HEVC, 36, 3916800, 1, 3916800},
/* ((1920 * 1088) / 256) * 960 fps */
{MBPS, DEC, CODECS_ALL, 64, 7833600, 1, 7833600},
/* ((4096 * 2304) / 256) * 120 */
{MBPS, DEC, VP9, 36, 4423680, 1, 4423680},
/* Enable check mbps for encoder */
{CHECK_MBPS, ENC, CODECS_ALL, 0, 1, 1, 1},
/* Disable check mbps for encoder */
{CHECK_MBPS, DEC, CODECS_ALL, 0, 1, 1, 0},
{FRAME_RATE, ENC, CODECS_ALL, {FRAME_RATE, ENC, CODECS_ALL,
(MINIMUM_FPS << 16), (MAXIMUM_FPS << 16), (MINIMUM_FPS << 16), (MAXIMUM_FPS << 16),
1, (DEFAULT_FPS << 16), 1, (DEFAULT_FPS << 16),

34
driver/platform/kalama/src/msm_vidc_kalama.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#include <dt-bindings/clock/qcom,gcc-kalama.h> #include <dt-bindings/clock/qcom,gcc-kalama.h>
@@ -445,32 +445,6 @@ static struct msm_platform_inst_capability instance_cap_data_kalama[] = {
{SECURE_MBPF, ENC, HEVC, 36, 36864, 1, 36864}, {SECURE_MBPF, ENC, HEVC, 36, 36864, 1, 36864},
/* ((1920 * 1088) / 256) * 480 fps */
{MBPS, ENC, CODECS_ALL, 64, 3916800, 1, 3916800},
{MBPS, ENC, HEVC, 36, 3916800, 1, 3916800},
/* ((16384x16384)/256)@1fps */
{MBPS, ENC, HEIC, 36, 1048576, 1, 1048576},
/* ((1920 * 1088) / 256) * 960 fps */
{MBPS, DEC, CODECS_ALL, 64, 7833600, 1, 7833600},
/* ((4096 * 2304) / 256) * 120 */
{MBPS, DEC, VP9, 36, 4423680, 1, 4423680},
/* ((8192x8192)/256)@1fps */
{MBPS, DEC, HEIC, 64, 262144, 1, 262144 },
/* ((4096 * 2304) / 256) * 60 fps */
{POWER_SAVE_MBPS, ENC, CODECS_ALL, 0, 2211840, 1, 2211840},
/* Enable check mbps for encoder */
{CHECK_MBPS, ENC, CODECS_ALL, 0, 1, 1, 1},
/* Disable check mbps for encoder */
{CHECK_MBPS, DEC, CODECS_ALL, 0, 1, 1, 0},
{FRAME_RATE, ENC, CODECS_ALL, {FRAME_RATE, ENC, CODECS_ALL,
(MINIMUM_FPS << 16), (MAXIMUM_FPS << 16), (MINIMUM_FPS << 16), (MAXIMUM_FPS << 16),
1, (DEFAULT_FPS << 16), 1, (DEFAULT_FPS << 16),
@@ -1281,7 +1255,7 @@ static struct msm_platform_inst_capability instance_cap_data_kalama[] = {
{LEVEL, ENC, HEVC|HEIC, {LEVEL, ENC, HEVC|HEIC,
V4L2_MPEG_VIDEO_HEVC_LEVEL_1, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_6, V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
@@ -1292,7 +1266,9 @@ static struct msm_platform_inst_capability instance_cap_data_kalama[] = {
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6), BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
V4L2_MPEG_VIDEO_HEVC_LEVEL_5, V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
HFI_PROP_LEVEL, HFI_PROP_LEVEL,

32
driver/platform/pineapple/src/msm_vidc_pineapple.c
View File

@@ -445,32 +445,6 @@ static struct msm_platform_inst_capability instance_cap_data_pineapple[] = {
{SECURE_MBPF, ENC, HEVC, 36, 36864, 1, 36864}, {SECURE_MBPF, ENC, HEVC, 36, 36864, 1, 36864},
/* ((1920 * 1088) / 256) * 480 fps */
{MBPS, ENC, CODECS_ALL, 64, 3916800, 1, 3916800},
{MBPS, ENC, HEVC, 36, 3916800, 1, 3916800},
/* ((16384x16384)/256)@1fps */
{MBPS, ENC, HEIC, 36, 1048576, 1, 1048576},
/* ((1920 * 1088) / 256) * 960 fps */
{MBPS, DEC, CODECS_ALL, 64, 7833600, 1, 7833600},
/* ((4096 * 2304) / 256) * 120 */
{MBPS, DEC, VP9, 36, 4423680, 1, 4423680},
/* ((8192x8192)/256)@1fps */
{MBPS, DEC, HEIC, 64, 262144, 1, 262144 },
/* ((4096 * 2304) / 256) * 60 fps */
{POWER_SAVE_MBPS, ENC, CODECS_ALL, 0, 2211840, 1, 2211840},
/* Enable check mbps for encoder */
{CHECK_MBPS, ENC, CODECS_ALL, 0, 1, 1, 1},
/* Disable check mbps for encoder */
{CHECK_MBPS, DEC, CODECS_ALL, 0, 1, 1, 0},
{FRAME_RATE, ENC, CODECS_ALL, {FRAME_RATE, ENC, CODECS_ALL,
(MINIMUM_FPS << 16), (MAXIMUM_FPS << 16), (MINIMUM_FPS << 16), (MAXIMUM_FPS << 16),
1, (DEFAULT_FPS << 16), 1, (DEFAULT_FPS << 16),
@@ -1281,7 +1255,7 @@ static struct msm_platform_inst_capability instance_cap_data_pineapple[] = {
{LEVEL, ENC, HEVC|HEIC, {LEVEL, ENC, HEVC|HEIC,
V4L2_MPEG_VIDEO_HEVC_LEVEL_1, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
V4L2_MPEG_VIDEO_HEVC_LEVEL_6, V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
@@ -1292,7 +1266,9 @@ static struct msm_platform_inst_capability instance_cap_data_pineapple[] = {
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6), BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
V4L2_MPEG_VIDEO_HEVC_LEVEL_5, V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
HFI_PROP_LEVEL, HFI_PROP_LEVEL,

17
driver/platform/pineapple/src/pineapple.c
View File

@@ -300,23 +300,6 @@ static struct msm_platform_inst_capability instance_cap_data_pineapple[] = {
/* (4096 * 2304) / 256 */ /* (4096 * 2304) / 256 */
{BATCH_FPS, DEC, H264|HEVC|VP9, 1, 120, 1, 120}, {BATCH_FPS, DEC, H264|HEVC|VP9, 1, 120, 1, 120},
/* ((1920 * 1088) / 256) * 480 fps */
{MBPS, ENC, CODECS_ALL, 64, 3916800, 1, 3916800},
{MBPS, ENC, HEVC, 36, 3916800, 1, 3916800},
/* ((1920 * 1088) / 256) * 960 fps */
{MBPS, DEC, CODECS_ALL, 64, 7833600, 1, 7833600},
/* ((4096 * 2304) / 256) * 120 */
{MBPS, DEC, VP9, 36, 4423680, 1, 4423680},
/* Enable check mbps for encoder */
{CHECK_MBPS, ENC, CODECS_ALL, 0, 1, 1, 1},
/* Disable check mbps for encoder */
{CHECK_MBPS, DEC, CODECS_ALL, 0, 1, 1, 0},
{FRAME_RATE, ENC, CODECS_ALL, {FRAME_RATE, ENC, CODECS_ALL,
(MINIMUM_FPS << 16), (MAXIMUM_FPS << 16), (MINIMUM_FPS << 16), (MAXIMUM_FPS << 16),
1, (DEFAULT_FPS << 16), 1, (DEFAULT_FPS << 16),

26
driver/platform/waipio/src/msm_vidc_waipio.c
View File

@@ -204,32 +204,6 @@ static struct msm_platform_inst_capability instance_cap_data_waipio[] = {
{SECURE_MBPF, ENC, HEVC, 36, 36864, 1, 36864}, {SECURE_MBPF, ENC, HEVC, 36, 36864, 1, 36864},
/* ((1920 * 1088) / 256) * 480 fps */
{MBPS, ENC, CODECS_ALL, 64, 3916800, 1, 3916800},
{MBPS, ENC, HEVC, 36, 3916800, 1, 3916800},
/* ((16384x16384)/256)@1fps */
{MBPS, ENC, HEIC, 36, 1048576, 1, 1048576},
/* ((1920 * 1088) / 256) * 960 fps */
{MBPS, DEC, CODECS_ALL, 64, 7833600, 1, 7833600},
/* ((4096 * 2304) / 256) * 120 */
{MBPS, DEC, VP9, 36, 4423680, 1, 4423680},
/* ((8192x8192)/256)@1fps */
{MBPS, DEC, HEIC, 64, 262144, 1, 262144 },
/* ((4096 * 2304) / 256) * 60 fps */
{POWER_SAVE_MBPS, ENC, CODECS_ALL, 0, 2211840, 1, 2211840},
/* Enable check mbps for encoder */
{CHECK_MBPS, ENC, CODECS_ALL, 0, 1, 1, 1},
/* Disable check mbps for encoder */
{CHECK_MBPS, DEC, CODECS_ALL, 0, 1, 1, 0},
{FRAME_RATE, ENC, CODECS_ALL, {FRAME_RATE, ENC, CODECS_ALL,
(MINIMUM_FPS << 16), (MAXIMUM_FPS << 16), (MINIMUM_FPS << 16), (MAXIMUM_FPS << 16),
1, (DEFAULT_FPS << 16), 1, (DEFAULT_FPS << 16),

15
driver/variant/iris3/src/msm_vidc_iris3.c
View File

@@ -274,19 +274,22 @@ static int __power_off_iris3_hardware(struct msm_vidc_core *core)
bool pwr_collapsed = false; bool pwr_collapsed = false;
/* /*
* Incase hw power control is enabled, when CPU WD occurred, check for power * Incase hw power control is enabled, for both CPU WD, video
* status to decide on executing NOC reset sequence before disabling power. * hw unresponsive cases, check for power status to decide on
* If there is no CPU WD and hw_power_control is enabled, fw is expected * executing NOC reset sequence before disabling power. If there
* is no CPU WD and hw_power_control is enabled, fw is expected
* to power collapse video hw always. * to power collapse video hw always.
*/ */
if (core->hw_power_control) { if (core->hw_power_control) {
pwr_collapsed = is_iris3_hw_power_collapsed(core); pwr_collapsed = is_iris3_hw_power_collapsed(core);
if (core->cpu_watchdog) { if (core->cpu_watchdog || core->video_unresponsive) {
if (pwr_collapsed) { if (pwr_collapsed) {
d_vpr_e("%s: CPU WD and video hw power collapsed\n", __func__); d_vpr_e("%s: video hw power collapsed %d, %d\n",
__func__, core->cpu_watchdog, core->video_unresponsive);
goto disable_power; goto disable_power;
} else { } else {
d_vpr_e("%s: CPU WD and video hw is power ON\n", __func__); d_vpr_e("%s: video hw is power ON %d, %d\n",
__func__, core->cpu_watchdog, core->video_unresponsive);
} }
} else { } else {
if (!pwr_collapsed) if (!pwr_collapsed)

16
driver/variant/iris3/src/msm_vidc_power_iris3.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#include "msm_vidc_power_iris3.h" #include "msm_vidc_power_iris3.h"
@@ -213,6 +213,11 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
if (fps >= 960) if (fps >= 960)
vsp_cycles += div_u64(vpp_cycles * 25, 100); vsp_cycles += div_u64(vpp_cycles * 25, 100);
/* Add 25 percent extra for HEVC 10bit all intra use case */
if (inst->iframe && is_hevc_10bit_decode_session(inst)) {
vsp_cycles += div_u64(vsp_cycles * 25, 100);
}
if (inst->codec == MSM_VIDC_VP9 && if (inst->codec == MSM_VIDC_VP9 &&
inst->capabilities->cap[STAGE].value == inst->capabilities->cap[STAGE].value ==
MSM_VIDC_STAGE_2 && MSM_VIDC_STAGE_2 &&
@@ -228,11 +233,14 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
freq = max(vpp_cycles, vsp_cycles); freq = max(vpp_cycles, vsp_cycles);
freq = max(freq, fw_cycles); freq = max(freq, fw_cycles);
if (inst->codec != MSM_VIDC_AV1) { if (inst->codec == MSM_VIDC_AV1 ||
(inst->iframe && is_hevc_10bit_decode_session(inst))) {
/* /*
* for non-AV1 codecs limit the frequency to NOM only * for AV1 or HEVC 10bit and iframe case only allow TURBO and
* index 0 is TURBO, index 1 is NOM clock rate * limit to NOM for all other cases
*/ */
} else {
/* limit to NOM, index 0 is TURBO, index 1 is NOM clock rate */
if (core->resource->freq_set.count >= 2 && if (core->resource->freq_set.count >= 2 &&
freq > core->resource->freq_set.freq_tbl[1].freq) freq > core->resource->freq_set.freq_tbl[1].freq)
freq = core->resource->freq_set.freq_tbl[1].freq; freq = core->resource->freq_set.freq_tbl[1].freq;

15
driver/variant/iris33/src/msm_vidc_iris33.c
View File

@@ -277,19 +277,22 @@ static int __power_off_iris33_hardware(struct msm_vidc_core *core)
bool pwr_collapsed = false; bool pwr_collapsed = false;
/* /*
* Incase hw power control is enabled, when CPU WD occurred, check for power * Incase hw power control is enabled, for both CPU WD, video
* status to decide on executing NOC reset sequence before disabling power. * hw unresponsive cases, check for power status to decide on
* If there is no CPU WD and hw_power_control is enabled, fw is expected * executing NOC reset sequence before disabling power. If there
* is no CPU WD and hw_power_control is enabled, fw is expected
* to power collapse video hw always. * to power collapse video hw always.
*/ */
if (core->hw_power_control) { if (core->hw_power_control) {
pwr_collapsed = is_iris33_hw_power_collapsed(core); pwr_collapsed = is_iris33_hw_power_collapsed(core);
if (core->cpu_watchdog) { if (core->cpu_watchdog || core->video_unresponsive) {
if (pwr_collapsed) { if (pwr_collapsed) {
d_vpr_e("%s: CPU WD and video hw power collapsed\n", __func__); d_vpr_e("%s: video hw power collapsed %d, %d\n",
__func__, core->cpu_watchdog, core->video_unresponsive);
goto disable_power; goto disable_power;
} else { } else {
d_vpr_e("%s: CPU WD and video hw is power ON\n", __func__); d_vpr_e("%s: video hw is power ON %d, %d\n",
__func__, core->cpu_watchdog, core->video_unresponsive);
} }
} else { } else {
if (!pwr_collapsed) if (!pwr_collapsed)

14
driver/variant/iris33/src/msm_vidc_power_iris33.c
View File

@@ -212,6 +212,11 @@ u64 msm_vidc_calc_freq_iris33(struct msm_vidc_inst *inst, u32 data_size)
if (fps >= 960) if (fps >= 960)
vsp_cycles += div_u64(vpp_cycles * 25, 100); vsp_cycles += div_u64(vpp_cycles * 25, 100);
/* Add 25 percent extra for HEVC 10bit all intra use case */
if (inst->iframe && is_hevc_10bit_decode_session(inst)) {
vsp_cycles += div_u64(vsp_cycles * 25, 100);
}
if (inst->codec == MSM_VIDC_VP9 && if (inst->codec == MSM_VIDC_VP9 &&
inst->capabilities->cap[STAGE].value == inst->capabilities->cap[STAGE].value ==
MSM_VIDC_STAGE_2 && MSM_VIDC_STAGE_2 &&
@@ -227,11 +232,14 @@ u64 msm_vidc_calc_freq_iris33(struct msm_vidc_inst *inst, u32 data_size)
freq = max(vpp_cycles, vsp_cycles); freq = max(vpp_cycles, vsp_cycles);
freq = max(freq, fw_cycles); freq = max(freq, fw_cycles);
if (inst->codec != MSM_VIDC_AV1) { if (inst->codec == MSM_VIDC_AV1 ||
(inst->iframe && is_hevc_10bit_decode_session(inst))) {
/* /*
* for non-AV1 codecs limit the frequency to NOM only * for AV1 or HEVC 10bit and iframe case only allow TURBO and
* index 0 is TURBO, index 1 is NOM clock rate * limit to NOM for all other cases
*/ */
} else {
/* limit to NOM, index 0 is TURBO, index 1 is NOM clock rate */
if (core->resource->freq_set.count >= 2 && if (core->resource->freq_set.count >= 2 &&
freq > core->resource->freq_set.freq_tbl[1].freq) freq > core->resource->freq_set.freq_tbl[1].freq)
freq = core->resource->freq_set.freq_tbl[1].freq; freq = core->resource->freq_set.freq_tbl[1].freq;

4
driver/vidc/inc/msm_vidc_core.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2020-2021,, The Linux Foundation. All rights reserved. * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#ifndef _MSM_VIDC_CORE_H_ #ifndef _MSM_VIDC_CORE_H_
@@ -118,6 +119,7 @@ struct msm_vidc_core {
bool hw_power_control; bool hw_power_control;
bool pm_suspended; bool pm_suspended;
bool cpu_watchdog; bool cpu_watchdog;
bool video_unresponsive;
}; };
#endif // _MSM_VIDC_CORE_H_ #endif // _MSM_VIDC_CORE_H_

2
driver/vidc/inc/msm_vidc_driver.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2020-2021,, The Linux Foundation. All rights reserved. * Copyright (c) 2020-2021,, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#ifndef _MSM_VIDC_DRIVER_H_ #ifndef _MSM_VIDC_DRIVER_H_
@@ -577,6 +578,7 @@ bool res_is_less_than(u32 width, u32 height,
u32 ref_width, u32 ref_height); u32 ref_width, u32 ref_height);
bool res_is_less_than_or_equal_to(u32 width, u32 height, bool res_is_less_than_or_equal_to(u32 width, u32 height,
u32 ref_width, u32 ref_height); u32 ref_width, u32 ref_height);
bool is_hevc_10bit_decode_session(struct msm_vidc_inst *inst);
int signal_session_msg_receipt(struct msm_vidc_inst *inst, int signal_session_msg_receipt(struct msm_vidc_inst *inst,
enum signal_session_response cmd); enum signal_session_response cmd);
int msm_vidc_get_properties(struct msm_vidc_inst *inst); int msm_vidc_get_properties(struct msm_vidc_inst *inst);

1
driver/vidc/inc/msm_vidc_inst.h
View File

@@ -181,5 +181,6 @@ struct msm_vidc_inst {
bool has_bframe; bool has_bframe;
bool ir_enabled; bool ir_enabled;
u32 adjust_priority; u32 adjust_priority;
bool iframe;
}; };
#endif // _MSM_VIDC_INST_H_ #endif // _MSM_VIDC_INST_H_

6
driver/vidc/inc/msm_vidc_internal.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2020-2021,, The Linux Foundation. All rights reserved. * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#ifndef _MSM_VIDC_INTERNAL_H_ #ifndef _MSM_VIDC_INTERNAL_H_
@@ -437,9 +438,6 @@ enum msm_vidc_inst_capability_type {
BATCH_FPS, BATCH_FPS,
LOSSLESS_MBPF, LOSSLESS_MBPF,
SECURE_MBPF, SECURE_MBPF,
MBPS,
POWER_SAVE_MBPS,
CHECK_MBPS,
FRAME_RATE, FRAME_RATE,
OPERATING_RATE, OPERATING_RATE,
INPUT_RATE, INPUT_RATE,

1
driver/vidc/src/msm_vidc.c
View File

@@ -901,6 +901,7 @@ void *msm_vidc_open(void *vidc_core, u32 session_type)
inst->ipsc_properties_set = false; inst->ipsc_properties_set = false;
inst->opsc_properties_set = false; inst->opsc_properties_set = false;
inst->has_bframe = false; inst->has_bframe = false;
inst->iframe = false;
inst->auto_framerate = DEFAULT_FPS << 16; inst->auto_framerate = DEFAULT_FPS << 16;
inst->initial_time_us = ktime_get_ns() / 1000; inst->initial_time_us = ktime_get_ns() / 1000;
kref_init(&inst->kref); kref_init(&inst->kref);

2
driver/vidc/src/msm_vidc_control.c
View File

@@ -3104,7 +3104,7 @@ int msm_vidc_set_header_mode(void *instance,
else else
hfi_value = HFI_SEQ_HEADER_SEPERATE_FRAME; hfi_value = HFI_SEQ_HEADER_SEPERATE_FRAME;
if (is_meta_rx_inp_enabled(inst, META_SEQ_HDR_NAL)) if (is_meta_rx_out_enabled(inst, META_SEQ_HDR_NAL))
hfi_value |= HFI_SEQ_HEADER_METADATA; hfi_value |= HFI_SEQ_HEADER_METADATA;
rc = msm_vidc_packetize_control(inst, cap_id, HFI_PAYLOAD_U32_ENUM, rc = msm_vidc_packetize_control(inst, cap_id, HFI_PAYLOAD_U32_ENUM,

23
driver/vidc/src/msm_vidc_driver.c
View File

@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2020-2022, The Linux Foundation. All rights reserved. * Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#include <linux/iommu.h> #include <linux/iommu.h>
@@ -97,9 +98,6 @@ static const struct msm_vidc_cap_name cap_name_arr[] = {
{BATCH_FPS, "BATCH_FPS" }, {BATCH_FPS, "BATCH_FPS" },
{LOSSLESS_MBPF, "LOSSLESS_MBPF" }, {LOSSLESS_MBPF, "LOSSLESS_MBPF" },
{SECURE_MBPF, "SECURE_MBPF" }, {SECURE_MBPF, "SECURE_MBPF" },
{MBPS, "MBPS" },
{POWER_SAVE_MBPS, "POWER_SAVE_MBPS" },
{CHECK_MBPS, "CHECK_MPBS" },
{FRAME_RATE, "FRAME_RATE" }, {FRAME_RATE, "FRAME_RATE" },
{OPERATING_RATE, "OPERATING_RATE" }, {OPERATING_RATE, "OPERATING_RATE" },
{INPUT_RATE, "INPUT_RATE" }, {INPUT_RATE, "INPUT_RATE" },
@@ -1800,6 +1798,22 @@ bool msm_vidc_allow_psc_last_flag(struct msm_vidc_inst *inst)
return false; return false;
} }
bool is_hevc_10bit_decode_session(struct msm_vidc_inst *inst)
{
bool is10bit = false;
enum msm_vidc_colorformat_type colorformat;
colorformat = v4l2_colorformat_to_driver(inst,
inst->fmts[OUTPUT_PORT].fmt.pix_mp.pixelformat, __func__);
if (colorformat == MSM_VIDC_FMT_TP10C || colorformat == MSM_VIDC_FMT_P010)
is10bit = true;
return inst->domain == MSM_VIDC_DECODER &&
inst->codec == MSM_VIDC_HEVC &&
is10bit;
}
int msm_vidc_state_change_streamon(struct msm_vidc_inst *inst, int msm_vidc_state_change_streamon(struct msm_vidc_inst *inst,
enum msm_vidc_port_type port) enum msm_vidc_port_type port)
{ {
@@ -4945,6 +4959,7 @@ int msm_vidc_core_init_wait(struct msm_vidc_core *core)
} else { } else {
d_vpr_h("%s: sys init wait timedout. state %s\n", d_vpr_h("%s: sys init wait timedout. state %s\n",
__func__, core_state_name(core->state)); __func__, core_state_name(core->state));
core->video_unresponsive = true;
rc = -EINVAL; rc = -EINVAL;
goto unlock; goto unlock;
} }
@@ -5019,6 +5034,8 @@ int msm_vidc_inst_timeout(struct msm_vidc_inst *inst)
rc = -EINVAL; rc = -EINVAL;
goto unlock; goto unlock;
} }
/* mark video hw unresponsive */
core->video_unresponsive = true;
/* call core deinit for a valid instance timeout case */ /* call core deinit for a valid instance timeout case */
msm_vidc_core_deinit_locked(core, true); msm_vidc_core_deinit_locked(core, true);

3
driver/vidc/src/venus_hfi.c
View File

@@ -687,6 +687,7 @@ int __load_fw(struct msm_vidc_core *core)
core->handoff_done = false; core->handoff_done = false;
core->hw_power_control = false; core->hw_power_control = false;
core->cpu_watchdog = false; core->cpu_watchdog = false;
core->video_unresponsive = false;
trace_msm_v4l2_vidc_fw_load("START"); trace_msm_v4l2_vidc_fw_load("START");
rc = __venus_power_on(core); rc = __venus_power_on(core);
@@ -726,6 +727,7 @@ void __unload_fw(struct msm_vidc_core *core)
__venus_power_off(core); __venus_power_off(core);
core->cpu_watchdog = false; core->cpu_watchdog = false;
core->video_unresponsive = false;
d_vpr_h("%s done\n", __func__); d_vpr_h("%s done\n", __func__);
} }
@@ -815,6 +817,7 @@ void venus_hfi_pm_work_handler(struct work_struct *work)
d_vpr_e("Failed to PC for %d times\n", d_vpr_e("Failed to PC for %d times\n",
core->skip_pc_count); core->skip_pc_count);
core->skip_pc_count = 0; core->skip_pc_count = 0;
core->video_unresponsive = true;
msm_vidc_core_deinit(core, true); msm_vidc_core_deinit(core, true);
return; return;
} }

5
driver/vidc/src/venus_hfi_response.c
View File

@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#include <linux/devcoredump.h> #include <linux/devcoredump.h>
@@ -1661,6 +1662,10 @@ static int handle_property_with_payload(struct msm_vidc_inst *inst,
inst->hfi_frame_info.picture_type = payload_ptr[0]; inst->hfi_frame_info.picture_type = payload_ptr[0];
if (inst->hfi_frame_info.picture_type & HFI_PICTURE_B) if (inst->hfi_frame_info.picture_type & HFI_PICTURE_B)
inst->has_bframe = true; inst->has_bframe = true;
if (inst->hfi_frame_info.picture_type & HFI_PICTURE_IDR)
inst->iframe = true;
else
inst->iframe = false;
break; break;
case HFI_PROP_SUBFRAME_INPUT: case HFI_PROP_SUBFRAME_INPUT:
if (port != INPUT_PORT) { if (port != INPUT_PORT) {