Merge "Video Driver: fix frame freeze for HEVC 10bit all intra decoding"

driver/platform/anorak/src/msm_vidc_anorak.c

@@ -207,32 +207,6 @@ static struct msm_platform_inst_capability instance_cap_data_anorak[] = {
 
 	{SECURE_MBPF, ENC, HEVC, 36, 36864, 1, 36864},
 
-	/* ((1920 * 1088) / 256) * 480 fps */
-	{MBPS, ENC, CODECS_ALL, 64, 3916800, 1, 3916800},
-
-	{MBPS, ENC, HEVC, 36, 3916800, 1, 3916800},
-
-	/* ((16384x16384)/256)@1fps */
-	{MBPS, ENC, HEIC, 36, 1048576, 1, 1048576},
-
-	/* ((3840 * 2176) / 256) * 240 fps */
-	{MBPS, DEC, CODECS_ALL, 64, 7833600, 1, 7833600},
-
-	/* ((4096 * 2304) / 256) * 120 */
-	{MBPS, DEC, VP9, 36, 4423680, 1, 4423680},
-
-	/* ((8192x8192)/256)@1fps */
-	{MBPS, DEC, HEIC, 64, 262144,  1, 262144 },
-
-	/* ((4096 * 2304) / 256) * 60 fps */
-	{POWER_SAVE_MBPS, ENC, CODECS_ALL, 0, 2211840, 1, 2211840},
-
-	/* Enable check mbps for encoder */
-	{CHECK_MBPS, ENC, CODECS_ALL, 0, 1, 1, 1},
-
-	/* Disable check mbps for encoder */
-	{CHECK_MBPS, DEC, CODECS_ALL, 0, 1, 1, 0},
-
 	{FRAME_RATE, ENC, CODECS_ALL,
 		(MINIMUM_FPS << 16), (MAXIMUM_FPS << 16),
 		1, (DEFAULT_FPS << 16),

driver/platform/kalama/src/kalama.c

@@ -298,23 +298,6 @@ static struct msm_platform_inst_capability instance_cap_data_kalama[] = {
 	/* (4096 * 2304) / 256 */
 	{BATCH_FPS, DEC, H264|HEVC|VP9, 1, 120, 1, 120},
 
-	/* ((1920 * 1088) / 256) * 480 fps */
-	{MBPS, ENC, CODECS_ALL, 64, 3916800, 1, 3916800},
-
-	{MBPS, ENC, HEVC, 36, 3916800, 1, 3916800},
-
-	/* ((1920 * 1088) / 256) * 960 fps */
-	{MBPS, DEC, CODECS_ALL, 64, 7833600, 1, 7833600},
-
-	/* ((4096 * 2304) / 256) * 120 */
-	{MBPS, DEC, VP9, 36, 4423680, 1, 4423680},
-
-	/* Enable check mbps for encoder */
-	{CHECK_MBPS, ENC, CODECS_ALL, 0, 1, 1, 1},
-
-	/* Disable check mbps for encoder */
-	{CHECK_MBPS, DEC, CODECS_ALL, 0, 1, 1, 0},
-
 	{FRAME_RATE, ENC, CODECS_ALL,
 		(MINIMUM_FPS << 16), (MAXIMUM_FPS << 16),
 		1, (DEFAULT_FPS << 16),

driver/platform/kalama/src/msm_vidc_kalama.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/clock/qcom,gcc-kalama.h>
@@ -445,32 +445,6 @@ static struct msm_platform_inst_capability instance_cap_data_kalama[] = {
 
 	{SECURE_MBPF, ENC, HEVC, 36, 36864, 1, 36864},
 
-	/* ((1920 * 1088) / 256) * 480 fps */
-	{MBPS, ENC, CODECS_ALL, 64, 3916800, 1, 3916800},
-
-	{MBPS, ENC, HEVC, 36, 3916800, 1, 3916800},
-
-	/* ((16384x16384)/256)@1fps */
-	{MBPS, ENC, HEIC, 36, 1048576, 1, 1048576},
-
-	/* ((1920 * 1088) / 256) * 960 fps */
-	{MBPS, DEC, CODECS_ALL, 64, 7833600, 1, 7833600},
-
-	/* ((4096 * 2304) / 256) * 120 */
-	{MBPS, DEC, VP9, 36, 4423680, 1, 4423680},
-
-	/* ((8192x8192)/256)@1fps */
-	{MBPS, DEC, HEIC, 64, 262144,  1, 262144 },
-
-	/* ((4096 * 2304) / 256) * 60 fps */
-	{POWER_SAVE_MBPS, ENC, CODECS_ALL, 0, 2211840, 1, 2211840},
-
-	/* Enable check mbps for encoder */
-	{CHECK_MBPS, ENC, CODECS_ALL, 0, 1, 1, 1},
-
-	/* Disable check mbps for encoder */
-	{CHECK_MBPS, DEC, CODECS_ALL, 0, 1, 1, 0},
-
 	{FRAME_RATE, ENC, CODECS_ALL,
 		(MINIMUM_FPS << 16), (MAXIMUM_FPS << 16),
 		1, (DEFAULT_FPS << 16),
@@ -1281,7 +1255,7 @@ static struct msm_platform_inst_capability instance_cap_data_kalama[] = {
 
 	{LEVEL, ENC, HEVC|HEIC,
 		V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
-		V4L2_MPEG_VIDEO_HEVC_LEVEL_6,
+		V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
 		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
 		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
 		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
@@ -1292,7 +1266,9 @@ static struct msm_platform_inst_capability instance_cap_data_kalama[] = {
 		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
 		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
 		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
-		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6),
+		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
+		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
+		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
 		V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
 		V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
 		HFI_PROP_LEVEL,

driver/platform/pineapple/src/msm_vidc_pineapple.c

@@ -445,32 +445,6 @@ static struct msm_platform_inst_capability instance_cap_data_pineapple[] = {
 
 	{SECURE_MBPF, ENC, HEVC, 36, 36864, 1, 36864},
 
-	/* ((1920 * 1088) / 256) * 480 fps */
-	{MBPS, ENC, CODECS_ALL, 64, 3916800, 1, 3916800},
-
-	{MBPS, ENC, HEVC, 36, 3916800, 1, 3916800},
-
-	/* ((16384x16384)/256)@1fps */
-	{MBPS, ENC, HEIC, 36, 1048576, 1, 1048576},
-
-	/* ((1920 * 1088) / 256) * 960 fps */
-	{MBPS, DEC, CODECS_ALL, 64, 7833600, 1, 7833600},
-
-	/* ((4096 * 2304) / 256) * 120 */
-	{MBPS, DEC, VP9, 36, 4423680, 1, 4423680},
-
-	/* ((8192x8192)/256)@1fps */
-	{MBPS, DEC, HEIC, 64, 262144,  1, 262144 },
-
-	/* ((4096 * 2304) / 256) * 60 fps */
-	{POWER_SAVE_MBPS, ENC, CODECS_ALL, 0, 2211840, 1, 2211840},
-
-	/* Enable check mbps for encoder */
-	{CHECK_MBPS, ENC, CODECS_ALL, 0, 1, 1, 1},
-
-	/* Disable check mbps for encoder */
-	{CHECK_MBPS, DEC, CODECS_ALL, 0, 1, 1, 0},
-
 	{FRAME_RATE, ENC, CODECS_ALL,
 		(MINIMUM_FPS << 16), (MAXIMUM_FPS << 16),
 		1, (DEFAULT_FPS << 16),
@@ -1281,7 +1255,7 @@ static struct msm_platform_inst_capability instance_cap_data_pineapple[] = {
 
 	{LEVEL, ENC, HEVC|HEIC,
 		V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
-		V4L2_MPEG_VIDEO_HEVC_LEVEL_6,
+		V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
 		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
 		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
 		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
@@ -1292,7 +1266,9 @@ static struct msm_platform_inst_capability instance_cap_data_pineapple[] = {
 		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
 		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
 		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
-		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6),
+		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
+		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
+		BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
 		V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
 		V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
 		HFI_PROP_LEVEL,

driver/platform/pineapple/src/pineapple.c

@@ -300,23 +300,6 @@ static struct msm_platform_inst_capability instance_cap_data_pineapple[] = {
 	/* (4096 * 2304) / 256 */
 	{BATCH_FPS, DEC, H264|HEVC|VP9, 1, 120, 1, 120},
 
-	/* ((1920 * 1088) / 256) * 480 fps */
-	{MBPS, ENC, CODECS_ALL, 64, 3916800, 1, 3916800},
-
-	{MBPS, ENC, HEVC, 36, 3916800, 1, 3916800},
-
-	/* ((1920 * 1088) / 256) * 960 fps */
-	{MBPS, DEC, CODECS_ALL, 64, 7833600, 1, 7833600},
-
-	/* ((4096 * 2304) / 256) * 120 */
-	{MBPS, DEC, VP9, 36, 4423680, 1, 4423680},
-
-	/* Enable check mbps for encoder */
-	{CHECK_MBPS, ENC, CODECS_ALL, 0, 1, 1, 1},
-
-	/* Disable check mbps for encoder */
-	{CHECK_MBPS, DEC, CODECS_ALL, 0, 1, 1, 0},
-
 	{FRAME_RATE, ENC, CODECS_ALL,
 		(MINIMUM_FPS << 16), (MAXIMUM_FPS << 16),
 		1, (DEFAULT_FPS << 16),

driver/platform/waipio/src/msm_vidc_waipio.c

@@ -204,32 +204,6 @@ static struct msm_platform_inst_capability instance_cap_data_waipio[] = {
 
 	{SECURE_MBPF, ENC, HEVC, 36, 36864, 1, 36864},
 
-	/* ((1920 * 1088) / 256) * 480 fps */
-	{MBPS, ENC, CODECS_ALL, 64, 3916800, 1, 3916800},
-
-	{MBPS, ENC, HEVC, 36, 3916800, 1, 3916800},
-
-	/* ((16384x16384)/256)@1fps */
-	{MBPS, ENC, HEIC, 36, 1048576, 1, 1048576},
-
-	/* ((1920 * 1088) / 256) * 960 fps */
-	{MBPS, DEC, CODECS_ALL, 64, 7833600, 1, 7833600},
-
-	/* ((4096 * 2304) / 256) * 120 */
-	{MBPS, DEC, VP9, 36, 4423680, 1, 4423680},
-
-	/* ((8192x8192)/256)@1fps */
-	{MBPS, DEC, HEIC, 64, 262144,  1, 262144 },
-
-	/* ((4096 * 2304) / 256) * 60 fps */
-	{POWER_SAVE_MBPS, ENC, CODECS_ALL, 0, 2211840, 1, 2211840},
-
-	/* Enable check mbps for encoder */
-	{CHECK_MBPS, ENC, CODECS_ALL, 0, 1, 1, 1},
-
-	/* Disable check mbps for encoder */
-	{CHECK_MBPS, DEC, CODECS_ALL, 0, 1, 1, 0},
-
 	{FRAME_RATE, ENC, CODECS_ALL,
 		(MINIMUM_FPS << 16), (MAXIMUM_FPS << 16),
 		1, (DEFAULT_FPS << 16),

driver/variant/iris3/src/msm_vidc_iris3.c

@@ -274,19 +274,22 @@ static int __power_off_iris3_hardware(struct msm_vidc_core *core)
 	bool pwr_collapsed = false;
 
 	/*
-	 * Incase hw power control is enabled, when CPU WD occurred, check for power
-	 * status to decide on executing NOC reset sequence before disabling power.
-	 * If there is no CPU WD and hw_power_control is enabled, fw is expected
+	 * Incase hw power control is enabled, for both CPU WD, video
+	 * hw unresponsive cases, check for power status to decide on
+	 * executing NOC reset sequence before disabling power. If there
+	 * is no CPU WD and hw_power_control is enabled, fw is expected
 	 * to power collapse video hw always.
 	 */
 	if (core->hw_power_control) {
 		pwr_collapsed = is_iris3_hw_power_collapsed(core);
-		if (core->cpu_watchdog) {
+		if (core->cpu_watchdog || core->video_unresponsive) {
 			if (pwr_collapsed) {
-				d_vpr_e("%s: CPU WD and video hw power collapsed\n", __func__);
+				d_vpr_e("%s: video hw power collapsed %d, %d\n",
+					__func__, core->cpu_watchdog, core->video_unresponsive);
 				goto disable_power;
 			} else {
-				d_vpr_e("%s: CPU WD and video hw is power ON\n", __func__);
+				d_vpr_e("%s: video hw is power ON %d, %d\n",
+					__func__, core->cpu_watchdog, core->video_unresponsive);
 			}
 		} else {
 			if (!pwr_collapsed)

driver/variant/iris3/src/msm_vidc_power_iris3.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include "msm_vidc_power_iris3.h"
@@ -213,6 +213,11 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
 			if (fps >= 960)
 				vsp_cycles += div_u64(vpp_cycles * 25, 100);
 
+			/* Add 25 percent extra for HEVC 10bit all intra use case */
+			if (inst->iframe && is_hevc_10bit_decode_session(inst)) {
+				vsp_cycles += div_u64(vsp_cycles * 25, 100);
+			}
+
 			if (inst->codec == MSM_VIDC_VP9 &&
 					inst->capabilities->cap[STAGE].value ==
 						MSM_VIDC_STAGE_2 &&
@@ -228,11 +233,14 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
 	freq = max(vpp_cycles, vsp_cycles);
 	freq = max(freq, fw_cycles);
 
-	if (inst->codec != MSM_VIDC_AV1) {
+	if (inst->codec == MSM_VIDC_AV1 ||
+		(inst->iframe && is_hevc_10bit_decode_session(inst))) {
 		/*
-		 * for non-AV1 codecs limit the frequency to NOM only
-		 * index 0 is TURBO, index 1 is NOM clock rate
+		 * for AV1 or HEVC 10bit and iframe case only allow TURBO and
+		 * limit to NOM for all other cases
 		 */
+	} else {
+		/* limit to NOM, index 0 is TURBO, index 1 is NOM clock rate */
 		if (core->resource->freq_set.count >= 2 &&
 		    freq > core->resource->freq_set.freq_tbl[1].freq)
 			freq = core->resource->freq_set.freq_tbl[1].freq;

driver/variant/iris33/src/msm_vidc_iris33.c

@@ -277,19 +277,22 @@ static int __power_off_iris33_hardware(struct msm_vidc_core *core)
 	bool pwr_collapsed = false;
 
 	/*
-	 * Incase hw power control is enabled, when CPU WD occurred, check for power
-	 * status to decide on executing NOC reset sequence before disabling power.
-	 * If there is no CPU WD and hw_power_control is enabled, fw is expected
+	 * Incase hw power control is enabled, for both CPU WD, video
+	 * hw unresponsive cases, check for power status to decide on
+	 * executing NOC reset sequence before disabling power. If there
+	 * is no CPU WD and hw_power_control is enabled, fw is expected
 	 * to power collapse video hw always.
 	 */
 	if (core->hw_power_control) {
 		pwr_collapsed = is_iris33_hw_power_collapsed(core);
-		if (core->cpu_watchdog) {
+		if (core->cpu_watchdog || core->video_unresponsive) {
 			if (pwr_collapsed) {
-				d_vpr_e("%s: CPU WD and video hw power collapsed\n", __func__);
+				d_vpr_e("%s: video hw power collapsed %d, %d\n",
+					__func__, core->cpu_watchdog, core->video_unresponsive);
 				goto disable_power;
 			} else {
-				d_vpr_e("%s: CPU WD and video hw is power ON\n", __func__);
+				d_vpr_e("%s: video hw is power ON %d, %d\n",
+					__func__, core->cpu_watchdog, core->video_unresponsive);
 			}
 		} else {
 			if (!pwr_collapsed)

driver/variant/iris33/src/msm_vidc_power_iris33.c

@@ -212,6 +212,11 @@ u64 msm_vidc_calc_freq_iris33(struct msm_vidc_inst *inst, u32 data_size)
 			if (fps >= 960)
 				vsp_cycles += div_u64(vpp_cycles * 25, 100);
 
+			/* Add 25 percent extra for HEVC 10bit all intra use case */
+			if (inst->iframe && is_hevc_10bit_decode_session(inst)) {
+				vsp_cycles += div_u64(vsp_cycles * 25, 100);
+			}
+
 			if (inst->codec == MSM_VIDC_VP9 &&
 					inst->capabilities->cap[STAGE].value ==
 						MSM_VIDC_STAGE_2 &&
@@ -227,11 +232,14 @@ u64 msm_vidc_calc_freq_iris33(struct msm_vidc_inst *inst, u32 data_size)
 	freq = max(vpp_cycles, vsp_cycles);
 	freq = max(freq, fw_cycles);
 
-	if (inst->codec != MSM_VIDC_AV1) {
+	if (inst->codec == MSM_VIDC_AV1 ||
+		(inst->iframe && is_hevc_10bit_decode_session(inst))) {
 		/*
-		 * for non-AV1 codecs limit the frequency to NOM only
-		 * index 0 is TURBO, index 1 is NOM clock rate
+		 * for AV1 or HEVC 10bit and iframe case only allow TURBO and
+		 * limit to NOM for all other cases
 		 */
+	} else {
+		/* limit to NOM, index 0 is TURBO, index 1 is NOM clock rate */
 		if (core->resource->freq_set.count >= 2 &&
 		    freq > core->resource->freq_set.freq_tbl[1].freq)
 			freq = core->resource->freq_set.freq_tbl[1].freq;

driver/vidc/inc/msm_vidc_core.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2020-2021,, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _MSM_VIDC_CORE_H_
@@ -118,6 +119,7 @@ struct msm_vidc_core {
 	bool                                   hw_power_control;
 	bool                                   pm_suspended;
 	bool                                   cpu_watchdog;
+	bool                                   video_unresponsive;
 };
 
 #endif // _MSM_VIDC_CORE_H_

driver/vidc/inc/msm_vidc_driver.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021,, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _MSM_VIDC_DRIVER_H_
@@ -577,6 +578,7 @@ bool res_is_less_than(u32 width, u32 height,
 	u32 ref_width, u32 ref_height);
 bool res_is_less_than_or_equal_to(u32 width, u32 height,
 	u32 ref_width, u32 ref_height);
+bool is_hevc_10bit_decode_session(struct msm_vidc_inst *inst);
 int signal_session_msg_receipt(struct msm_vidc_inst *inst,
 	enum signal_session_response cmd);
 int msm_vidc_get_properties(struct msm_vidc_inst *inst);

driver/vidc/inc/msm_vidc_inst.h

@@ -181,5 +181,6 @@ struct msm_vidc_inst {
 	bool                               has_bframe;
 	bool                               ir_enabled;
 	u32                                adjust_priority;
+	bool                               iframe;
 };
 #endif // _MSM_VIDC_INST_H_

driver/vidc/inc/msm_vidc_internal.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2020-2021,, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _MSM_VIDC_INTERNAL_H_
@@ -437,9 +438,6 @@ enum msm_vidc_inst_capability_type {
 	BATCH_FPS,
 	LOSSLESS_MBPF,
 	SECURE_MBPF,
-	MBPS,
-	POWER_SAVE_MBPS,
-	CHECK_MBPS,
 	FRAME_RATE,
 	OPERATING_RATE,
 	INPUT_RATE,

driver/vidc/src/msm_vidc.c

@@ -901,6 +901,7 @@ void *msm_vidc_open(void *vidc_core, u32 session_type)
 	inst->ipsc_properties_set = false;
 	inst->opsc_properties_set = false;
 	inst->has_bframe = false;
+	inst->iframe = false;
 	inst->auto_framerate = DEFAULT_FPS << 16;
 	inst->initial_time_us = ktime_get_ns() / 1000;
 	kref_init(&inst->kref);

driver/vidc/src/msm_vidc_control.c

@@ -3104,7 +3104,7 @@ int msm_vidc_set_header_mode(void *instance,
 	else
 		hfi_value = HFI_SEQ_HEADER_SEPERATE_FRAME;
 
-	if (is_meta_rx_inp_enabled(inst, META_SEQ_HDR_NAL))
+	if (is_meta_rx_out_enabled(inst, META_SEQ_HDR_NAL))
 		hfi_value |= HFI_SEQ_HEADER_METADATA;
 
 	rc = msm_vidc_packetize_control(inst, cap_id, HFI_PAYLOAD_U32_ENUM,

driver/vidc/src/msm_vidc_driver.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/iommu.h>
@@ -97,9 +98,6 @@ static const struct msm_vidc_cap_name cap_name_arr[] = {
 	{BATCH_FPS,                      "BATCH_FPS"                  },
 	{LOSSLESS_MBPF,                  "LOSSLESS_MBPF"              },
 	{SECURE_MBPF,                    "SECURE_MBPF"                },
-	{MBPS,                           "MBPS"                       },
-	{POWER_SAVE_MBPS,                "POWER_SAVE_MBPS"            },
-	{CHECK_MBPS,                     "CHECK_MPBS"                 },
 	{FRAME_RATE,                     "FRAME_RATE"                 },
 	{OPERATING_RATE,                 "OPERATING_RATE"             },
 	{INPUT_RATE,                     "INPUT_RATE"                 },
@@ -1800,6 +1798,22 @@ bool msm_vidc_allow_psc_last_flag(struct msm_vidc_inst *inst)
 	return false;
 }
 
+bool is_hevc_10bit_decode_session(struct msm_vidc_inst *inst)
+{
+	bool is10bit = false;
+	enum msm_vidc_colorformat_type colorformat;
+
+	colorformat = v4l2_colorformat_to_driver(inst,
+		inst->fmts[OUTPUT_PORT].fmt.pix_mp.pixelformat, __func__);
+
+	if (colorformat == MSM_VIDC_FMT_TP10C || colorformat == MSM_VIDC_FMT_P010)
+		is10bit = true;
+
+	return inst->domain == MSM_VIDC_DECODER &&
+				inst->codec == MSM_VIDC_HEVC &&
+				is10bit;
+}
+
 int msm_vidc_state_change_streamon(struct msm_vidc_inst *inst,
 		enum msm_vidc_port_type port)
 {
@@ -4945,6 +4959,7 @@ int msm_vidc_core_init_wait(struct msm_vidc_core *core)
 	} else {
 		d_vpr_h("%s: sys init wait timedout. state %s\n",
 			__func__, core_state_name(core->state));
+		core->video_unresponsive = true;
 		rc = -EINVAL;
 		goto unlock;
 	}
@@ -5019,6 +5034,8 @@ int msm_vidc_inst_timeout(struct msm_vidc_inst *inst)
 		rc = -EINVAL;
 		goto unlock;
 	}
+	/* mark video hw unresponsive */
+	core->video_unresponsive = true;
 
 	/* call core deinit for a valid instance timeout case */
 	msm_vidc_core_deinit_locked(core, true);

driver/vidc/src/venus_hfi.c

@@ -687,6 +687,7 @@ int __load_fw(struct msm_vidc_core *core)
 	core->handoff_done = false;
 	core->hw_power_control = false;
 	core->cpu_watchdog = false;
+	core->video_unresponsive = false;
 
 	trace_msm_v4l2_vidc_fw_load("START");
 	rc = __venus_power_on(core);
@@ -726,6 +727,7 @@ void __unload_fw(struct msm_vidc_core *core)
 	__venus_power_off(core);
 
 	core->cpu_watchdog = false;
+	core->video_unresponsive = false;
 
 	d_vpr_h("%s done\n", __func__);
 }
@@ -815,6 +817,7 @@ void venus_hfi_pm_work_handler(struct work_struct *work)
 		d_vpr_e("Failed to PC for %d times\n",
 				core->skip_pc_count);
 		core->skip_pc_count = 0;
+		core->video_unresponsive = true;
 		msm_vidc_core_deinit(core, true);
 		return;
 	}

driver/vidc/src/venus_hfi_response.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/devcoredump.h>
@@ -1661,6 +1662,10 @@ static int handle_property_with_payload(struct msm_vidc_inst *inst,
 		inst->hfi_frame_info.picture_type = payload_ptr[0];
 		if (inst->hfi_frame_info.picture_type & HFI_PICTURE_B)
 			inst->has_bframe = true;
+		if (inst->hfi_frame_info.picture_type & HFI_PICTURE_IDR)
+			inst->iframe = true;
+		else
+			inst->iframe = false;
 		break;
 	case HFI_PROP_SUBFRAME_INPUT:
 		if (port != INPUT_PORT) {