Merge "Video Driver: fix frame freeze for HEVC 10bit all intra decoding"

driver/variant/iris3/src/msm_vidc_iris3.c

@@ -274,19 +274,22 @@ static int __power_off_iris3_hardware(struct msm_vidc_core *core)
 	bool pwr_collapsed = false;
 
 	/*
-	 * Incase hw power control is enabled, when CPU WD occurred, check for power
-	 * status to decide on executing NOC reset sequence before disabling power.
-	 * If there is no CPU WD and hw_power_control is enabled, fw is expected
+	 * Incase hw power control is enabled, for both CPU WD, video
+	 * hw unresponsive cases, check for power status to decide on
+	 * executing NOC reset sequence before disabling power. If there
+	 * is no CPU WD and hw_power_control is enabled, fw is expected
 	 * to power collapse video hw always.
 	 */
 	if (core->hw_power_control) {
 		pwr_collapsed = is_iris3_hw_power_collapsed(core);
-		if (core->cpu_watchdog) {
+		if (core->cpu_watchdog || core->video_unresponsive) {
 			if (pwr_collapsed) {
-				d_vpr_e("%s: CPU WD and video hw power collapsed\n", __func__);
+				d_vpr_e("%s: video hw power collapsed %d, %d\n",
+					__func__, core->cpu_watchdog, core->video_unresponsive);
 				goto disable_power;
 			} else {
-				d_vpr_e("%s: CPU WD and video hw is power ON\n", __func__);
+				d_vpr_e("%s: video hw is power ON %d, %d\n",
+					__func__, core->cpu_watchdog, core->video_unresponsive);
 			}
 		} else {
 			if (!pwr_collapsed)

driver/variant/iris3/src/msm_vidc_power_iris3.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include "msm_vidc_power_iris3.h"
@@ -213,6 +213,11 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
 			if (fps >= 960)
 				vsp_cycles += div_u64(vpp_cycles * 25, 100);
 
+			/* Add 25 percent extra for HEVC 10bit all intra use case */
+			if (inst->iframe && is_hevc_10bit_decode_session(inst)) {
+				vsp_cycles += div_u64(vsp_cycles * 25, 100);
+			}
+
 			if (inst->codec == MSM_VIDC_VP9 &&
 					inst->capabilities->cap[STAGE].value ==
 						MSM_VIDC_STAGE_2 &&
@@ -228,11 +233,14 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
 	freq = max(vpp_cycles, vsp_cycles);
 	freq = max(freq, fw_cycles);
 
-	if (inst->codec != MSM_VIDC_AV1) {
+	if (inst->codec == MSM_VIDC_AV1 ||
+		(inst->iframe && is_hevc_10bit_decode_session(inst))) {
 		/*
-		 * for non-AV1 codecs limit the frequency to NOM only
-		 * index 0 is TURBO, index 1 is NOM clock rate
+		 * for AV1 or HEVC 10bit and iframe case only allow TURBO and
+		 * limit to NOM for all other cases
 		 */
+	} else {
+		/* limit to NOM, index 0 is TURBO, index 1 is NOM clock rate */
 		if (core->resource->freq_set.count >= 2 &&
 		    freq > core->resource->freq_set.freq_tbl[1].freq)
 			freq = core->resource->freq_set.freq_tbl[1].freq;

driver/variant/iris33/src/msm_vidc_iris33.c

@@ -277,19 +277,22 @@ static int __power_off_iris33_hardware(struct msm_vidc_core *core)
 	bool pwr_collapsed = false;
 
 	/*
-	 * Incase hw power control is enabled, when CPU WD occurred, check for power
-	 * status to decide on executing NOC reset sequence before disabling power.
-	 * If there is no CPU WD and hw_power_control is enabled, fw is expected
+	 * Incase hw power control is enabled, for both CPU WD, video
+	 * hw unresponsive cases, check for power status to decide on
+	 * executing NOC reset sequence before disabling power. If there
+	 * is no CPU WD and hw_power_control is enabled, fw is expected
 	 * to power collapse video hw always.
 	 */
 	if (core->hw_power_control) {
 		pwr_collapsed = is_iris33_hw_power_collapsed(core);
-		if (core->cpu_watchdog) {
+		if (core->cpu_watchdog || core->video_unresponsive) {
 			if (pwr_collapsed) {
-				d_vpr_e("%s: CPU WD and video hw power collapsed\n", __func__);
+				d_vpr_e("%s: video hw power collapsed %d, %d\n",
+					__func__, core->cpu_watchdog, core->video_unresponsive);
 				goto disable_power;
 			} else {
-				d_vpr_e("%s: CPU WD and video hw is power ON\n", __func__);
+				d_vpr_e("%s: video hw is power ON %d, %d\n",
+					__func__, core->cpu_watchdog, core->video_unresponsive);
 			}
 		} else {
 			if (!pwr_collapsed)

driver/variant/iris33/src/msm_vidc_power_iris33.c

@@ -212,6 +212,11 @@ u64 msm_vidc_calc_freq_iris33(struct msm_vidc_inst *inst, u32 data_size)
 			if (fps >= 960)
 				vsp_cycles += div_u64(vpp_cycles * 25, 100);
 
+			/* Add 25 percent extra for HEVC 10bit all intra use case */
+			if (inst->iframe && is_hevc_10bit_decode_session(inst)) {
+				vsp_cycles += div_u64(vsp_cycles * 25, 100);
+			}
+
 			if (inst->codec == MSM_VIDC_VP9 &&
 					inst->capabilities->cap[STAGE].value ==
 						MSM_VIDC_STAGE_2 &&
@@ -227,11 +232,14 @@ u64 msm_vidc_calc_freq_iris33(struct msm_vidc_inst *inst, u32 data_size)
 	freq = max(vpp_cycles, vsp_cycles);
 	freq = max(freq, fw_cycles);
 
-	if (inst->codec != MSM_VIDC_AV1) {
+	if (inst->codec == MSM_VIDC_AV1 ||
+		(inst->iframe && is_hevc_10bit_decode_session(inst))) {
 		/*
-		 * for non-AV1 codecs limit the frequency to NOM only
-		 * index 0 is TURBO, index 1 is NOM clock rate
+		 * for AV1 or HEVC 10bit and iframe case only allow TURBO and
+		 * limit to NOM for all other cases
 		 */
+	} else {
+		/* limit to NOM, index 0 is TURBO, index 1 is NOM clock rate */
 		if (core->resource->freq_set.count >= 2 &&
 		    freq > core->resource->freq_set.freq_tbl[1].freq)
 			freq = core->resource->freq_set.freq_tbl[1].freq;