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Merge "msm: camera: isp: Add new IRQ for CSID 780" into camera-kernel.lnx.5.0

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This commit is contained in:
Savita Patted
2021-06-08 19:56:38 -07:00
committed by Gerrit - the friendly Code Review server
parent 8c98bdf674 e4525208a0
commit b06f482946
7 changed files with 1132 additions and 192 deletions
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229
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid680.h
View File

@@ -15,6 +15,232 @@
#define CAM_CSID_VERSION_V680 0x60080000
static const struct cam_ife_csid_irq_desc cam_ife_csid_680_rx_irq_desc[] = {
{
.bitmask = BIT(0),
.desc = "DL0_EOT",
},
{
.bitmask = BIT(1),
.desc = "DL1_EOT",
},
{
.bitmask = BIT(2),
.desc = "DL2_EOT",
},
{
.bitmask = BIT(3),
.desc = "DL3_EOT",
},
{
.bitmask = BIT(4),
.desc = "DL0_SOT",
},
{
.bitmask = BIT(5),
.desc = "DL1_SOT",
},
{
.bitmask = BIT(6),
.desc = "DL2_SOT",
},
{
.bitmask = BIT(7),
.desc = "DL3_SOT",
},
{
.bitmask = BIT(8),
.desc = "LONG_PKT",
},
{
.bitmask = BIT(9),
.desc = "SHORT_PKT",
},
{
.bitmask = BIT(10),
.desc = "CPHY_PKT_HDR",
},
{
.bitmask = BIT(11),
.desc = "ERROR_CPHY_EOT_RECEPTION",
},
{
.bitmask = BIT(12),
.desc = "ERROR_CPHY_SOT_RECEPTION",
},
{
.bitmask = BIT(13),
.desc = "ERROR_CPHY_PH_CRC",
},
{
.bitmask = BIT(14),
.desc = "WARNING_ECC",
},
{
.bitmask = BIT(15),
.desc = "ERROR_LANE0_FIFO_OVERFLOW",
},
{
.bitmask = BIT(16),
.desc = "ERROR_LANE1_FIFO_OVERFLOW",
},
{
.bitmask = BIT(17),
.desc = "ERROR_LANE2_FIFO_OVERFLOW",
},
{
.bitmask = BIT(18),
.desc = "ERROR_LANE3_FIFO_OVERFLOW",
},
{
.bitmask = BIT(19),
.desc = "ERROR_CRC",
},
{
.bitmask = BIT(20),
.desc = "ERROR_ECC",
},
{
.bitmask = BIT(21),
.desc = "ERROR_MMAPPED_VC_DT",
},
{
.bitmask = BIT(22),
.desc = "ERROR_UNMAPPED_VC_DT",
},
{
.bitmask = BIT(23),
.desc = "ERROR_STREAM_UNDERFLOW",
},
{
.bitmask = BIT(24),
.desc = "ERROR_UNBOUNDED_FRAME",
},
};
static const struct cam_ife_csid_irq_desc cam_ife_csid_680_path_irq_desc[] = {
{
.bitmask = BIT(0),
.desc = "",
},
{
.bitmask = BIT(1),
.desc = "",
},
{
.bitmask = BIT(2),
.desc = "ERROR_FIFO_OVERFLOW",
},
{
.bitmask = BIT(3),
.desc = "CAMIF_EOF",
},
{
.bitmask = BIT(4),
.desc = "CAMIF_SOF",
},
{
.bitmask = BIT(5),
.desc = "FRAME_DROP_EOF",
},
{
.bitmask = BIT(6),
.desc = "FRAME_DROP_EOL",
},
{
.bitmask = BIT(7),
.desc = "FRAME_DROP_SOL",
},
{
.bitmask = BIT(8),
.desc = "FRAME_DROP_SOF",
},
{
.bitmask = BIT(9),
.desc = "INFO_INPUT_EOF",
},
{
.bitmask = BIT(10),
.desc = "INFO_INPUT_EOL",
},
{
.bitmask = BIT(11),
.desc = "INFO_INPUT_SOL",
},
{
.bitmask = BIT(12),
.desc = "INFO_INPUT_SOF",
},
{
.bitmask = BIT(13),
.desc = "ERROR_PIX_COUNT",
},
{
.bitmask = BIT(14),
.desc = "ERROR_LINE_COUNT",
},
{
.bitmask = BIT(15),
.desc = "VCDT_GRP0_SEL",
},
{
.bitmask = BIT(16),
.desc = "VCDT_GRP1_SEL",
},
{
.bitmask = BIT(17),
.desc = "VCDT_GRP_CHANGE",
},
{
.bitmask = BIT(18),
.desc = "FRAME_DROP",
},
{
.bitmask = BIT(19),
.desc = "OVERFLOW_RECOVERY: Back pressure/output fifo ovrfl",
},
{
.bitmask = BIT(20),
.desc = "ERROR_REC_CCIF_VIOLATION From Camif",
},
{
.bitmask = BIT(21),
.desc = "CAMIF_EPOCH0",
},
{
.bitmask = BIT(22),
.desc = "CAMIF_EPOCH1",
},
{
.bitmask = BIT(23),
.desc = "RUP_DONE",
},
{
.bitmask = BIT(24),
.desc = "ILLEGAL_BATCH_ID",
},
{
.bitmask = BIT(25),
.desc = "BATCH_END_MISSING_VIOLATION",
},
{
.bitmask = BIT(26),
.desc = "HEIGHT_VIOLATION",
},
{
.bitmask = BIT(27),
.desc = "WIDTH_VIOLATION",
},
{
.bitmask = BIT(28),
.desc = "SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP",
},
{
.bitmask = BIT(29),
.desc = "CCIF_VIOLATION: Bad frame timings",
},
};
static struct cam_irq_register_set cam_ife_csid_680_irq_reg_set[9] = {
/* Top */
{
@@ -916,6 +1142,7 @@ static struct cam_ife_csid_ver2_common_reg_info
.ipp_irq_mask_all = 0x7FFF,
.rdi_irq_mask_all = 0x7FFF,
.ppp_irq_mask_all = 0xFFFF,
.top_err_irq_mask = 0x0,
.rst_loc_path_only_val = 0x0,
.rst_loc_complete_csid_val = 0x1,
.rst_mode_frame_boundary_val = 0x0,
@@ -1006,5 +1233,7 @@ static struct cam_ife_csid_ver2_reg_info cam_ife_csid_680_reg_info = {
},
.need_top_cfg = 0x1,
.csid_cust_node_map = {0x1, 0x0, 0x2},
.rx_irq_desc = cam_ife_csid_680_rx_irq_desc,
.path_irq_desc = cam_ife_csid_680_path_irq_desc,
};
#endif /*_CAM_IFE_CSID_680_H_ */

274
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid780.h
View File

@@ -12,9 +12,263 @@
#include "cam_ife_csid_common.h"
#include "cam_ife_csid_hw_ver2.h"
#include "cam_irq_controller.h"
#include "cam_isp_hw_mgr_intf.h"
#define CAM_CSID_VERSION_V780 0x70080000
static const struct cam_ife_csid_irq_desc cam_ife_csid_780_rx_irq_desc[] = {
{
.bitmask = BIT(0),
.desc = "DL0_EOT",
},
{
.bitmask = BIT(1),
.desc = "DL1_EOT",
},
{
.bitmask = BIT(2),
.desc = "DL2_EOT",
},
{
.bitmask = BIT(3),
.desc = "DL3_EOT",
},
{
.bitmask = BIT(4),
.desc = "DL0_SOT",
},
{
.bitmask = BIT(5),
.desc = "DL1_SOT",
},
{
.bitmask = BIT(6),
.desc = "DL2_SOT",
},
{
.bitmask = BIT(7),
.desc = "DL3_SOT",
},
{
.bitmask = BIT(8),
.desc = "LONG_PKT",
},
{
.bitmask = BIT(9),
.desc = "SHORT_PKT",
},
{
.bitmask = BIT(10),
.desc = "CPHY_PKT_HDR",
},
{
.bitmask = BIT(11),
.desc = "ERROR_CPHY_EOT_RECEPTION",
},
{
.bitmask = BIT(12),
.desc = "ERROR_CPHY_SOT_RECEPTION",
},
{
.bitmask = BIT(13),
.desc = "ERROR_CPHY_PH_CRC",
},
{
.bitmask = BIT(14),
.desc = "WARNING_ECC",
},
{
.bitmask = BIT(15),
.desc = "ERROR_LANE0_FIFO_OVERFLOW",
},
{
.bitmask = BIT(16),
.desc = "ERROR_LANE1_FIFO_OVERFLOW",
},
{
.bitmask = BIT(17),
.desc = "ERROR_LANE2_FIFO_OVERFLOW",
},
{
.bitmask = BIT(18),
.desc = "ERROR_LANE3_FIFO_OVERFLOW",
},
{
.bitmask = BIT(19),
.desc = "ERROR_CRC",
},
{
.bitmask = BIT(20),
.desc = "ERROR_ECC",
},
{
.bitmask = BIT(21),
.desc = "ERROR_MMAPPED_VC_DT",
},
{
.bitmask = BIT(22),
.desc = "ERROR_UNMAPPED_VC_DT",
},
{
.bitmask = BIT(23),
.desc = "ERROR_STREAM_UNDERFLOW",
},
{
.bitmask = BIT(24),
.desc = "ERROR_UNBOUNDED_FRAME",
},
};
static const struct cam_ife_csid_irq_desc cam_ife_csid_780_path_irq_desc[] = {
{
.bitmask = BIT(0),
.desc = "ILLEGAL_PROGRAMMING",
},
{
.bitmask = BIT(1),
.desc = "EROOR_MSG_FIFO_OVERFLOW",
},
{
.bitmask = BIT(2),
.desc = "ERROR_FIFO_OVERFLOW",
},
{
.bitmask = BIT(3),
.desc = "CAMIF_EOF",
},
{
.bitmask = BIT(4),
.desc = "CAMIF_SOF",
},
{
.bitmask = BIT(5),
.desc = "FRAME_DROP_EOF",
},
{
.bitmask = BIT(6),
.desc = "FRAME_DROP_EOL",
},
{
.bitmask = BIT(7),
.desc = "FRAME_DROP_SOL",
},
{
.bitmask = BIT(8),
.desc = "FRAME_DROP_SOF",
},
{
.bitmask = BIT(9),
.desc = "INFO_INPUT_EOF",
},
{
.bitmask = BIT(10),
.desc = "INFO_INPUT_EOL",
},
{
.bitmask = BIT(11),
.desc = "INFO_INPUT_SOL",
},
{
.bitmask = BIT(12),
.desc = "INFO_INPUT_SOF",
},
{
.bitmask = BIT(13),
.desc = "ERROR_PIX_COUNT",
},
{
.bitmask = BIT(14),
.desc = "ERROR_LINE_COUNT",
},
{
.bitmask = BIT(15),
.desc = "VCDT_GRP0_SEL",
},
{
.bitmask = BIT(16),
.desc = "VCDT_GRP1_SEL",
},
{
.bitmask = BIT(17),
.desc = "VCDT_GRP_CHANGE",
},
{
.bitmask = BIT(18),
.desc = "FRAME_DROP",
},
{
.bitmask = BIT(19),
.desc = "OVERFLOW_RECOVERY: Back pressure/output fifo ovrfl",
},
{
.bitmask = BIT(20),
.desc = "ERROR_REC_CCIF_VIOLATION From Camif",
},
{
.bitmask = BIT(21),
.desc = "CAMIF_EPOCH0",
},
{
.bitmask = BIT(22),
.desc = "CAMIF_EPOCH1",
},
{
.bitmask = BIT(23),
.desc = "RUP_DONE",
},
{
.bitmask = BIT(24),
.desc = "ILLEGAL_BATCH_ID",
},
{
.bitmask = BIT(25),
.desc = "BATCH_END_MISSING_VIOLATION",
},
{
.bitmask = BIT(26),
.desc = "HEIGHT_VIOLATION",
},
{
.bitmask = BIT(27),
.desc = "WIDTH_VIOLATION",
},
{
.bitmask = BIT(28),
.desc = "SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP",
},
{
.bitmask = BIT(29),
.desc = "CCIF_VIOLATION: Bad frame timings",
},
};
static const struct cam_ife_csid_top_irq_desc cam_ife_csid_780_top_irq_desc[] = {
{
.bitmask = BIT(1),
.err_type = CAM_ISP_HW_ERROR_CSID_FATAL,
.err_name = "FATAL_SENSOR_SWITCHING_IRQ",
.desc = "Fatal Error duirng dynamically switching between 2 sensors",
},
{
.bitmask = BIT(18),
.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
.err_name = "ERROR_NO_VOTE_DN",
.desc = "vote_up is asserted before IDLE is encountered in a frame",
},
{
.bitmask = BIT(19),
.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
.err_name = "ERROR_VOTE_UP_LATE",
.desc = "vote_up is asserted at the same time as an SOF",
},
{
.bitmask = BIT(20),
.err_type = CAM_ISP_HW_ERROR_CSID_FIFO_OVERFLOW,
.err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
.desc = "Two or more RDIs programmed to access the shared line buffer",
},
};
static struct cam_irq_register_set cam_ife_csid_780_irq_reg_set[9] = {
/* Top */
{
@@ -200,7 +454,7 @@ static struct cam_ife_csid_ver2_pxl_reg_info
.stripe_loc_shift_val = 20,
.lut_bank_0_sel_val = 0,
.lut_bank_1_sel_val = 1,
.fatal_err_mask = 0x186005,
.fatal_err_mask = 0x186007,
.non_fatal_err_mask = 0x10000000,
.camif_irq_mask = 0x800000,
.rup_aup_mask = 0x10001,
@@ -296,7 +550,7 @@ static struct cam_ife_csid_ver2_pxl_reg_info
.start_master_sel_shift_val = 4,
.lut_bank_0_sel_val = 0,
.lut_bank_1_sel_val = 1,
.fatal_err_mask = 0x186005,
.fatal_err_mask = 0x186007,
.non_fatal_err_mask = 0x10000000,
.rup_aup_mask = 0x40004,
.top_irq_mask = 0x10,
@@ -391,7 +645,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
.pix_pattern_shift_val = 24,
.stripe_loc_shift_val = 20,
.ccif_violation_en = 1,
.fatal_err_mask = 0x186005,
.fatal_err_mask = 0x186007,
.non_fatal_err_mask = 0x10000000,
.camif_irq_mask = 0x800000,
.rup_aup_mask = 0x100010,
@@ -487,7 +741,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
.pix_pattern_shift_val = 24,
.stripe_loc_shift_val = 20,
.ccif_violation_en = 1,
.fatal_err_mask = 0x186005,
.fatal_err_mask = 0x186007,
.non_fatal_err_mask = 0x10000000,
.camif_irq_mask = 0x800000,
.rup_aup_mask = 0x200020,
@@ -583,7 +837,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
.pix_pattern_shift_val = 24,
.stripe_loc_shift_val = 20,
.ccif_violation_en = 1,
.fatal_err_mask = 0x186005,
.fatal_err_mask = 0x186007,
.non_fatal_err_mask = 0x10000000,
.camif_irq_mask = 0x800000,
.rup_aup_mask = 0x400040,
@@ -679,7 +933,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
.pix_pattern_shift_val = 24,
.stripe_loc_shift_val = 20,
.ccif_violation_en = 1,
.fatal_err_mask = 0x186005,
.fatal_err_mask = 0x186007,
.non_fatal_err_mask = 0x10000000,
.camif_irq_mask = 0x800000,
.rup_aup_mask = 0x800080,
@@ -775,7 +1029,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
.pix_pattern_shift_val = 24,
.stripe_loc_shift_val = 20,
.ccif_violation_en = 1,
.fatal_err_mask = 0x186005,
.fatal_err_mask = 0x186007,
.non_fatal_err_mask = 0x10000000,
.camif_irq_mask = 0x800000,
.rup_aup_mask = 0x1000100,
@@ -913,7 +1167,7 @@ static struct cam_ife_csid_ver2_common_reg_info
.ipp_irq_mask_all = 0x7FFF,
.rdi_irq_mask_all = 0x7FFF,
.ppp_irq_mask_all = 0xFFFF,
.top_err_irq_mask = 0x2,
.top_err_irq_mask = 0x1C0002,
.rst_loc_path_only_val = 0x0,
.rst_loc_complete_csid_val = 0x1,
.rst_mode_frame_boundary_val = 0x0,
@@ -1004,5 +1258,9 @@ static struct cam_ife_csid_ver2_reg_info cam_ife_csid_780_reg_info = {
},
.need_top_cfg = 0x1,
.csid_cust_node_map = {0x1, 0x0, 0x2},
.rx_irq_desc = cam_ife_csid_780_rx_irq_desc,
.path_irq_desc = cam_ife_csid_780_path_irq_desc,
.top_irq_desc = cam_ife_csid_780_top_irq_desc,
.num_top_err_irqs = ARRAY_SIZE(cam_ife_csid_780_top_irq_desc),
};
#endif /*_CAM_IFE_CSID_780_H_ */

16
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.h
View File

@@ -94,12 +94,28 @@ enum cam_ife_csid_irq_reg {
/*
* struct cam_ife_csid_irq_desc: Structure to hold IRQ description
*
* @bitmask : Bitmask of the IRQ
* @irq_desc: String to describe the IRQ bit
*/
struct cam_ife_csid_irq_desc {
uint32_t bitmask;
uint8_t *desc;
};
/*
* struct cam_ife_csid_top_irq_desc: Structure to hold IRQ bitmask and description
*
* @bitmask : Bitmask of the IRQ
* @err_name : IRQ name
* @desc : String to describe about the IRQ
*/
struct cam_ife_csid_top_irq_desc {
uint32_t bitmask;
uint32_t err_type;
char *err_name;
char *desc;
};
/*
* struct cam_ife_csid_vc_dt: Structure to hold vc dt combination
*

301
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c
View File

@@ -51,180 +51,6 @@
/* Max CSI Rx irq error count threshold value */
#define CAM_IFE_CSID_MAX_IRQ_ERROR_COUNT 100
static const struct cam_ife_csid_irq_desc ver2_rx_irq_desc[] = {
{
.desc = "DL0_EOT",
},
{
.desc = "DL1_EOT",
},
{
.desc = "DL2_EOT",
},
{
.desc = "DL3_EOT",
},
{
.desc = "DL0_SOT",
},
{
.desc = "DL1_SOT",
},
{
.desc = "DL2_SOT",
},
{
.desc = "DL3_SOT",
},
{
.desc = "LONG_PKT",
},
{
.desc = "SHORT_PKT",
},
{
.desc = "CPHY_PKT_HDR",
},
{
.desc = "ERROR_CPHY_EOT_RECEPTION",
},
{
.desc = "ERROR_CPHY_SOT_RECEPTION",
},
{
.desc = "ERROR_CPHY_PH_CRC",
},
{
.desc = "WARNING_ECC",
},
{
.desc = "ERROR_LANE0_FIFO_OVERFLOW",
},
{
.desc = "ERROR_LANE1_FIFO_OVERFLOW",
},
{
.desc = "ERROR_LANE2_FIFO_OVERFLOW",
},
{
.desc = "ERROR_LANE3_FIFO_OVERFLOW",
},
{
.desc = "ERROR_CRC",
},
{
.desc = "ERROR_ECC",
},
{
.desc = "ERROR_MMAPPED_VC_DT",
},
{
.desc = "ERROR_UNMAPPED_VC_DT",
},
{
.desc = "ERROR_STREAM_UNDERFLOW",
},
{
.desc = "ERROR_UNBOUNDED_FRAME",
},
{
.desc = "RST_DONE",
},
};
static const struct cam_ife_csid_irq_desc ver2_path_irq_desc[] = {
{
.desc = "",
},
{
.desc = "",
},
{
.desc = "ERROR_FIFO_OVERFLOW",
},
{
.desc = "CAMIF_EOF",
},
{
.desc = "CAMIF_SOF",
},
{
.desc = "FRAME_DROP_EOF",
},
{
.desc = "FRAME_DROP_EOL",
},
{
.desc = "FRAME_DROP_SOL",
},
{
.desc = "FRAME_DROP_SOF",
},
{
.desc = "INFO_INPUT_EOF",
},
{
.desc = "INFO_INPUT_EOL",
},
{
.desc = "INFO_INPUT_SOL",
},
{
.desc = "INFO_INPUT_SOF",
},
{
.desc = "ERROR_PIX_COUNT",
},
{
.desc = "ERROR_LINE_COUNT",
},
{
.desc = "VCDT_GRP0_SEL",
},
{
.desc = "VCDT_GRP1_SEL",
},
{
.desc = "VCDT_GRP_CHANGE",
},
{
.desc = "FRAME_DROP",
},
{
.desc = "OVERFLOW_RECOVERY: Back pressure/output fifo ovrfl",
},
{
.desc = "ERROR_REC_CCIF_VIOLATION From Camif",
},
{
.desc = "CAMIF_EPOCH0",
},
{
.desc = "CAMIF_EPOCH1",
},
{
.desc = "RUP_DONE",
},
{
.desc = "ILLEGAL_BATCH_ID",
},
{
.desc = "BATCH_END_MISSING_VIOLATION",
},
{
.desc = "HEIGHT_VIOLATION",
},
{
.desc = "WIDTH_VIOLATION",
},
{
.desc = "SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP",
},
{
.desc = "CCIF_VIOLATION: Bad frame timings",
},
};
static int cam_ife_csid_ver2_set_debug(
struct cam_ife_csid_ver2_hw *csid_hw,
uint32_t debug_val)
@@ -408,6 +234,42 @@ static int cam_ife_csid_ver2_put_evt_payload(
return 0;
}
static int cam_ife_csid_ver2_top_err_irq_top_half(
uint32_t evt_id,
struct cam_irq_th_payload *th_payload)
{
int rc = 0;
struct cam_ife_csid_ver2_hw *csid_hw = NULL;
struct cam_ife_csid_ver2_evt_payload *evt_payload;
struct cam_ife_csid_ver2_reg_info *csid_reg = NULL;
csid_hw = th_payload->handler_priv;
csid_reg = (struct cam_ife_csid_ver2_reg_info *)
csid_hw->core_info->csid_reg;
rc = cam_ife_csid_ver2_get_evt_payload(csid_hw, &evt_payload,
&csid_hw->path_free_payload_list,
&csid_hw->path_payload_lock);
CAM_DBG(CAM_ISP, "CSID:%d TOP status: 0x%x",
csid_hw->hw_intf->hw_idx,
th_payload->evt_status_arr[CAM_IFE_CSID_IRQ_REG_TOP]);
if (rc) {
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d TOP status: 0x%x",
csid_hw->hw_intf->hw_idx,
th_payload->evt_status_arr[CAM_IFE_CSID_IRQ_REG_TOP]);
return rc;
}
evt_payload->irq_reg_val[CAM_IFE_CSID_IRQ_REG_TOP] =
th_payload->evt_status_arr[CAM_IFE_CSID_IRQ_REG_TOP];
th_payload->evt_payload_priv = evt_payload;
return 0;
}
static int cam_ife_csid_ver2_handle_buf_done_irq(
uint32_t evt_id,
struct cam_irq_th_payload *th_payload)
@@ -959,7 +821,7 @@ static int cam_ife_csid_ver2_handle_rx_debug_event(
CAM_INFO_RATE_LIMIT(CAM_ISP,
"CSID[%d] RX_IRQ: %s",
csid_hw->hw_intf->hw_idx,
ver2_rx_irq_desc[bit_pos].desc);
csid_reg->rx_irq_desc[bit_pos].desc);
break;
}
@@ -1264,12 +1126,16 @@ static int cam_ife_csid_ver2_parse_path_irq_status(
uint32_t irq_status)
{
const uint8_t **irq_reg_tag;
const struct cam_ife_csid_ver2_reg_info *csid_reg;
uint32_t bit_pos = 0;
uint32_t status;
uint32_t sof_irq_debug_en = 0;
size_t len = 0;
uint8_t *log_buf = NULL;
csid_reg = (struct cam_ife_csid_ver2_reg_info *)
csid_hw->core_info->csid_reg;
log_buf = csid_hw->log_buf;
memset(log_buf, 0, sizeof(csid_hw->log_buf));
@@ -1279,7 +1145,7 @@ static int cam_ife_csid_ver2_parse_path_irq_status(
while (status) {
if (status & 0x1 )
CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len, "%s",
ver2_path_irq_desc[bit_pos].desc);
csid_reg->path_irq_desc[bit_pos].desc);
bit_pos++;
status >>= 1;
}
@@ -1296,7 +1162,7 @@ static int cam_ife_csid_ver2_parse_path_irq_status(
if (status & 0x1)
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID[%d] IRQ %s %s ",
csid_hw->hw_intf->hw_idx, irq_reg_tag[index],
ver2_path_irq_desc[bit_pos].desc);
csid_reg->path_irq_desc[bit_pos].desc);
bit_pos++;
status >>= 1;
@@ -1318,6 +1184,57 @@ static int cam_ife_csid_ver2_parse_path_irq_status(
return 0;
}
static int cam_ife_csid_ver2_top_err_irq_bottom_half(
void *handler_priv,
void *evt_payload_priv)
{
struct cam_ife_csid_ver2_evt_payload *payload;
struct cam_ife_csid_ver2_hw *csid_hw = NULL;
struct cam_ife_csid_ver2_reg_info *csid_reg;
uint32_t irq_status;
uint32_t event_type = 0;
uint32_t i = 0;
if (!handler_priv || !evt_payload_priv) {
CAM_ERR(CAM_ISP, "Invalid params");
return -EINVAL;
}
payload = evt_payload_priv;
csid_hw = handler_priv;
csid_reg = (struct cam_ife_csid_ver2_reg_info *)
csid_hw->core_info->csid_reg;
irq_status = payload->irq_reg_val[CAM_IFE_CSID_IRQ_REG_TOP] &
csid_reg->cmn_reg->top_err_irq_mask;
if (!irq_status) {
CAM_ERR(CAM_ISP, "Unexpected Scenario");
return 0;
}
for (i = 0; i < csid_reg->num_top_err_irqs; i++) {
if (csid_reg->top_irq_desc[i].bitmask &
irq_status) {
CAM_ERR(CAM_ISP, "%s %s",
csid_reg->top_irq_desc[i].err_name,
csid_reg->top_irq_desc[i].desc);
event_type |= csid_reg->top_irq_desc[i].err_type;
}
}
if (event_type)
cam_ife_csid_ver2_handle_event_err(csid_hw,
irq_status, event_type, NULL);
cam_ife_csid_ver2_put_evt_payload(csid_hw, &payload,
&csid_hw->path_free_payload_list,
&csid_hw->path_payload_lock);
return 0;
}
static int cam_ife_csid_ver2_ipp_bottom_half(
void *handler_priv,
void *evt_payload_priv)
@@ -3598,6 +3515,7 @@ static int cam_ife_csid_ver2_enable_hw(
int i;
void __iomem *mem_base;
uint32_t buf_done_irq_mask[CAM_IFE_CSID_IRQ_REG_MAX] = {0};
uint32_t top_err_irq_mask[CAM_IFE_CSID_IRQ_REG_MAX] = {0};
if (csid_hw->flags.device_enabled) {
CAM_DBG(CAM_ISP, "CSID[%d] hw has already been enabled",
@@ -3651,6 +3569,28 @@ static int cam_ife_csid_ver2_enable_hw(
return -EINVAL;
}
top_err_irq_mask[CAM_IFE_CSID_IRQ_REG_TOP] =
csid_reg->cmn_reg->top_err_irq_mask;
csid_hw->top_err_irq_handle = cam_irq_controller_subscribe_irq(
csid_hw->csid_irq_controller,
CAM_IRQ_PRIORITY_0,
top_err_irq_mask,
csid_hw,
cam_ife_csid_ver2_top_err_irq_top_half,
cam_ife_csid_ver2_top_err_irq_bottom_half,
csid_hw->tasklet,
&tasklet_bh_api);
if (csid_hw->top_err_irq_handle < 1) {
CAM_ERR(CAM_ISP, "csid[%d] top error irq subscribe fail",
csid_hw->hw_intf->hw_idx);
cam_irq_controller_unsubscribe_irq(
csid_hw->csid_irq_controller,
csid_hw->top_err_irq_handle);
csid_hw->top_err_irq_handle = 0;
return -EINVAL;
}
csid_hw->flags.device_enabled = true;
csid_hw->flags.fatal_err_detected = false;
CAM_DBG(CAM_ISP, "CSID:%d CSID HW version: 0x%x",
@@ -3952,6 +3892,13 @@ int cam_ife_csid_ver2_stop(void *hw_priv,
csid_hw->buf_done_irq_handle = 0;
}
if (csid_hw->top_err_irq_handle) {
rc = cam_irq_controller_unsubscribe_irq(
csid_hw->csid_irq_controller,
csid_hw->top_err_irq_handle);
csid_hw->buf_done_irq_handle = 0;
}
mutex_unlock(&csid_hw->hw_info->hw_mutex);
cam_ife_csid_ver2_disable_csi2(csid_hw);

5
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h
View File

@@ -573,6 +573,10 @@ struct cam_ife_csid_ver2_reg_info {
CAM_IFE_CSID_HW_NUM_MAX];
const int input_core_sel[
CAM_IFE_CSID_HW_NUM_MAX][CAM_IFE_CSID_INPUT_CORE_SEL_MAX];
const struct cam_ife_csid_irq_desc *rx_irq_desc;
const struct cam_ife_csid_irq_desc *path_irq_desc;
const struct cam_ife_csid_top_irq_desc *top_irq_desc;
const uint32_t num_top_err_irqs;
};
/*
@@ -646,6 +650,7 @@ struct cam_ife_csid_ver2_hw {
void *tasklet;
int reset_irq_handle;
int buf_done_irq_handle;
int top_err_irq_handle;
enum cam_isp_hw_sync_mode sync_mode;
uint32_t mup;
atomic_t discard_frame_per_path;

227
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite680.h
View File

@@ -11,6 +11,231 @@
#include "cam_ife_csid_hw_ver2.h"
#include "cam_irq_controller.h"
static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_680_rx_irq_desc[] = {
{
.bitmask = BIT(0),
.desc = "DL0_EOT",
},
{
.bitmask = BIT(1),
.desc = "DL1_EOT",
},
{
.bitmask = BIT(2),
.desc = "DL2_EOT",
},
{
.bitmask = BIT(3),
.desc = "DL3_EOT",
},
{
.bitmask = BIT(4),
.desc = "DL0_SOT",
},
{
.bitmask = BIT(5),
.desc = "DL1_SOT",
},
{
.bitmask = BIT(6),
.desc = "DL2_SOT",
},
{
.bitmask = BIT(7),
.desc = "DL3_SOT",
},
{
.bitmask = BIT(8),
.desc = "LONG_PKT",
},
{
.bitmask = BIT(9),
.desc = "SHORT_PKT",
},
{
.bitmask = BIT(10),
.desc = "CPHY_PKT_HDR",
},
{
.bitmask = BIT(11),
.desc = "ERROR_CPHY_EOT_RECEPTION",
},
{
.bitmask = BIT(12),
.desc = "ERROR_CPHY_SOT_RECEPTION",
},
{
.bitmask = BIT(13),
.desc = "ERROR_CPHY_PH_CRC",
},
{
.bitmask = BIT(14),
.desc = "WARNING_ECC",
},
{
.bitmask = BIT(15),
.desc = "ERROR_LANE0_FIFO_OVERFLOW",
},
{
.bitmask = BIT(16),
.desc = "ERROR_LANE1_FIFO_OVERFLOW",
},
{
.bitmask = BIT(17),
.desc = "ERROR_LANE2_FIFO_OVERFLOW",
},
{
.bitmask = BIT(18),
.desc = "ERROR_LANE3_FIFO_OVERFLOW",
},
{
.bitmask = BIT(19),
.desc = "ERROR_CRC",
},
{
.bitmask = BIT(20),
.desc = "ERROR_ECC",
},
{
.bitmask = BIT(21),
.desc = "ERROR_MMAPPED_VC_DT",
},
{
.bitmask = BIT(22),
.desc = "ERROR_UNMAPPED_VC_DT",
},
{
.bitmask = BIT(23),
.desc = "ERROR_STREAM_UNDERFLOW",
},
{
.bitmask = BIT(24),
.desc = "ERROR_UNBOUNDED_FRAME",
},
};
static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_680_path_irq_desc[] = {
{
.bitmask = BIT(0),
.desc = "",
},
{
.bitmask = BIT(1),
.desc = "",
},
{
.bitmask = BIT(2),
.desc = "ERROR_FIFO_OVERFLOW",
},
{
.bitmask = BIT(3),
.desc = "CAMIF_EOF",
},
{
.bitmask = BIT(4),
.desc = "CAMIF_SOF",
},
{
.bitmask = BIT(5),
.desc = "FRAME_DROP_EOF",
},
{
.bitmask = BIT(6),
.desc = "FRAME_DROP_EOL",
},
{
.bitmask = BIT(7),
.desc = "FRAME_DROP_SOL",
},
{
.bitmask = BIT(8),
.desc = "FRAME_DROP_SOF",
},
{
.bitmask = BIT(9),
.desc = "INFO_INPUT_EOF",
},
{
.bitmask = BIT(10),
.desc = "INFO_INPUT_EOL",
},
{
.bitmask = BIT(11),
.desc = "INFO_INPUT_SOL",
},
{
.bitmask = BIT(12),
.desc = "INFO_INPUT_SOF",
},
{
.bitmask = BIT(13),
.desc = "ERROR_PIX_COUNT",
},
{
.bitmask = BIT(14),
.desc = "ERROR_LINE_COUNT",
},
{
.bitmask = BIT(15),
.desc = "VCDT_GRP0_SEL",
},
{
.bitmask = BIT(16),
.desc = "VCDT_GRP1_SEL",
},
{
.bitmask = BIT(17),
.desc = "VCDT_GRP_CHANGE",
},
{
.bitmask = BIT(18),
.desc = "FRAME_DROP",
},
{
.bitmask = BIT(19),
.desc = "OVERFLOW_RECOVERY: Back pressure/output fifo ovrfl",
},
{
.bitmask = BIT(20),
.desc = "ERROR_REC_CCIF_VIOLATION From Camif",
},
{
.bitmask = BIT(21),
.desc = "CAMIF_EPOCH0",
},
{
.bitmask = BIT(22),
.desc = "CAMIF_EPOCH1",
},
{
.bitmask = BIT(23),
.desc = "RUP_DONE",
},
{
.bitmask = BIT(24),
.desc = "ILLEGAL_BATCH_ID",
},
{
.bitmask = BIT(25),
.desc = "BATCH_END_MISSING_VIOLATION",
},
{
.bitmask = BIT(26),
.desc = "HEIGHT_VIOLATION",
},
{
.bitmask = BIT(27),
.desc = "WIDTH_VIOLATION",
},
{
.bitmask = BIT(28),
.desc = "SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP",
},
{
.bitmask = BIT(29),
.desc = "CCIF_VIOLATION: Bad frame timings",
},
};
static struct cam_irq_register_set cam_ife_csid_lite_680_irq_reg_set[7] = {
/* Top */
{
@@ -679,5 +904,7 @@ static struct cam_ife_csid_ver2_reg_info cam_ife_csid_lite_680_reg_info = {
&cam_ife_csid_lite_680_rdi_3_reg_info,
},
.need_top_cfg = 0,
.rx_irq_desc = cam_ife_csid_lite_680_rx_irq_desc,
.path_irq_desc = cam_ife_csid_lite_680_path_irq_desc,
};
#endif /* _CAM_IFE_CSID_LITE_680_H_ */

258
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite780.h
View File

@@ -10,6 +10,260 @@
#include "cam_ife_csid_dev.h"
#include "cam_ife_csid_hw_ver2.h"
#include "cam_irq_controller.h"
#include "cam_isp_hw_mgr_intf.h"
static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_780_rx_irq_desc[] = {
{
.bitmask = BIT(0),
.desc = "DL0_EOT",
},
{
.bitmask = BIT(1),
.desc = "DL1_EOT",
},
{
.bitmask = BIT(2),
.desc = "DL2_EOT",
},
{
.bitmask = BIT(3),
.desc = "DL3_EOT",
},
{
.bitmask = BIT(4),
.desc = "DL0_SOT",
},
{
.bitmask = BIT(5),
.desc = "DL1_SOT",
},
{
.bitmask = BIT(6),
.desc = "DL2_SOT",
},
{
.bitmask = BIT(7),
.desc = "DL3_SOT",
},
{
.bitmask = BIT(8),
.desc = "LONG_PKT",
},
{
.bitmask = BIT(9),
.desc = "SHORT_PKT",
},
{
.bitmask = BIT(10),
.desc = "CPHY_PKT_HDR",
},
{
.bitmask = BIT(11),
.desc = "ERROR_CPHY_EOT_RECEPTION",
},
{
.bitmask = BIT(12),
.desc = "ERROR_CPHY_SOT_RECEPTION",
},
{
.bitmask = BIT(13),
.desc = "ERROR_CPHY_PH_CRC",
},
{
.bitmask = BIT(14),
.desc = "WARNING_ECC",
},
{
.bitmask = BIT(15),
.desc = "ERROR_LANE0_FIFO_OVERFLOW",
},
{
.bitmask = BIT(16),
.desc = "ERROR_LANE1_FIFO_OVERFLOW",
},
{
.bitmask = BIT(17),
.desc = "ERROR_LANE2_FIFO_OVERFLOW",
},
{
.bitmask = BIT(18),
.desc = "ERROR_LANE3_FIFO_OVERFLOW",
},
{
.bitmask = BIT(19),
.desc = "ERROR_CRC",
},
{
.bitmask = BIT(20),
.desc = "ERROR_ECC",
},
{
.bitmask = BIT(21),
.desc = "ERROR_MMAPPED_VC_DT",
},
{
.bitmask = BIT(22),
.desc = "ERROR_UNMAPPED_VC_DT",
},
{
.bitmask = BIT(23),
.desc = "ERROR_STREAM_UNDERFLOW",
},
{
.bitmask = BIT(24),
.desc = "ERROR_UNBOUNDED_FRAME",
},
};
static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_780_path_irq_desc[] = {
{
.bitmask = BIT(0),
.desc = "ILLEGAL_PROGRAMMING",
},
{
.bitmask = BIT(1),
.desc = "EROOR_MSG_FIFO_OVERFLOW",
},
{
.bitmask = BIT(2),
.desc = "ERROR_FIFO_OVERFLOW",
},
{
.bitmask = BIT(3),
.desc = "CAMIF_EOF",
},
{
.bitmask = BIT(4),
.desc = "CAMIF_SOF",
},
{
.bitmask = BIT(5),
.desc = "FRAME_DROP_EOF",
},
{
.bitmask = BIT(6),
.desc = "FRAME_DROP_EOL",
},
{
.bitmask = BIT(7),
.desc = "FRAME_DROP_SOL",
},
{
.bitmask = BIT(8),
.desc = "FRAME_DROP_SOF",
},
{
.bitmask = BIT(9),
.desc = "INFO_INPUT_EOF",
},
{
.bitmask = BIT(10),
.desc = "INFO_INPUT_EOL",
},
{
.bitmask = BIT(11),
.desc = "INFO_INPUT_SOL",
},
{
.bitmask = BIT(12),
.desc = "INFO_INPUT_SOF",
},
{
.bitmask = BIT(13),
.desc = "ERROR_PIX_COUNT",
},
{
.bitmask = BIT(14),
.desc = "ERROR_LINE_COUNT",
},
{
.bitmask = BIT(15),
.desc = "VCDT_GRP0_SEL",
},
{
.bitmask = BIT(16),
.desc = "VCDT_GRP1_SEL",
},
{
.bitmask = BIT(17),
.desc = "VCDT_GRP_CHANGE",
},
{
.bitmask = BIT(18),
.desc = "FRAME_DROP",
},
{
.bitmask = BIT(19),
.desc = "OVERFLOW_RECOVERY: Back pressure/output fifo ovrfl",
},
{
.bitmask = BIT(20),
.desc = "ERROR_REC_CCIF_VIOLATION From Camif",
},
{
.bitmask = BIT(21),
.desc = "CAMIF_EPOCH0",
},
{
.bitmask = BIT(22),
.desc = "CAMIF_EPOCH1",
},
{
.bitmask = BIT(23),
.desc = "RUP_DONE",
},
{
.bitmask = BIT(24),
.desc = "ILLEGAL_BATCH_ID",
},
{
.bitmask = BIT(25),
.desc = "BATCH_END_MISSING_VIOLATION",
},
{
.bitmask = BIT(26),
.desc = "HEIGHT_VIOLATION",
},
{
.bitmask = BIT(27),
.desc = "WIDTH_VIOLATION",
},
{
.bitmask = BIT(28),
.desc = "SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP",
},
{
.bitmask = BIT(29),
.desc = "CCIF_VIOLATION: Bad frame timings",
},
};
static const struct cam_ife_csid_top_irq_desc cam_ife_csid_lite_780_top_irq_desc[] = {
{
.bitmask = BIT(1),
.err_type = CAM_ISP_HW_ERROR_CSID_FATAL,
.err_name = "FATAL_SENSOR_SWITCHING_IRQ",
.desc = "Fatal Error duirng dynamically switching between 2 sensors",
},
{
.bitmask = BIT(18),
.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
.err_name = "ERROR_NO_VOTE_DN",
.desc = "vote_up is asserted before IDLE is encountered in a frame",
},
{
.bitmask = BIT(19),
.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
.err_name = "ERROR_VOTE_UP_LATE",
.desc = "vote_up is asserted at the same time as an SOF",
},
{
.bitmask = BIT(20),
.err_type = CAM_ISP_HW_ERROR_CSID_FIFO_OVERFLOW,
.err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
.desc = "Two or more RDIs programmed to access the shared line buffer",
},
};
static struct cam_irq_register_set cam_ife_csid_lite_780_irq_reg_set[7] = {
/* Top */
@@ -671,5 +925,9 @@ static struct cam_ife_csid_ver2_reg_info cam_ife_csid_lite_780_reg_info = {
&cam_ife_csid_lite_780_rdi_3_reg_info,
},
.need_top_cfg = 0,
.rx_irq_desc = cam_ife_csid_lite_780_rx_irq_desc,
.path_irq_desc = cam_ife_csid_lite_780_path_irq_desc,
.top_irq_desc = cam_ife_csid_lite_780_top_irq_desc,
.num_top_err_irqs = ARRAY_SIZE(cam_ife_csid_lite_780_top_irq_desc),
};
#endif /* _CAM_IFE_CSID_LITE_780_H_ */