asoc: bolero: Update PCM_RATE based delay for amic

The PCM_RATE bit field in LPASS_TX_CDC_TXn_TX_PATH_CTL
ranges from 0 to 6.
In the current implementation of tx-macro, the value
read is mapped directly to the sample rate instead of
the indices. Change is to correct this.
Add the delay based on pcm_rate in va-macro as well.

Change-Id: I6cb7e58e71f2a25356608611f1dfed83171706f6
Signed-off-by: Soumya Managoli <smanag@codeaurora.org>

asoc/codecs/lpass-cdc/lpass-cdc-va-macro.c

@@ -171,6 +171,7 @@ struct lpass_cdc_va_macro_priv {
 	bool lpi_enable;
 	bool clk_div_switch;
 	int dec_mode[LPASS_CDC_VA_MACRO_NUM_DECIMATORS];
+	int pcm_rate[LPASS_CDC_VA_MACRO_NUM_DECIMATORS];
 };
 
 static bool lpass_cdc_va_macro_get_data(struct snd_soc_component *component,
@@ -834,8 +835,29 @@ static void lpass_cdc_va_macro_tx_hpf_corner_freq_callback(
 				hpf_cut_off_freq << 5);
 		snd_soc_component_update_bits(component, hpf_gate_reg,
 					      0x03, 0x02);
-		/* Minimum 1 clk cycle delay is required as per HW spec */
-		usleep_range(1000, 1010);
+		/* Add delay between toggle hpf gate based on sample rate */
+		switch (va_priv->pcm_rate[hpf_work->decimator]) {
+		case 0:
+			usleep_range(125, 130);
+			break;
+		case 1:
+			usleep_range(62, 65);
+			break;
+		case 3:
+			usleep_range(31, 32);
+			break;
+		case 4:
+			usleep_range(20, 21);
+			break;
+		case 5:
+			usleep_range(10, 11);
+			break;
+		case 6:
+			usleep_range(5, 6);
+			break;
+		default:
+			usleep_range(125, 130);
+		}
 		snd_soc_component_update_bits(component, hpf_gate_reg,
 					      0x03, 0x01);
 	} else {
@@ -1085,6 +1107,7 @@ static int lpass_cdc_va_macro_enable_dec(struct snd_soc_dapm_widget *w,
 	u16 tx_gain_ctl_reg;
 	u8 hpf_cut_off_freq;
 	u16 adc_mux_reg = 0;
+	u16 tx_fs_reg = 0;
 	struct device *va_dev = NULL;
 	struct lpass_cdc_va_macro_priv *va_priv = NULL;
 	int hpf_delay = LPASS_CDC_VA_TX_DMIC_HPF_DELAY_MS;
@@ -1109,6 +1132,10 @@ static int lpass_cdc_va_macro_enable_dec(struct snd_soc_dapm_widget *w,
 				LPASS_CDC_VA_MACRO_TX_PATH_OFFSET * decimator;
 	adc_mux_reg = LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1 +
 			LPASS_CDC_VA_MACRO_ADC_MUX_CFG_OFFSET * decimator;
+	tx_fs_reg = LPASS_CDC_VA_TX0_TX_PATH_CTL +
+				LPASS_CDC_VA_MACRO_TX_PATH_OFFSET * decimator;
+	va_priv->pcm_rate[decimator] = (snd_soc_component_read(component,
+				tx_fs_reg) & 0x0F);
 
 	switch (event) {
 	case SND_SOC_DAPM_PRE_PMU: