qcacmn: Fix kernel module check patch warnings in HIF CE files

Fix kernel module check patch warnings in HIF CE files

Change-Id: I5a0d22f8b139e76c33580fe9ef5b01736b2b5735
CRs-fixed: 2033001

hif/src/ce/ce_api.h

@@ -191,7 +191,8 @@ void ce_sendlist_init(struct ce_sendlist *sendlist);
 int ce_sendlist_buf_add(struct ce_sendlist *sendlist,
 		qdf_dma_addr_t buffer,
 		unsigned int nbytes,
-		uint32_t flags, /* OR-ed with internal flags */
+		/* OR-ed with internal flags */
+		uint32_t flags,
 		uint32_t user_flags);
 
 /*
@@ -401,18 +402,23 @@ bool ce_get_rx_pending(struct hif_softc *scn);
 #define CE_ATTR_ENABLE_POLL          0x10 /* poll for residue descriptors */
 #define CE_ATTR_DIAG                 0x20 /* Diag CE */
 
-/* Attributes of an instance of a Copy Engine */
+/**
+ * stuct CE_attr - Attributes of an instance of a Copy Engine
+ * @flags:         CE_ATTR_* values
+ * @priority:      TBD
+ * @src_nentries:  #entries in source ring - Must be a power of 2
+ * @src_sz_max:    Max source send size for this CE. This is also the minimum
+ *                 size of a destination buffer
+ * @dest_nentries: #entries in destination ring - Must be a power of 2
+ * @reserved:      Future Use
+ */
 struct CE_attr {
-	unsigned int flags;         /* CE_ATTR_* values */
-	unsigned int priority;      /* TBD */
-	unsigned int src_nentries;  /* #entries in source ring -
-				     * Must be a power of 2 */
-	unsigned int src_sz_max;    /* Max source send size for this CE.
-				     * This is also the minimum size of
-				     * a destination buffer. */
-	unsigned int dest_nentries; /* #entries in destination ring -
-				     * Must be a power of 2 */
-	void *reserved;             /* Future use */
+	unsigned int flags;
+	unsigned int priority;
+	unsigned int src_nentries;
+	unsigned int src_sz_max;
+	unsigned int dest_nentries;
+	void *reserved;
 };
 
 /*
@@ -465,7 +471,6 @@ static inline void ce_ipa_get_resource(struct CE_handle *ce,
 			 uint32_t *ce_sr_ring_size,
 			 qdf_dma_addr_t *ce_reg_paddr)
 {
-	return;
 }
 #endif /* IPA_OFFLOAD */
 
@@ -484,10 +489,10 @@ bool ce_check_rx_pending(struct CE_state *CE_state);
 void *hif_ce_get_lro_ctx(struct hif_opaque_softc *hif_hdl, int ctx_id);
 #if defined(FEATURE_LRO)
 int ce_lro_flush_cb_register(struct hif_opaque_softc *scn,
-			     void (handler)(void *),
+			     void (handler)(void *arg),
 			     void *(lro_init_handler)(void));
 int ce_lro_flush_cb_deregister(struct hif_opaque_softc *hif_hdl,
-			       void (lro_deinit_cb)(void *));
+			       void (lro_deinit_cb)(void *arg));
 #endif
 struct ce_ops *ce_services_srng(void);
 struct ce_ops *ce_services_legacy(void);

hif/src/ce/ce_bmi.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2017 The Linux Foundation. All rights reserved.
  *
  * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
  *
@@ -95,7 +95,8 @@ void hif_bmi_send_done(struct CE_handle *copyeng, void *ce_context,
 	transaction->bmi_transaction_flags |= BMI_REQ_SEND_DONE;
 
 	/* resp is't needed or has already been received,
-	 * never assume resp comes later then this */
+	 * never assume resp comes later then this
+	 */
 	if (!transaction->bmi_response_CE ||
 	    (transaction->bmi_transaction_flags & BMI_RESP_RECV_DONE)) {
 		qdf_semaphore_release(&transaction->bmi_transaction_sem);
@@ -116,9 +117,8 @@ void hif_bmi_recv_data(struct CE_handle *copyeng, void *ce_context,
 	transaction->bmi_transaction_flags |= BMI_RESP_RECV_DONE;
 
 	/* when both send/recv are done, the sem can be released */
-	if (transaction->bmi_transaction_flags & BMI_REQ_SEND_DONE) {
+	if (transaction->bmi_transaction_flags & BMI_REQ_SEND_DONE)
 		qdf_semaphore_release(&transaction->bmi_transaction_sem);
-	}
 }
 #endif
 
@@ -192,7 +192,8 @@ QDF_STATUS hif_exchange_bmi_msg(struct hif_opaque_softc *hif_ctx,
 		transaction->bmi_response_host = bmi_response;
 		transaction->bmi_response_CE = CE_response;
 		/* dma_cache_sync(dev, bmi_response,
-		    BMI_DATASZ_MAX, DMA_FROM_DEVICE); */
+		 *      BMI_DATASZ_MAX, DMA_FROM_DEVICE);
+		 */
 		qdf_mem_dma_sync_single_for_device(scn->qdf_dev,
 					       CE_response,
 					       BMI_DATASZ_MAX,
@@ -220,7 +221,8 @@ QDF_STATUS hif_exchange_bmi_msg(struct hif_opaque_softc *hif_ctx,
 
 	/* Wait for BMI request/response transaction to complete */
 	/* Always just wait for BMI request here if
-	 * BMI_RSP_POLLING is defined */
+	 * BMI_RSP_POLLING is defined
+	 */
 	while (qdf_semaphore_acquire
 		       (&transaction->bmi_transaction_sem)) {
 		/*need some break out condition(time out?) */
@@ -258,10 +260,11 @@ QDF_STATUS hif_exchange_bmi_msg(struct hif_opaque_softc *hif_ctx,
 	}
 
 	/* dma_unmap_single(dev, transaction->bmi_request_CE,
-		request_length, DMA_TO_DEVICE); */
-	/* bus_unmap_single(scn->sc_osdev,
-		 transaction->bmi_request_CE,
-		request_length, BUS_DMA_TODEVICE); */
+	 *     request_length, DMA_TO_DEVICE);
+	 * bus_unmap_single(scn->sc_osdev,
+	 *     transaction->bmi_request_CE,
+	 *     request_length, BUS_DMA_TODEVICE);
+	 */
 
 	if (status != QDF_STATUS_SUCCESS) {
 		qdf_dma_addr_t unused_buffer;

hif/src/ce/ce_diag.c

@@ -256,7 +256,8 @@ QDF_STATUS hif_diag_read_mem(struct hif_opaque_softc *hif_ctx,
 		}
 
 		/* Request CE to send from Target(!)
-		 * address to Host buffer */
+		 * address to Host buffer
+		 */
 		status = ce_send(ce_diag, NULL, ce_phy_addr, nbytes,
 				transaction_id, 0, user_flags);
 		if (status != QDF_STATUS_SUCCESS)
@@ -498,7 +499,7 @@ done:
 	}
 
 	if (status != QDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s failure (0x%llu)", __func__,
+		HIF_ERROR("%s failure (0x%llx)", __func__,
 			(uint64_t)ce_phy_addr);
 	}
 

hif/src/ce/ce_internal.h

@@ -136,14 +136,13 @@ struct CE_state {
 	atomic_t rx_pending;
 
 	qdf_spinlock_t ce_index_lock;
-	bool force_break;	/* Flag to indicate whether to
-				 * break out the DPC context */
+	/* Flag to indicate whether to break out the DPC context */
+	bool force_break;
 
 	/* time in nanoseconds to yield control of napi poll */
 	unsigned long long ce_service_yield_time;
-	unsigned int receive_count;	/* count Num Of Receive Buffers
-					 * handled for one interrupt
-					 * DPC routine */
+	/* Num Of Receive Buffers handled for one interrupt DPC routine */
+	unsigned int receive_count;
 	/* epping */
 	bool timer_inited;
 	qdf_timer_t poll_timer;
@@ -476,7 +475,8 @@ struct ce_sendlist_s {
 			unsigned int ndesc;     /* Rx descriptor list */
 		} u;
 		/* flags: externally-specified flags;
-		 * OR-ed with internal flags */
+		 * OR-ed with internal flags
+		 */
 		uint32_t flags;
 		uint32_t user_flags;
 	} item[CE_SENDLIST_ITEMS_MAX];

hif/src/ce/ce_main.c

@@ -141,6 +141,7 @@ void hif_trigger_dump(struct hif_opaque_softc *hif_ctx,
 static void ce_poll_timeout(void *arg)
 {
 	struct CE_state *CE_state = (struct CE_state *)arg;
+
 	if (CE_state->timer_inited) {
 		ce_per_engine_service(CE_state->scn, CE_state->id);
 		qdf_timer_mod(&CE_state->poll_timer, CE_POLL_TIMEOUT);
@@ -782,7 +783,8 @@ static void ce_ring_setup(struct hif_softc *scn, uint8_t ring_type,
 {
 	struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
 
-	hif_state->ce_services->ce_ring_setup(scn, ring_type, ce_id, ring, attr);
+	hif_state->ce_services->ce_ring_setup(scn, ring_type, ce_id,
+					      ring, attr);
 }
 
 int hif_ce_bus_early_suspend(struct hif_softc *scn)
@@ -790,6 +792,7 @@ int hif_ce_bus_early_suspend(struct hif_softc *scn)
 	uint8_t ul_pipe, dl_pipe;
 	int ce_id, status, ul_is_polled, dl_is_polled;
 	struct CE_state *ce_state;
+
 	status = hif_map_service_to_pipe(&scn->osc, WMI_CONTROL_SVC,
 					 &ul_pipe, &dl_pipe,
 					 &ul_is_polled, &dl_is_polled);
@@ -926,6 +929,7 @@ struct CE_handle *ce_init(struct hif_softc *scn,
 	nentries = attr->src_nentries;
 	if (nentries) {
 		struct CE_ring_state *src_ring;
+
 		nentries = roundup_pwr2(nentries);
 		if (CE_state->src_ring) {
 			QDF_ASSERT(CE_state->src_ring->nentries == nentries);
@@ -946,13 +950,12 @@ struct CE_handle *ce_init(struct hif_softc *scn,
 					malloc_CE_state = false;
 				}
 				return NULL;
-			} else {
-				/* we can allocate src ring.
-				 * Mark that the src ring is
-				 * allocated locally
-				 */
-				malloc_src_ring = true;
 			}
+			/* we can allocate src ring. Mark that the src ring is
+			 * allocated locally
+			 */
+			malloc_src_ring = true;
+
 			/*
 			 * Also allocate a shadow src ring in
 			 * regular mem to use for faster access.
@@ -1009,7 +1012,8 @@ struct CE_handle *ce_init(struct hif_softc *scn,
 			if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
 				goto error_target_access;
 
-			ce_ring_setup(scn, CE_RING_DEST, CE_id, dest_ring, attr);
+			ce_ring_setup(scn, CE_RING_DEST, CE_id,
+				      dest_ring, attr);
 
 			if (Q_TARGET_ACCESS_END(scn) < 0)
 				goto error_target_access;
@@ -1157,13 +1161,13 @@ void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int id)
  *
  * Return: none
  */
-void
-ce_h2t_tx_ce_cleanup(struct CE_handle *ce_hdl)
+void ce_h2t_tx_ce_cleanup(struct CE_handle *ce_hdl)
 {
 	struct CE_state *ce_state = (struct CE_state *)ce_hdl;
 	struct CE_ring_state *src_ring = ce_state->src_ring;
 	struct hif_softc *sc = ce_state->scn;
 	uint32_t sw_index, write_index;
+
 	if (hif_is_nss_wifi_enabled(sc))
 		return;
 
@@ -1467,9 +1471,9 @@ void hif_send_complete_check(struct hif_opaque_softc *hif_ctx, uint8_t pipe,
 		 * If at least 50% of the total resources are still available,
 		 * don't bother checking again yet.
 		 */
-		if (resources > (hif_state->host_ce_config[pipe].src_nentries >> 1)) {
+		if (resources > (hif_state->host_ce_config[pipe].src_nentries >>
+									 1))
 			return;
-		}
 	}
 #if ATH_11AC_TXCOMPACT
 	ce_per_engine_servicereap(scn, pipe);
@@ -1599,7 +1603,8 @@ hif_pci_ce_recv_data(struct CE_handle *copyeng, void *ce_context,
 				nbytes, pipe_info);
 
 		/* Set up force_break flag if num of receices reaches
-		 * MAX_NUM_OF_RECEIVES */
+		 * MAX_NUM_OF_RECEIVES
+		 */
 		ce_state->receive_count++;
 		if (qdf_unlikely(hif_ce_service_should_yield(scn, ce_state))) {
 			ce_state->force_break = 1;
@@ -1656,9 +1661,8 @@ static int hif_completion_thread_startup(struct HIF_CE_state *hif_state)
 		struct HIF_CE_pipe_info *pipe_info;
 
 		pipe_info = &hif_state->pipe_info[pipe_num];
-		if (pipe_info->ce_hdl == ce_diag) {
+		if (pipe_info->ce_hdl == ce_diag)
 			continue;       /* Handle Diagnostic CE specially */
-		}
 		attr = hif_state->host_ce_config[pipe_num];
 		if (attr.src_nentries) {
 			/* pipe used to send to target */
@@ -1881,13 +1885,13 @@ static int hif_post_recv_buffers(struct hif_softc *scn)
 	A_TARGET_ACCESS_LIKELY(scn);
 	for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) {
 		struct HIF_CE_pipe_info *pipe_info;
+
 		ce_state = scn->ce_id_to_state[pipe_num];
 		pipe_info = &hif_state->pipe_info[pipe_num];
 
 		if (hif_is_nss_wifi_enabled(scn) &&
-		    ce_state && (ce_state->htt_rx_data)) {
+		    ce_state && (ce_state->htt_rx_data))
 			continue;
-		}
 
 		if (hif_post_recv_buffers_for_pipe(pipe_info)) {
 			rv = 1;
@@ -1937,22 +1941,20 @@ static void hif_recv_buffer_cleanup_on_pipe(struct HIF_CE_pipe_info *pipe_info)
 	void *per_CE_context;
 
 	buf_sz = pipe_info->buf_sz;
-	if (buf_sz == 0) {
-		/* Unused Copy Engine */
+	/* Unused Copy Engine */
+	if (buf_sz == 0)
 		return;
-	}
+
 
 	hif_state = pipe_info->HIF_CE_state;
-	if (!hif_state->started) {
+	if (!hif_state->started)
 		return;
-	}
 
 	scn = HIF_GET_SOFTC(hif_state);
 	ce_hdl = pipe_info->ce_hdl;
 
-	if (scn->qdf_dev == NULL) {
+	if (scn->qdf_dev == NULL)
 		return;
-	}
 	while (ce_revoke_recv_next
 		       (ce_hdl, &per_CE_context, (void **)&netbuf,
 			&CE_data) == QDF_STATUS_SUCCESS) {
@@ -2006,9 +2008,9 @@ static void hif_send_buffer_cleanup_on_pipe(struct HIF_CE_pipe_info *pipe_info)
 			if (id == scn->htc_htt_tx_endpoint)
 				return;
 			/* Indicate the completion to higher
-			 * layer to free the buffer */
-			if (pipe_info->pipe_callbacks.
-					txCompletionHandler)
+			 * layer to free the buffer
+			 */
+			if (pipe_info->pipe_callbacks.txCompletionHandler)
 				pipe_info->pipe_callbacks.
 				    txCompletionHandler(pipe_info->
 					    pipe_callbacks.Context,
@@ -2403,7 +2405,6 @@ static void hif_post_static_buf_to_target(struct hif_softc *scn)
 #else
 static inline void hif_post_static_buf_to_target(struct hif_softc *scn)
 {
-	return;
 }
 #endif
 
@@ -2450,6 +2451,7 @@ int hif_config_ce(struct hif_softc *scn)
 
 	for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) {
 		struct CE_attr *attr;
+
 		pipe_info = &hif_state->pipe_info[pipe_num];
 		pipe_info->pipe_num = pipe_num;
 		pipe_info->HIF_CE_state = hif_state;
@@ -2467,7 +2469,8 @@ int hif_config_ce(struct hif_softc *scn)
 
 		if (attr->flags & CE_ATTR_DIAG) {
 			/* Reserve the ultimate CE for
-			 * Diagnostic Window support */
+			 * Diagnostic Window support
+			 */
 			hif_state->ce_diag = pipe_info->ce_hdl;
 			continue;
 		}
@@ -2586,7 +2589,6 @@ void hif_ce_ipa_get_ce_resource(struct hif_softc *scn,
 
 	ce_ipa_get_resource(ce_hdl, ce_sr_base_paddr, ce_sr_ring_size,
 			    ce_reg_paddr);
-	return;
 }
 #endif /* IPA_OFFLOAD */
 
@@ -2594,71 +2596,71 @@ void hif_ce_ipa_get_ce_resource(struct hif_softc *scn,
 #ifdef ADRASTEA_SHADOW_REGISTERS
 
 /*
-	Current shadow register config
-
-	-----------------------------------------------------------
-	Shadow Register      |     CE   |    src/dst write index
-	-----------------------------------------------------------
-		0            |     0    |           src
-		1     No Config - Doesn't point to anything
-		2     No Config - Doesn't point to anything
-		3            |     3    |           src
-		4            |     4    |           src
-		5            |     5    |           src
-		6     No Config - Doesn't point to anything
-		7            |     7    |           src
-		8     No Config - Doesn't point to anything
-		9     No Config - Doesn't point to anything
-		10    No Config - Doesn't point to anything
-		11    No Config - Doesn't point to anything
-	-----------------------------------------------------------
-		12    No Config - Doesn't point to anything
-		13           |     1    |           dst
-		14           |     2    |           dst
-		15    No Config - Doesn't point to anything
-		16    No Config - Doesn't point to anything
-		17    No Config - Doesn't point to anything
-		18    No Config - Doesn't point to anything
-		19           |     7    |           dst
-		20           |     8    |           dst
-		21    No Config - Doesn't point to anything
-		22    No Config - Doesn't point to anything
-		23    No Config - Doesn't point to anything
-	-----------------------------------------------------------
-
-
-	ToDo - Move shadow register config to following in the future
-	This helps free up a block of shadow registers towards the end.
-	Can be used for other purposes
-
-	-----------------------------------------------------------
-	Shadow Register      |     CE   |    src/dst write index
-	-----------------------------------------------------------
-		0            |     0    |           src
-		1            |     3    |           src
-		2            |     4    |           src
-		3            |     5    |           src
-		4            |     7    |           src
-	-----------------------------------------------------------
-		5            |     1    |           dst
-		6            |     2    |           dst
-		7            |     7    |           dst
-		8            |     8    |           dst
-	-----------------------------------------------------------
-		9     No Config - Doesn't point to anything
-		12    No Config - Doesn't point to anything
-		13    No Config - Doesn't point to anything
-		14    No Config - Doesn't point to anything
-		15    No Config - Doesn't point to anything
-		16    No Config - Doesn't point to anything
-		17    No Config - Doesn't point to anything
-		18    No Config - Doesn't point to anything
-		19    No Config - Doesn't point to anything
-		20    No Config - Doesn't point to anything
-		21    No Config - Doesn't point to anything
-		22    No Config - Doesn't point to anything
-		23    No Config - Doesn't point to anything
-	-----------------------------------------------------------
+ * Current shadow register config
+ *
+ * -----------------------------------------------------------
+ * Shadow Register      |     CE   |    src/dst write index
+ * -----------------------------------------------------------
+ *         0            |     0    |           src
+ *         1     No Config - Doesn't point to anything
+ *         2     No Config - Doesn't point to anything
+ *         3            |     3    |           src
+ *         4            |     4    |           src
+ *         5            |     5    |           src
+ *         6     No Config - Doesn't point to anything
+ *         7            |     7    |           src
+ *         8     No Config - Doesn't point to anything
+ *         9     No Config - Doesn't point to anything
+ *         10    No Config - Doesn't point to anything
+ *         11    No Config - Doesn't point to anything
+ * -----------------------------------------------------------
+ *         12    No Config - Doesn't point to anything
+ *         13           |     1    |           dst
+ *         14           |     2    |           dst
+ *         15    No Config - Doesn't point to anything
+ *         16    No Config - Doesn't point to anything
+ *         17    No Config - Doesn't point to anything
+ *         18    No Config - Doesn't point to anything
+ *         19           |     7    |           dst
+ *         20           |     8    |           dst
+ *         21    No Config - Doesn't point to anything
+ *         22    No Config - Doesn't point to anything
+ *         23    No Config - Doesn't point to anything
+ * -----------------------------------------------------------
+ *
+ *
+ * ToDo - Move shadow register config to following in the future
+ * This helps free up a block of shadow registers towards the end.
+ * Can be used for other purposes
+ *
+ * -----------------------------------------------------------
+ * Shadow Register      |     CE   |    src/dst write index
+ * -----------------------------------------------------------
+ *      0            |     0    |           src
+ *      1            |     3    |           src
+ *      2            |     4    |           src
+ *      3            |     5    |           src
+ *      4            |     7    |           src
+ * -----------------------------------------------------------
+ *      5            |     1    |           dst
+ *      6            |     2    |           dst
+ *      7            |     7    |           dst
+ *      8            |     8    |           dst
+ * -----------------------------------------------------------
+ *      9     No Config - Doesn't point to anything
+ *      12    No Config - Doesn't point to anything
+ *      13    No Config - Doesn't point to anything
+ *      14    No Config - Doesn't point to anything
+ *      15    No Config - Doesn't point to anything
+ *      16    No Config - Doesn't point to anything
+ *      17    No Config - Doesn't point to anything
+ *      18    No Config - Doesn't point to anything
+ *      19    No Config - Doesn't point to anything
+ *      20    No Config - Doesn't point to anything
+ *      21    No Config - Doesn't point to anything
+ *      22    No Config - Doesn't point to anything
+ *      23    No Config - Doesn't point to anything
+ * -----------------------------------------------------------
 */
 
 u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr)
@@ -2999,6 +3001,7 @@ static inline void hif_config_rri_on_ddr(struct hif_softc *scn)
 	unsigned int i;
 	qdf_dma_addr_t paddr_rri_on_ddr;
 	uint32_t high_paddr, low_paddr;
+
 	scn->vaddr_rri_on_ddr =
 		(uint32_t *)qdf_mem_alloc_consistent(scn->qdf_dev,
 		scn->qdf_dev->dev, (CE_COUNT*sizeof(uint32_t)),
@@ -3017,7 +3020,6 @@ static inline void hif_config_rri_on_ddr(struct hif_softc *scn)
 
 	qdf_mem_zero(scn->vaddr_rri_on_ddr, CE_COUNT*sizeof(uint32_t));
 
-	return;
 }
 #else
 
@@ -3033,7 +3035,6 @@ static inline void hif_config_rri_on_ddr(struct hif_softc *scn)
  */
 static inline void hif_config_rri_on_ddr(struct hif_softc *scn)
 {
-	return;
 }
 #endif
 
@@ -3065,8 +3066,8 @@ int hif_dump_ce_registers(struct hif_softc *scn)
 					   ce_reg_word_size * sizeof(uint32_t));
 
 		if (status != QDF_STATUS_SUCCESS) {
-				HIF_ERROR("Dumping CE register failed!");
-				return -EACCES;
+			HIF_ERROR("Dumping CE register failed!");
+			return -EACCES;
 		}
 		HIF_ERROR("CE%d=>\n", i);
 		qdf_trace_hex_dump(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_DEBUG,

hif/src/ce/ce_main.h

@@ -207,7 +207,6 @@ void hif_ce_ipa_get_ce_resource(struct hif_softc *scn,
 			     uint32_t *ce_sr_ring_size,
 			     qdf_dma_addr_t *ce_reg_paddr)
 {
-	return;
 }
 
 #endif

hif/src/ce/ce_reg.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2017 The Linux Foundation. All rights reserved.
  *
  * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
  *
@@ -40,56 +40,71 @@
 #define CURRENT_SRRI_ADDRESS    (scn->target_ce_def->d_CURRENT_SRRI_ADDRESS)
 #define CURRENT_DRRI_ADDRESS    (scn->target_ce_def->d_CURRENT_DRRI_ADDRESS)
 
-#define SHADOW_VALUE0           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_0)
-#define SHADOW_VALUE1           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_1)
-#define SHADOW_VALUE2           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_2)
-#define SHADOW_VALUE3           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_3)
-#define SHADOW_VALUE4           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_4)
-#define SHADOW_VALUE5           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_5)
-#define SHADOW_VALUE6           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_6)
-#define SHADOW_VALUE7           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_7)
-#define SHADOW_VALUE8           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_8)
-#define SHADOW_VALUE9           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_9)
-#define SHADOW_VALUE10          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_10)
-#define SHADOW_VALUE11          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_11)
-#define SHADOW_VALUE12          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_12)
-#define SHADOW_VALUE13          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_13)
-#define SHADOW_VALUE14          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_14)
-#define SHADOW_VALUE15          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_15)
-#define SHADOW_VALUE16          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_16)
-#define SHADOW_VALUE17          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_17)
-#define SHADOW_VALUE18          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_18)
-#define SHADOW_VALUE19          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_19)
-#define SHADOW_VALUE20          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_20)
-#define SHADOW_VALUE21          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_21)
-#define SHADOW_VALUE22          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_22)
-#define SHADOW_VALUE23          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_23)
-#define SHADOW_ADDRESS0         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_0)
-#define SHADOW_ADDRESS1         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_1)
-#define SHADOW_ADDRESS2         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_2)
-#define SHADOW_ADDRESS3         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_3)
-#define SHADOW_ADDRESS4         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_4)
-#define SHADOW_ADDRESS5         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_5)
-#define SHADOW_ADDRESS6         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_6)
-#define SHADOW_ADDRESS7         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_7)
-#define SHADOW_ADDRESS8         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_8)
-#define SHADOW_ADDRESS9         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_9)
-#define SHADOW_ADDRESS10        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_10)
-#define SHADOW_ADDRESS11        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_11)
-#define SHADOW_ADDRESS12        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_12)
-#define SHADOW_ADDRESS13        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_13)
-#define SHADOW_ADDRESS14        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_14)
-#define SHADOW_ADDRESS15        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_15)
-#define SHADOW_ADDRESS16        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_16)
-#define SHADOW_ADDRESS17        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_17)
-#define SHADOW_ADDRESS18        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_18)
-#define SHADOW_ADDRESS19        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_19)
-#define SHADOW_ADDRESS20        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_20)
-#define SHADOW_ADDRESS21        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_21)
-#define SHADOW_ADDRESS22        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_22)
-#define SHADOW_ADDRESS23        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_23)
-
-#define SHADOW_ADDRESS(i) (SHADOW_ADDRESS0 + i*(SHADOW_ADDRESS1-SHADOW_ADDRESS0))
+#define SHADOW_VALUE0    (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_0)
+#define SHADOW_VALUE1    (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_1)
+#define SHADOW_VALUE2    (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_2)
+#define SHADOW_VALUE3    (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_3)
+#define SHADOW_VALUE4    (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_4)
+#define SHADOW_VALUE5    (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_5)
+#define SHADOW_VALUE6    (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_6)
+#define SHADOW_VALUE7    (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_7)
+#define SHADOW_VALUE8    (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_8)
+#define SHADOW_VALUE9    (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_9)
+#define SHADOW_VALUE10   (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_10)
+#define SHADOW_VALUE11   (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_11)
+#define SHADOW_VALUE12   (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_12)
+#define SHADOW_VALUE13   (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_13)
+#define SHADOW_VALUE14   (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_14)
+#define SHADOW_VALUE15   (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_15)
+#define SHADOW_VALUE16   (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_16)
+#define SHADOW_VALUE17   (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_17)
+#define SHADOW_VALUE18   (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_18)
+#define SHADOW_VALUE19   (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_19)
+#define SHADOW_VALUE20   (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_20)
+#define SHADOW_VALUE21   (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_21)
+#define SHADOW_VALUE22   (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_22)
+#define SHADOW_VALUE23   (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_23)
+#define SHADOW_ADDRESS0  (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_0)
+#define SHADOW_ADDRESS1  (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_1)
+#define SHADOW_ADDRESS2  (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_2)
+#define SHADOW_ADDRESS3  (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_3)
+#define SHADOW_ADDRESS4  (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_4)
+#define SHADOW_ADDRESS5  (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_5)
+#define SHADOW_ADDRESS6  (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_6)
+#define SHADOW_ADDRESS7  (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_7)
+#define SHADOW_ADDRESS8  (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_8)
+#define SHADOW_ADDRESS9  (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_9)
+#define SHADOW_ADDRESS10 \
+			(scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_10)
+#define SHADOW_ADDRESS11 \
+			(scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_11)
+#define SHADOW_ADDRESS12 \
+			(scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_12)
+#define SHADOW_ADDRESS13 \
+			(scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_13)
+#define SHADOW_ADDRESS14 \
+			(scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_14)
+#define SHADOW_ADDRESS15 \
+			(scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_15)
+#define SHADOW_ADDRESS16 \
+			(scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_16)
+#define SHADOW_ADDRESS17 \
+			(scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_17)
+#define SHADOW_ADDRESS18 \
+			(scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_18)
+#define SHADOW_ADDRESS19 \
+			(scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_19)
+#define SHADOW_ADDRESS20 \
+			(scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_20)
+#define SHADOW_ADDRESS21 \
+			(scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_21)
+#define SHADOW_ADDRESS22 \
+			(scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_22)
+#define SHADOW_ADDRESS23 \
+			(scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_23)
+
+#define SHADOW_ADDRESS(i) \
+			(SHADOW_ADDRESS0 + i*(SHADOW_ADDRESS1-SHADOW_ADDRESS0))
 
 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \
 	(scn->target_ce_def->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK)
@@ -145,7 +160,8 @@
 	(scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK)
 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB  \
 	(scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
-#define CE_CTRL1_DMAX_LENGTH_LSB  (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_LSB)
+#define CE_CTRL1_DMAX_LENGTH_LSB \
+				(scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_LSB)
 #define CE_CTRL1_IDX_UPD_EN  (scn->target_ce_def->d_CE_CTRL1_IDX_UPD_EN_MASK)
 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \
 	(scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
@@ -184,10 +200,14 @@
 #define AMBA_DEBUG_BUS_SEL_MSB    (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB)
 #define AMBA_DEBUG_BUS_SEL_LSB    (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB)
 #define AMBA_DEBUG_BUS_SEL_MASK   (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK)
-#define CE_WRAPPER_DEBUG_OFFSET   (scn->target_ce_def->d_CE_WRAPPER_DEBUG_OFFSET)
-#define CE_WRAPPER_DEBUG_SEL_MSB  (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MSB)
-#define CE_WRAPPER_DEBUG_SEL_LSB  (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_LSB)
-#define CE_WRAPPER_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MASK)
+#define CE_WRAPPER_DEBUG_OFFSET   \
+				(scn->target_ce_def->d_CE_WRAPPER_DEBUG_OFFSET)
+#define CE_WRAPPER_DEBUG_SEL_MSB  \
+				(scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MSB)
+#define CE_WRAPPER_DEBUG_SEL_LSB  \
+				(scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_LSB)
+#define CE_WRAPPER_DEBUG_SEL_MASK \
+			(scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MASK)
 #define CE_DEBUG_OFFSET           (scn->target_ce_def->d_CE_DEBUG_OFFSET)
 #define CE_DEBUG_SEL_MSB          (scn->target_ce_def->d_CE_DEBUG_SEL_MSB)
 #define CE_DEBUG_SEL_LSB          (scn->target_ce_def->d_CE_DEBUG_SEL_LSB)

hif/src/ce/ce_service.c

@@ -137,6 +137,7 @@ struct hif_ce_desc_event hif_ce_desc_history[CE_COUNT_MAX][HIF_CE_HISTORY_MAX];
 static int get_next_record_index(qdf_atomic_t *table_index, int array_size)
 {
 	int record_index = qdf_atomic_inc_return(table_index);
+
 	if (record_index == array_size)
 		qdf_atomic_sub(array_size, table_index);
 
@@ -295,6 +296,7 @@ void war_ce_src_ring_write_idx_set(struct hif_softc *scn,
 				      (CDC_WAR_MAGIC_STR | write_index));
 		} else {
 			unsigned long irq_flags;
+
 			local_irq_save(irq_flags);
 			hif_write32_mb(indicator_addr, 1);
 
@@ -467,6 +469,7 @@ unsigned int ce_sendlist_sizeof(void)
 void ce_sendlist_init(struct ce_sendlist *sendlist)
 {
 	struct ce_sendlist_s *sl = (struct ce_sendlist_s *)sendlist;
+
 	sl->num_items = 0;
 }
 
@@ -1292,9 +1295,8 @@ ce_completed_recv_next_nolock_legacy(struct CE_state *CE_state,
 	*transfer_idp = dest_desc_info.meta_data;
 	*flagsp = (dest_desc_info.byte_swap) ? CE_RECV_FLAG_SWAPPED : 0;
 
-	if (per_CE_contextp) {
+	if (per_CE_contextp)
 		*per_CE_contextp = CE_state->recv_context;
-	}
 
 	if (per_transfer_contextp) {
 		*per_transfer_contextp =
@@ -1363,9 +1365,8 @@ ce_revoke_recv_next_legacy(struct CE_handle *copyeng,
 
 	CE_state = (struct CE_state *)copyeng;
 	dest_ring = CE_state->dest_ring;
-	if (!dest_ring) {
+	if (!dest_ring)
 		return QDF_STATUS_E_FAILURE;
-	}
 
 	scn = CE_state->scn;
 	qdf_spin_lock(&CE_state->ce_index_lock);
@@ -1382,9 +1383,8 @@ ce_revoke_recv_next_legacy(struct CE_handle *copyeng,
 		/* Return data from completed destination descriptor */
 		*bufferp = HIF_CE_DESC_ADDR_TO_DMA(dest_desc);
 
-		if (per_CE_contextp) {
+		if (per_CE_contextp)
 			*per_CE_contextp = CE_state->recv_context;
-		}
 
 		if (per_transfer_contextp) {
 			*per_transfer_contextp =
@@ -1476,9 +1476,8 @@ ce_completed_send_next_nolock_legacy(struct CE_state *CE_state,
 #else
 		*toeplitz_hash_result = 0;
 #endif
-		if (per_CE_contextp) {
+		if (per_CE_contextp)
 			*per_CE_contextp = CE_state->send_context;
-		}
 
 		if (per_transfer_contextp) {
 			*per_transfer_contextp =
@@ -1532,9 +1531,8 @@ ce_cancel_send_next_legacy(struct CE_handle *copyeng,
 
 	CE_state = (struct CE_state *)copyeng;
 	src_ring = CE_state->src_ring;
-	if (!src_ring) {
+	if (!src_ring)
 		return QDF_STATUS_E_FAILURE;
-	}
 
 	scn = CE_state->scn;
 	qdf_spin_lock(&CE_state->ce_index_lock);
@@ -1558,9 +1556,8 @@ ce_cancel_send_next_legacy(struct CE_handle *copyeng,
 		*toeplitz_hash_result = 0;
 #endif
 
-		if (per_CE_contextp) {
+		if (per_CE_contextp)
 			*per_CE_contextp = CE_state->send_context;
-		}
 
 		if (per_transfer_contextp) {
 			*per_transfer_contextp =
@@ -1749,7 +1746,7 @@ static void ce_fastpath_rx_handle(struct CE_state *ce_state,
 
 #define MSG_FLUSH_NUM 32
 /**
- * ce_per_engine_service_fast() - CE handler routine to service fastpath messages
+ * ce_per_engine_service_fast() - CE handler routine to service fastpath msgs
  * @scn: hif_context
  * @ce_id: Copy engine ID
  * 1) Go through the CE ring, and find the completions
@@ -2165,6 +2162,7 @@ void ce_per_engine_service_any(int irq, struct hif_softc *scn)
 	if (!qdf_atomic_read(&scn->tasklet_from_intr)) {
 		for (CE_id = 0; CE_id < scn->ce_count; CE_id++) {
 			struct CE_state *CE_state = scn->ce_id_to_state[CE_id];
+
 			if (qdf_atomic_read(&CE_state->rx_pending)) {
 				qdf_atomic_set(&CE_state->rx_pending, 0);
 				ce_per_engine_service(scn, CE_id);
@@ -2178,11 +2176,10 @@ void ce_per_engine_service_any(int irq, struct hif_softc *scn)
 	intr_summary = CE_INTERRUPT_SUMMARY(scn);
 
 	for (CE_id = 0; intr_summary && (CE_id < scn->ce_count); CE_id++) {
-		if (intr_summary & (1 << CE_id)) {
+		if (intr_summary & (1 << CE_id))
 			intr_summary &= ~(1 << CE_id);
-		} else {
+		else
 			continue;       /* no intr pending on this CE */
-		}
 
 		ce_per_engine_service(scn, CE_id);
 	}
@@ -2210,17 +2207,15 @@ ce_per_engine_handler_adjust_legacy(struct CE_state *CE_state,
 		return;
 
 	if ((!disable_copy_compl_intr) &&
-	    (CE_state->send_cb || CE_state->recv_cb)) {
+	    (CE_state->send_cb || CE_state->recv_cb))
 		CE_COPY_COMPLETE_INTR_ENABLE(scn, ctrl_addr);
-	} else {
+	else
 		CE_COPY_COMPLETE_INTR_DISABLE(scn, ctrl_addr);
-	}
 
-	if (CE_state->watermark_cb) {
+	if (CE_state->watermark_cb)
 		CE_WATERMARK_INTR_ENABLE(scn, ctrl_addr);
-	} else {
+	 else
 		CE_WATERMARK_INTR_DISABLE(scn, ctrl_addr);
-	}
 	Q_TARGET_ACCESS_END(scn);
 }
 
@@ -2240,13 +2235,11 @@ void ce_disable_any_copy_compl_intr_nolock(struct hif_softc *scn)
 
 		/* if the interrupt is currently enabled, disable it */
 		if (!CE_state->disable_copy_compl_intr
-		    && (CE_state->send_cb || CE_state->recv_cb)) {
+		    && (CE_state->send_cb || CE_state->recv_cb))
 			CE_COPY_COMPLETE_INTR_DISABLE(scn, ctrl_addr);
-		}
 
-		if (CE_state->watermark_cb) {
+		if (CE_state->watermark_cb)
 			CE_WATERMARK_INTR_DISABLE(scn, ctrl_addr);
-		}
 	}
 	Q_TARGET_ACCESS_END(scn);
 }
@@ -2268,13 +2261,11 @@ void ce_enable_any_copy_compl_intr_nolock(struct hif_softc *scn)
 		 * "disable" flag is not set), then re-enable the interrupt.
 		 */
 		if (!CE_state->disable_copy_compl_intr
-		    && (CE_state->send_cb || CE_state->recv_cb)) {
+		    && (CE_state->send_cb || CE_state->recv_cb))
 			CE_COPY_COMPLETE_INTR_ENABLE(scn, ctrl_addr);
-		}
 
-		if (CE_state->watermark_cb) {
+		if (CE_state->watermark_cb)
 			CE_WATERMARK_INTR_ENABLE(scn, ctrl_addr);
-		}
 	}
 	Q_TARGET_ACCESS_END(scn);
 }
@@ -2375,9 +2366,8 @@ ce_watermark_cb_register(struct CE_handle *copyeng,
 	CE_state->wm_context = CE_wm_context;
 	hif_state->ce_services->ce_per_engine_handler_adjust(CE_state,
 							0);
-	if (fn_ptr) {
+	if (fn_ptr)
 		CE_state->misc_cbs = 1;
-	}
 }
 
 bool ce_get_rx_pending(struct hif_softc *scn)
@@ -2386,6 +2376,7 @@ bool ce_get_rx_pending(struct hif_softc *scn)
 
 	for (CE_id = 0; CE_id < scn->ce_count; CE_id++) {
 		struct CE_state *CE_state = scn->ce_id_to_state[CE_id];
+
 		if (qdf_atomic_read(&CE_state->rx_pending))
 			return true;
 	}
@@ -2458,7 +2449,6 @@ void ce_ipa_get_resource(struct CE_handle *ce,
 		sizeof(struct CE_src_desc));
 	*ce_reg_paddr = phy_mem_base + CE_BASE_ADDRESS(CE_state->id) +
 			SR_WR_INDEX_ADDRESS;
-	return;
 }
 #endif /* IPA_OFFLOAD */
 

hif/src/ce/ce_tasklet.c

@@ -83,7 +83,6 @@ static void reschedule_ce_tasklet_work_handler(struct work_struct *work)
 		return;
 	}
 	tasklet_schedule(&hif_ce_state->tasklets[ce_work->id].intr_tq);
-	return;
 }
 
 static struct tasklet_work tasklet_workers[CE_ID_MAX];
@@ -175,9 +174,8 @@ static void ce_tasklet(unsigned long data)
 	qdf_spin_lock_bh(&CE_state->lro_unloading_lock);
 	ce_per_engine_service(scn, tasklet_entry->ce_id);
 
-	if (CE_state->lro_flush_cb != NULL) {
+	if (CE_state->lro_flush_cb != NULL)
 		CE_state->lro_flush_cb(CE_state->lro_data);
-	}
 	qdf_spin_unlock_bh(&CE_state->lro_unloading_lock);
 
 	if (ce_check_rx_pending(CE_state)) {
@@ -600,9 +598,8 @@ QDF_STATUS ce_register_irq(struct HIF_CE_state *hif_ce_state, uint32_t mask)
 					__func__, id, ret);
 				ce_unregister_irq(hif_ce_state, done_mask);
 				return QDF_STATUS_E_FAULT;
-			} else {
-				done_mask |= 1 << id;
 			}
+			done_mask |= 1 << id;
 		}
 	}
 	hif_ce_state->ce_register_irq_done |= done_mask;