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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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*/
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#include <linux/iopoll.h>
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@@ -54,7 +54,7 @@ static int cam_top_tpg_ver3_process_cmd(void *hw_priv,
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struct cam_top_tpg_hw *tpg_hw;
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struct cam_hw_info *tpg_hw_info;
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struct cam_isp_tpg_core_config *core_cfg;
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- struct cam_top_tpg_cfg *tpg_data;
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+ struct cam_top_tpg_cfg_v2 *tpg_data;
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if (!hw_priv || !cmd_args) {
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CAM_ERR(CAM_ISP, "TPG: Invalid args");
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@@ -63,7 +63,7 @@ static int cam_top_tpg_ver3_process_cmd(void *hw_priv,
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tpg_hw_info = (struct cam_hw_info *)hw_priv;
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tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info;
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- tpg_data = (struct cam_top_tpg_cfg *)tpg_hw->tpg_res.res_priv;
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+ tpg_data = (struct cam_top_tpg_cfg_v2 *)tpg_hw->tpg_res.res_priv;
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switch (cmd_type) {
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case CAM_ISP_HW_CMD_TPG_CORE_CFG_CMD:
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@@ -99,6 +99,104 @@ static int cam_top_tpg_ver3_process_cmd(void *hw_priv,
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return rc;
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}
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+static int cam_top_tpg_ver3_add_append_vc_dt_info(uint32_t *num_active_vcs,
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+ struct cam_top_tpg_vc_dt_info *tpg_vcdt,
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+ struct cam_isp_in_port_generic_info *in_port)
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+{
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+ bool is_dt_saved = false;
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+ int i;
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+ int j;
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+ uint32_t *num_dts;
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+ uint32_t encode_format;
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+ int rc;
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+
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+ for (i = 0; i < in_port->num_valid_vc_dt; i++) {
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+ if (in_port->dt[i] > 0x3f || in_port->vc[i] > 0x1f) {
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+ CAM_ERR(CAM_ISP, "Invalid vc:%d dt %d",
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+ in_port->vc[i],
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+ in_port->dt[i]);
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+ return -EINVAL;
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+ }
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+ rc = cam_top_tpg_get_format(in_port->format, &encode_format);
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+ if (rc)
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+ return rc;
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+
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+ for (j = 0; j < *num_active_vcs; j++) {
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+ if (tpg_vcdt[j].vc_num == in_port->vc[i]) {
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+ num_dts = &tpg_vcdt[j].num_active_dts;
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+ if (*num_dts >=
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+ CAM_TOP_TPG_MAX_SUPPORTED_DT) {
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+ CAM_ERR(CAM_ISP,
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+ "Cannot support more than 4 DTs per VC"
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+ );
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+ return -EINVAL;
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+ }
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+ tpg_vcdt[j].dt_cfg[*num_dts].data_type =
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+ in_port->dt[i];
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+ tpg_vcdt[j].dt_cfg[*num_dts].encode_format =
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+ encode_format;
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+ tpg_vcdt[j].dt_cfg[*num_dts].frame_height =
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+ in_port->height;
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+ if (in_port->usage_type)
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+ tpg_vcdt[j].dt_cfg[*num_dts].frame_width
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+ = ((in_port->right_stop -
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+ in_port->left_start) + 1);
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+ else
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+ tpg_vcdt[j].dt_cfg[*num_dts].frame_width
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+ = in_port->left_width;
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+
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+ CAM_DBG(CAM_ISP,
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+ "vc:%d dt:%d format:%d height:%d width:%d",
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+ in_port->vc[i], in_port->dt[i],
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+ encode_format, in_port->height,
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+ tpg_vcdt[j].dt_cfg[*num_dts].frame_width
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+ );
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+
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+ *num_dts += 1;
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+ is_dt_saved = true;
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+ break;
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+ }
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+ }
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+
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+ if (is_dt_saved == false) {
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+ if (*num_active_vcs >= CAM_TOP_TPG_MAX_SUPPORTED_VC) {
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+ CAM_ERR(CAM_ISP,
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+ "Cannot support more than 4 VCs");
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+ return -EINVAL;
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+ }
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+
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+ tpg_vcdt[*num_active_vcs].vc_num = in_port->vc[i];
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+ tpg_vcdt[*num_active_vcs].dt_cfg[0].data_type =
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+ in_port->dt[i];
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+ tpg_vcdt[*num_active_vcs].dt_cfg[0].encode_format =
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+ encode_format;
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+ tpg_vcdt[*num_active_vcs].dt_cfg[0].frame_height =
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+ in_port->height;
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+
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+ if (in_port->usage_type)
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+ tpg_vcdt[*num_active_vcs].dt_cfg[0].frame_width
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+ = ((in_port->right_stop - in_port->left_start)
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+ + 1);
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+ else
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+ tpg_vcdt[*num_active_vcs].dt_cfg[0].frame_width
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+ = in_port->left_width;
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+
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+ CAM_DBG(CAM_ISP,
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+ "vc:%d dt:%d format:%d height:%d width:%d",
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+ in_port->vc[i], in_port->dt[i],
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+ encode_format, in_port->height,
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+ tpg_vcdt[*num_active_vcs].dt_cfg[0].frame_width
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+ );
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+
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+ tpg_vcdt[*num_active_vcs].num_active_dts++;
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+ *num_active_vcs += 1;
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+ } else {
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+ is_dt_saved = false;
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+ }
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+ }
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+ return 0;
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+}
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+
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static int cam_top_tpg_ver3_reserve(
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void *hw_priv,
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void *reserve_args,
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@@ -107,124 +205,91 @@ static int cam_top_tpg_ver3_reserve(
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int rc = 0;
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struct cam_top_tpg_hw *tpg_hw;
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struct cam_hw_info *tpg_hw_info;
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- struct cam_top_tpg_ver3_reserve_args *reserv;
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- struct cam_top_tpg_cfg *tpg_data;
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- uint32_t encode_format = 0;
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- uint32_t i, num_vc_dt;
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+ struct cam_top_tpg_reserve_args *reserv;
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+ struct cam_top_tpg_cfg_v2 *tpg_data;
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+ uint32_t num_active_vcs = 0;
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+ struct cam_top_tpg_vc_dt_info
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+ in_port_vc_dt[CAM_TOP_TPG_MAX_SUPPORTED_VC];
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+ int i;
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if (!hw_priv || !reserve_args || (arg_size !=
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- sizeof(struct cam_top_tpg_ver3_reserve_args))) {
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+ sizeof(struct cam_top_tpg_reserve_args))) {
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CAM_ERR(CAM_ISP, "TPG: Invalid args");
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return -EINVAL;
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}
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tpg_hw_info = (struct cam_hw_info *)hw_priv;
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tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info;
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- reserv = (struct cam_top_tpg_ver3_reserve_args *)reserve_args;
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-
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- if (reserv->num_inport <= 0 ||
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- reserv->num_inport > CAM_TOP_TPG_MAX_SUPPORTED_DT) {
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- CAM_ERR_RATE_LIMIT(CAM_ISP, "TPG: %u invalid input num port:%d",
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- tpg_hw->hw_intf->hw_idx, reserv->num_inport);
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- return -EINVAL;
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- }
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+ reserv = (struct cam_top_tpg_reserve_args *)reserve_args;
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mutex_lock(&tpg_hw->hw_info->hw_mutex);
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- if ((reserv->in_port->lane_num <= 0 ||
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- reserv->in_port->lane_num > 4) ||
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- (reserv->in_port->lane_type >= 2)) {
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+
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+ if ((reserv->in_port[0]->lane_num <= 0 ||
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+ reserv->in_port[0]->lane_num > 4) ||
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+ (reserv->in_port[0]->lane_type >= 2)) {
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CAM_ERR_RATE_LIMIT(CAM_ISP, "TPG:%u invalid input %d %d",
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tpg_hw->hw_intf->hw_idx,
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- reserv->in_port->lane_num,
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- reserv->in_port->lane_type);
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+ reserv->in_port[0]->lane_num,
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+ reserv->in_port[0]->lane_type);
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rc = -EINVAL;
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goto error;
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}
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- tpg_data = (struct cam_top_tpg_cfg *)tpg_hw->tpg_res.res_priv;
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- if (!tpg_hw->reserve_cnt)
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- memset(tpg_data, 0, sizeof(*tpg_data));
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-
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- if (tpg_hw->reserve_cnt) {
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- if ((tpg_data->num_active_dts +
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- reserv->in_port->num_valid_vc_dt) >
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- CAM_TOP_TPG_MAX_SUPPORTED_DT) {
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- CAM_DBG(CAM_ISP, "TPG: %u at max vc-dt config",
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- tpg_hw->hw_intf->hw_idx);
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- rc = -EINVAL;
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- goto error;
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- }
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-
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- if (tpg_data->phy_sel != reserv->in_port->lane_type ||
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- tpg_data->num_active_lanes != reserv->in_port->lane_num) {
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- CAM_DBG(CAM_ISP, "TPG: %u config mismatch",
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- tpg_hw->hw_intf->hw_idx);
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- rc = -EINVAL;
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- goto error;
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+ tpg_data = (struct cam_top_tpg_cfg_v2 *)tpg_hw->tpg_res.res_priv;
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+
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+ memcpy((void *)&in_port_vc_dt[0], (void *)&tpg_data->vc_dt[0],
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+ CAM_TOP_TPG_MAX_SUPPORTED_VC *
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+ sizeof(struct cam_top_tpg_vc_dt_info));
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+ num_active_vcs = tpg_data->num_active_vcs;
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+
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+ for (i = 0; i < reserv->num_inport; i++) {
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+ if (tpg_data->num_active_vcs) {
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+ if ((tpg_data->phy_sel !=
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+ reserv->in_port[i]->lane_type) ||
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+ (tpg_data->num_active_lanes !=
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+ reserv->in_port[i]->lane_num)) {
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+ CAM_ERR_RATE_LIMIT(CAM_ISP,
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+ "TPG: %u invalid DT config for tpg",
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+ tpg_hw->hw_intf->hw_idx);
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+ rc = -EINVAL;
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+ goto error;
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+ }
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+ } else {
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+ tpg_data->phy_sel = reserv->in_port[0]->lane_type;
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+ tpg_data->num_active_lanes =
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+ reserv->in_port[0]->lane_num;
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}
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- }
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- num_vc_dt = tpg_data->num_active_dts;
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- for (i = 0; i < reserv->in_port->num_valid_vc_dt; i++) {
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- if (reserv->in_port->dt[i] > 0x3f ||
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- reserv->in_port->vc[i] > 0x1f) {
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- CAM_ERR(CAM_ISP, "TPG:%u Invalid vc:%d dt %d",
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- tpg_hw->hw_intf->hw_idx,
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- reserv->in_port->vc[i],
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- reserv->in_port->dt[i]);
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+ rc = cam_top_tpg_ver3_add_append_vc_dt_info(
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+ &num_active_vcs,
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+ &in_port_vc_dt[0],
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+ reserv->in_port[i]);
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+ if (rc) {
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rc = -EINVAL;
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+ CAM_ERR(CAM_ISP,
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+ "Failed to reserve TPG:%u for in_port: %u",
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+ tpg_hw->hw_intf->hw_idx, i);
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goto error;
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}
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- tpg_data->vc_num[num_vc_dt + i] = reserv->in_port->vc[i];
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- tpg_data->dt_cfg[num_vc_dt + i].data_type = reserv->in_port->dt[i];
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}
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- rc = cam_top_tpg_get_format(reserv->in_port->format,
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- &encode_format);
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- if (rc)
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- goto error;
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-
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-
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CAM_DBG(CAM_ISP, "TPG: %u enter", tpg_hw->hw_intf->hw_idx);
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- if (!tpg_hw->reserve_cnt) {
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- tpg_data->phy_sel = reserv->in_port->lane_type;
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- tpg_data->num_active_lanes = reserv->in_port->lane_num;
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- }
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-
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- for (i = 0; i < reserv->in_port->num_valid_vc_dt; i++) {
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- tpg_data->dt_cfg[num_vc_dt + i].encode_format = encode_format;
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- tpg_data->dt_cfg[num_vc_dt + i].frame_height = reserv->in_port->height;
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+ tpg_data->num_active_vcs = num_active_vcs;
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+ memcpy((void *)&tpg_data->vc_dt[0], (void *)&in_port_vc_dt[0],
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+ CAM_TOP_TPG_MAX_SUPPORTED_VC *
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+ sizeof(struct cam_top_tpg_vc_dt_info));
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- if (reserv->in_port->usage_type)
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- tpg_data->dt_cfg[num_vc_dt + i].frame_width =
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- ((reserv->in_port->right_stop -
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- reserv->in_port->left_start) + 1);
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- else
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- tpg_data->dt_cfg[num_vc_dt + i].frame_width =
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- reserv->in_port->left_width;
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- }
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- tpg_data->num_active_dts += reserv->in_port->num_valid_vc_dt;
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CAM_DBG(CAM_ISP,
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- "TPG:%u phy:%d lines:%d pattern:%d format:%d",
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+ "TPG:%u phy:%d lines:%d pattern:%d hbi: %d vbi: %d",
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tpg_hw->hw_intf->hw_idx,
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- tpg_data->phy_sel, tpg_data->num_active_lanes,
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+ tpg_data->phy_sel,
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+ tpg_data->num_active_lanes,
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tpg_data->pix_pattern,
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- tpg_data->dt_cfg[0].encode_format);
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-
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- for (i = 0; i < tpg_data->num_active_dts; i++) {
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- CAM_DBG(CAM_ISP,
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- "TPG:%u idx: %d vc_num:%d dt:%d height:%d width:%d h blank:%d v blank:%d",
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- tpg_hw->hw_intf->hw_idx, i,
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- tpg_data->vc_num[i], tpg_data->dt_cfg[i].data_type,
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- tpg_data->dt_cfg[i].frame_height,
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- tpg_data->dt_cfg[i].frame_width,
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- tpg_data->h_blank_count,
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- tpg_data->v_blank_count);
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- }
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+ tpg_data->h_blank_count,
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+ tpg_data->v_blank_count);
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reserv->node_res = &tpg_hw->tpg_res;
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- tpg_hw->reserve_cnt++;
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tpg_hw->tpg_res.res_state = CAM_ISP_RESOURCE_STATE_RESERVED;
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error:
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mutex_unlock(&tpg_hw->hw_info->hw_mutex);
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@@ -233,6 +298,47 @@ error:
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return rc;
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}
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+static int cam_top_tpg_ver3_release(void *hw_priv,
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+ void *release_args, uint32_t arg_size)
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+{
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+ int rc = 0;
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+ struct cam_top_tpg_hw *tpg_hw;
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+ struct cam_hw_info *tpg_hw_info;
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+ struct cam_top_tpg_cfg_v2 *tpg_data;
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+ struct cam_isp_resource_node *tpg_res;
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+
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+ if (!hw_priv || !release_args ||
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+ (arg_size != sizeof(struct cam_isp_resource_node))) {
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+ CAM_ERR(CAM_ISP, "TPG: Invalid args");
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+ return -EINVAL;
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+ }
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+
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+ tpg_hw_info = (struct cam_hw_info *)hw_priv;
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+ tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info;
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+ tpg_res = (struct cam_isp_resource_node *)release_args;
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+
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+ mutex_lock(&tpg_hw->hw_info->hw_mutex);
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+ if ((tpg_res->res_type != CAM_ISP_RESOURCE_TPG) ||
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+ (tpg_res->res_state <= CAM_ISP_RESOURCE_STATE_AVAILABLE)) {
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+ CAM_ERR(CAM_ISP, "TPG:%d Invalid res type:%d res_state:%d",
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+ tpg_hw->hw_intf->hw_idx, tpg_res->res_type,
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+ tpg_res->res_state);
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+ rc = -EINVAL;
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+ goto end;
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+ }
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+
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+ CAM_DBG(CAM_ISP, "TPG:%d res type :%d",
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+ tpg_hw->hw_intf->hw_idx, tpg_res->res_type);
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+
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+ tpg_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE;
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+ tpg_data = (struct cam_top_tpg_cfg_v2 *)tpg_res->res_priv;
|
|
|
+ memset(tpg_data, 0, sizeof(struct cam_top_tpg_cfg_v2));
|
|
|
+
|
|
|
+end:
|
|
|
+ mutex_unlock(&tpg_hw->hw_info->hw_mutex);
|
|
|
+ return rc;
|
|
|
+}
|
|
|
+
|
|
|
static int cam_top_tpg_ver3_start(
|
|
|
void *hw_priv,
|
|
|
void *start_args,
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|
|
@@ -244,8 +350,9 @@ static int cam_top_tpg_ver3_start(
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|
struct cam_hw_soc_info *soc_info;
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|
struct cam_isp_resource_node *tpg_res;
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|
|
struct cam_top_tpg_ver3_reg_offset *tpg_reg;
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|
|
- struct cam_top_tpg_cfg *tpg_data;
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|
|
- uint32_t i, val;
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|
|
+ struct cam_top_tpg_cfg_v2 *tpg_data;
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|
+ struct cam_top_tpg_vc_dt_info *vc_dt;
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|
+ uint32_t i, val, j;
|
|
|
|
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|
if (!hw_priv || !start_args ||
|
|
|
(arg_size != sizeof(struct cam_isp_resource_node))) {
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@@ -257,12 +364,9 @@ static int cam_top_tpg_ver3_start(
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tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info;
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tpg_reg = tpg_hw->tpg_info->tpg_reg;
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tpg_res = (struct cam_isp_resource_node *)start_args;
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- tpg_data = (struct cam_top_tpg_cfg *)tpg_res->res_priv;
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+ tpg_data = (struct cam_top_tpg_cfg_v2 *)tpg_res->res_priv;
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soc_info = &tpg_hw->hw_info->soc_info;
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- if (tpg_res->res_state == CAM_ISP_RESOURCE_STATE_STREAMING)
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- goto end;
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-
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if ((tpg_res->res_type != CAM_ISP_RESOURCE_TPG) ||
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(tpg_res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED)) {
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CAM_ERR(CAM_ISP, "TPG:%d Invalid Res type:%d res_state:%d",
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@@ -274,82 +378,81 @@ static int cam_top_tpg_ver3_start(
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cam_io_w_mb(1, soc_info->reg_map[0].mem_base + tpg_reg->tpg_top_clear);
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- for (i = 0; i < tpg_data->num_active_dts; i++) {
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- val = (((tpg_data->dt_cfg[i].frame_width & 0xFFFF) << 16) |
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- (tpg_data->dt_cfg[i].frame_height & 0xFFFF));
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- cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
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- tpg_reg->tpg_vc0_dt_0_cfg_0 + 0x60 * i);
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-
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- CAM_DBG(CAM_ISP, "vc%d_dt_%d_cfg_0 0x%x",
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- i, i, val);
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- cam_io_w_mb(tpg_data->dt_cfg[i].data_type,
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- soc_info->reg_map[0].mem_base +
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- tpg_reg->tpg_vc0_dt_0_cfg_1 + 0x60 * i);
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+ for (i = 0; i < tpg_data->num_active_vcs; i++) {
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+ vc_dt = &tpg_data->vc_dt[i];
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|
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- CAM_DBG(CAM_ISP, "vc%d_dt_%d_cfg_1 0x%x",
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- i, i, tpg_data->dt_cfg[i].data_type);
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- val = ((tpg_data->dt_cfg[i].encode_format & 0xF) <<
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- tpg_reg->tpg_dt_encode_format_shift) |
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- tpg_reg->tpg_payload_mode_color;
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-
|
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- cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
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- tpg_reg->tpg_vc0_dt_0_cfg_2 + 0x60 * i);
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-
|
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- CAM_DBG(CAM_ISP, "vc%d_dt_%d_cfg_2 0x%x",
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- i, i, val);
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val = (1 << tpg_reg->tpg_split_en_shift);
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val |= tpg_data->pix_pattern;
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if (tpg_data->qcfa_en)
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|
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- val |= (1 << tpg_reg->tpg_color_bar_qcfa_en_shift);
|
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+ val |=
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|
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+ (1 << tpg_reg->tpg_color_bar_qcfa_en_shift);
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|
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cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
|
|
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- tpg_reg->tpg_vc0_color_bar_cfg + 0x60 * i);
|
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-
|
|
|
- CAM_DBG(CAM_ISP, "vc%d color_bar_cfg 0x%x",
|
|
|
- i, val);
|
|
|
- /*
|
|
|
- * if hblank is notset configureHBlank count 500 and
|
|
|
- * V blank count is 600
|
|
|
- */
|
|
|
+ tpg_reg->tpg_vc0_color_bar_cfg + (0x60 * i));
|
|
|
+ CAM_DBG(CAM_ISP, "vc%d_color_bar_cfg: 0x%x", i, val);
|
|
|
|
|
|
if (tpg_data->h_blank_count)
|
|
|
- cam_io_w_mb(tpg_data->h_blank_count,
|
|
|
- soc_info->reg_map[0].mem_base +
|
|
|
- tpg_reg->tpg_vc0_hbi_cfg + 0x60 * i);
|
|
|
+ val = tpg_data->h_blank_count;
|
|
|
else
|
|
|
- cam_io_w_mb(0x1F4,
|
|
|
- soc_info->reg_map[0].mem_base +
|
|
|
- tpg_reg->tpg_vc0_hbi_cfg + 0x60 * i);
|
|
|
+ val = 0x40;
|
|
|
+ cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
|
|
|
+ tpg_reg->tpg_vc0_hbi_cfg + (0x60 * i));
|
|
|
+ CAM_DBG(CAM_ISP, "vc%d_hbi_cfg: 0x%x", i, val);
|
|
|
|
|
|
if (tpg_data->v_blank_count)
|
|
|
- cam_io_w_mb(tpg_data->v_blank_count,
|
|
|
- soc_info->reg_map[0].mem_base +
|
|
|
- tpg_reg->tpg_vc0_vbi_cfg + 0x60 * i);
|
|
|
+ val = tpg_data->v_blank_count;
|
|
|
else
|
|
|
- cam_io_w_mb(0x258,
|
|
|
- soc_info->reg_map[0].mem_base +
|
|
|
- tpg_reg->tpg_vc0_vbi_cfg + 0x60 * i);
|
|
|
+ val = 0xC600;
|
|
|
+ cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
|
|
|
+ tpg_reg->tpg_vc0_vbi_cfg + (0x60 * i));
|
|
|
+ CAM_DBG(CAM_ISP, "vc%d_vbi_cgf: 0x%x", i, val);
|
|
|
|
|
|
- cam_io_w_mb(0x12345678, soc_info->reg_map[0].mem_base +
|
|
|
- tpg_reg->tpg_vc0_lfsr_seed + 0x60 * i);
|
|
|
+ cam_io_w_mb(CAM_TPG_LFSR_SEED,
|
|
|
+ soc_info->reg_map[0].mem_base +
|
|
|
+ tpg_reg->tpg_vc0_lfsr_seed + (0x60 * i));
|
|
|
|
|
|
- val = tpg_data->vc_num[i];
|
|
|
+ val = (((vc_dt->num_active_dts-1) <<
|
|
|
+ tpg_reg->tpg_num_dts_shift_val) |
|
|
|
+ vc_dt->vc_num);
|
|
|
cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
|
|
|
- tpg_reg->tpg_vc0_cfg0 + 0x60 * i);
|
|
|
- CAM_DBG(CAM_ISP, "vc%d_cfg0 0x%x",
|
|
|
- i, val);
|
|
|
+ tpg_reg->tpg_vc0_cfg0 + (0x60 * i));
|
|
|
+ CAM_DBG(CAM_ISP, "vc%d_cfg0: 0x%x", i, val);
|
|
|
+
|
|
|
+ for (j = 0; j < vc_dt->num_active_dts; j++) {
|
|
|
+ val = (((vc_dt->dt_cfg[j].frame_width & 0xFFFF) << 16) |
|
|
|
+ (vc_dt->dt_cfg[j].frame_height & 0xFFFF));
|
|
|
+ cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
|
|
|
+ tpg_reg->tpg_vc0_dt_0_cfg_0 +
|
|
|
+ (0x60 * i) + (j * 0x0c));
|
|
|
+ CAM_DBG(CAM_ISP, "vc%d_dt%d_cfg_0: 0x%x", i, j, val);
|
|
|
+
|
|
|
+ cam_io_w_mb(vc_dt->dt_cfg[j].data_type,
|
|
|
+ soc_info->reg_map[0].mem_base +
|
|
|
+ tpg_reg->tpg_vc0_dt_0_cfg_1 +
|
|
|
+ (0x60 * i) + (j * 0x0c));
|
|
|
+ CAM_DBG(CAM_ISP, "vc%d_dt%d_cfg_1: 0x%x",
|
|
|
+ i, j, vc_dt->dt_cfg[j].data_type);
|
|
|
+
|
|
|
+ val = ((vc_dt->dt_cfg[j].encode_format & 0xF) <<
|
|
|
+ tpg_reg->tpg_dt_encode_format_shift) |
|
|
|
+ tpg_reg->tpg_payload_mode_color;
|
|
|
+ cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
|
|
|
+ tpg_reg->tpg_vc0_dt_0_cfg_2 +
|
|
|
+ (0x60 * i) + (j * 0x0c));
|
|
|
+ CAM_DBG(CAM_ISP, "vc%d_dt%d_cfg_2: 0x%x", i, j, val);
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
if (tpg_data->throttle_pattern)
|
|
|
- cam_io_w_mb(tpg_data->throttle_pattern,
|
|
|
- soc_info->reg_map[0].mem_base + tpg_reg->tpg_throttle);
|
|
|
+ val = tpg_data->throttle_pattern;
|
|
|
else
|
|
|
- cam_io_w_mb(0x1111,
|
|
|
- soc_info->reg_map[0].mem_base + tpg_reg->tpg_throttle);
|
|
|
+ val = 0x1111;
|
|
|
+ cam_io_w_mb(val, soc_info->reg_map[0].mem_base + tpg_reg->tpg_throttle);
|
|
|
+ CAM_DBG(CAM_ISP, "tpg_throttle: 0x%x", val);
|
|
|
|
|
|
cam_io_w_mb(1, soc_info->reg_map[0].mem_base +
|
|
|
tpg_reg->tpg_top_irq_mask);
|
|
|
|
|
|
- val = ((tpg_data->num_active_dts - 1) <<
|
|
|
+ val = ((tpg_data->num_active_vcs - 1) <<
|
|
|
(tpg_reg->tpg_num_active_vcs_shift) |
|
|
|
(tpg_data->num_active_lanes - 1) <<
|
|
|
tpg_reg->tpg_num_active_lanes_shift) |
|
|
|
@@ -382,7 +485,6 @@ static int cam_top_tpg_ver3_stop(
|
|
|
struct cam_hw_soc_info *soc_info;
|
|
|
struct cam_isp_resource_node *tpg_res;
|
|
|
const struct cam_top_tpg_ver3_reg_offset *tpg_reg;
|
|
|
- struct cam_top_tpg_cfg *tpg_data;
|
|
|
|
|
|
if (!hw_priv || !stop_args ||
|
|
|
(arg_size != sizeof(struct cam_isp_resource_node))) {
|
|
|
@@ -394,7 +496,6 @@ static int cam_top_tpg_ver3_stop(
|
|
|
tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info;
|
|
|
tpg_reg = tpg_hw->tpg_info->tpg_reg;
|
|
|
tpg_res = (struct cam_isp_resource_node *) stop_args;
|
|
|
- tpg_data = (struct cam_top_tpg_cfg *)tpg_res->res_state;
|
|
|
soc_info = &tpg_hw->hw_info->soc_info;
|
|
|
|
|
|
if ((tpg_res->res_type != CAM_ISP_RESOURCE_TPG) ||
|
|
|
@@ -431,6 +532,7 @@ int cam_top_tpg_ver3_init(
|
|
|
{
|
|
|
tpg_hw->hw_intf->hw_ops.get_hw_caps = cam_top_tpg_ver3_get_hw_caps;
|
|
|
tpg_hw->hw_intf->hw_ops.reserve = cam_top_tpg_ver3_reserve;
|
|
|
+ tpg_hw->hw_intf->hw_ops.release = cam_top_tpg_ver3_release;
|
|
|
tpg_hw->hw_intf->hw_ops.start = cam_top_tpg_ver3_start;
|
|
|
tpg_hw->hw_intf->hw_ops.stop = cam_top_tpg_ver3_stop;
|
|
|
tpg_hw->hw_intf->hw_ops.process_cmd = cam_top_tpg_ver3_process_cmd;
|
Jigar Agrawal