disp: msm: sde: add ctl api to enable/disable sub-blocks

Certain sub-blocks need to be enabled disabled dynamically on a
seemless mode switch (for ex. partial update) CWB is another example
where control path interface configuration needs to be dynamically
changed on enable/disable of concurrent writeback. Similarly
3d mux needs to be enabled/disabled for partial update use cases.
This change modfies the current api update_cwb_cfg and makes it
more generic and adds support to enable/disable only the 3d mux.

Change-Id: I5e5a6e78b0599f689cb2f83d0d626a5f392eff6e
Signed-off-by: Abhijit Kulkarni <[email protected]>

msm/sde/sde_encoder_phys_wb.c

@@ -499,8 +499,8 @@ static void _sde_encoder_phys_wb_setup_cwb(struct sde_encoder_phys *phys_enc,
 		if (hw_wb->ops.bind_pingpong_blk)
 			hw_wb->ops.bind_pingpong_blk(hw_wb, enable, hw_pp->idx);
 
-		if (hw_ctl->ops.update_cwb_cfg) {
-			hw_ctl->ops.update_cwb_cfg(hw_ctl, &intf_cfg, enable);
+		if (hw_ctl->ops.update_intf_cfg) {
+			hw_ctl->ops.update_intf_cfg(hw_ctl, &intf_cfg, enable);
 			SDE_DEBUG("in CWB mode on CTL_%d PP-%d merge3d:%d\n",
 					hw_ctl->idx - CTL_0,
 					hw_pp->idx - PINGPONG_0,

msm/sde/sde_hw_ctl.c

@@ -64,6 +64,8 @@
 
 #define CTL_INVALID_BIT                0xffff
 
+#define UPDATE_ACTIVE(r, idx, en)  UPDATE_MASK((r), (idx), (en))
+
 /**
  * List of SSPP bits in CTL_FLUSH
  */
@@ -1078,7 +1080,7 @@ static int sde_hw_ctl_reset_post_disable(struct sde_hw_ctl *ctx,
 	return 0;
 }
 
-static int sde_hw_ctl_update_cwb_cfg(struct sde_hw_ctl *ctx,
+static int sde_hw_ctl_update_intf_cfg(struct sde_hw_ctl *ctx,
 		struct sde_hw_intf_cfg_v1 *cfg, bool enable)
 {
 	int i;
@@ -1091,28 +1093,33 @@ static int sde_hw_ctl_update_cwb_cfg(struct sde_hw_ctl *ctx,
 		return -EINVAL;
 
 	c = &ctx->hw;
-	cwb_active = SDE_REG_READ(c, CTL_CWB_ACTIVE);
-	for (i = 0; i < cfg->cwb_count; i++) {
-		if (cfg->cwb[i])
-			cwb_active |= BIT(cfg->cwb[i] - CWB_0);
-	}
 
-	merge_3d_active = SDE_REG_READ(c, CTL_MERGE_3D_ACTIVE);
-	for (i = 0; i < cfg->merge_3d_count; i++) {
-		if (cfg->merge_3d[i])
-			merge_3d_active |= BIT(cfg->merge_3d[i] - MERGE_3D_0);
-	}
+	if (cfg->cwb_count) {
+		wb_active = 0;
+		cwb_active = SDE_REG_READ(c, CTL_CWB_ACTIVE);
+		for (i = 0; i < cfg->cwb_count; i++) {
+			if (cfg->cwb[i])
+				UPDATE_ACTIVE(cwb_active,
+					(cfg->cwb[i] - CWB_0),
+					enable);
+		}
 
-	if (enable) {
-		wb_active = BIT(2);
+		wb_active = enable ? BIT(2) : 0;
+		SDE_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);
 		SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
+	}
+
+	if (cfg->merge_3d_count) {
+		merge_3d_active = SDE_REG_READ(c, CTL_MERGE_3D_ACTIVE);
+		for (i = 0; i < cfg->merge_3d_count; i++) {
+			if (cfg->merge_3d[i])
+				UPDATE_ACTIVE(merge_3d_active,
+					(cfg->merge_3d[i] - MERGE_3D_0),
+					enable);
+		}
 		SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
-		SDE_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);
-	} else {
-		SDE_REG_WRITE(c, CTL_WB_ACTIVE, 0x0);
-		SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, 0x0);
-		SDE_REG_WRITE(c, CTL_CWB_ACTIVE, 0x0);
 	}
+
 	return 0;
 }
 
@@ -1280,7 +1287,7 @@ static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops,
 		ops->trigger_flush = sde_hw_ctl_trigger_flush_v1;
 
 		ops->setup_intf_cfg_v1 = sde_hw_ctl_intf_cfg_v1;
-		ops->update_cwb_cfg = sde_hw_ctl_update_cwb_cfg;
+		ops->update_intf_cfg = sde_hw_ctl_update_intf_cfg;
 		ops->setup_dsc_cfg = sde_hw_ctl_dsc_cfg;
 
 		ops->update_bitmask_cdm = sde_hw_ctl_update_bitmask_cdm_v1;

msm/sde/sde_hw_ctl.h

@@ -249,10 +249,10 @@ struct sde_hw_ctl_ops {
 	/** update cwb  for ctl_path
 	 * @ctx       : ctl path ctx pointer
 	 * @cfg    : interface config structure pointer
-	 * @enable    : enable/disable the cwb hw block
+	 * @enable    : enable/disable the dynamic sub-blocks in interface cfg
 	 * @Return: error code
 	 */
-	int (*update_cwb_cfg)(struct sde_hw_ctl *ctx,
+	int (*update_intf_cfg)(struct sde_hw_ctl *ctx,
 		struct sde_hw_intf_cfg_v1 *cfg, bool enable);
 
 	/**