qcacld-3.0: Add cfg ini parameter tgt_gtx_usr_cfg

qcacld-2.0 to qcacld-3.0 propagation

GTX use this parameter to drop TPC and in turn TPC drop is the cause
for mcs rate drop and may happen in higher percentage. This change,
provide a way to select the desired value and reduce mcs-8 usage to
2% from 8%.

Change-Id: I64f05c8b41cf3d360819122a08eca72f3a2c1aed
CRs-Fixed: 1010564

core/hdd/inc/wlan_hdd_cfg.h

@@ -3380,6 +3380,11 @@ enum dot11p_mode {
 #define CFG_SUB_20_CHANNEL_WIDTH_MAX               (WLAN_SUB_20_CH_WIDTH_10)
 #define CFG_SUB_20_CHANNEL_WIDTH_DEFAULT           (WLAN_SUB_20_CH_WIDTH_NONE)
 
+#define CFG_TGT_GTX_USR_CFG_NAME    "tgt_gtx_usr_cfg"
+#define CFG_TGT_GTX_USR_CFG_MIN     (0)
+#define CFG_TGT_GTX_USR_CFG_MAX     (32)
+#define CFG_TGT_GTX_USR_CFG_DEFAULT (32)
+
 /*
  * This parameter determines that which defered method will be use in rx path
  * If no bits are set then rx path processing will happen in tasklet context.
@@ -4121,6 +4126,8 @@ struct hdd_config {
 	uint8_t nan_datapath_ndi_channel;
 #endif
 	uint32_t iface_change_wait_time;
+	/* parameter to control GTX */
+	uint32_t tgt_gtx_usr_cfg;
 	enum cfg_sub_20_channel_width enable_sub_20_channel_width;
 	bool indoor_channel_support;
 	bool multicast_replay_filter;

core/hdd/src/wlan_hdd_cfg.c

@@ -3901,6 +3901,13 @@ REG_TABLE_ENTRY g_registry_table[] = {
 		     CFG_SUB_20_CHANNEL_WIDTH_MIN,
 		     CFG_SUB_20_CHANNEL_WIDTH_MAX),
 
+	REG_VARIABLE(CFG_TGT_GTX_USR_CFG_NAME, WLAN_PARAM_Integer,
+		     struct hdd_config, tgt_gtx_usr_cfg,
+		     VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT,
+		     CFG_TGT_GTX_USR_CFG_DEFAULT,
+		     CFG_TGT_GTX_USR_CFG_MIN,
+		     CFG_TGT_GTX_USR_CFG_MAX),
+
 	REG_VARIABLE(CFG_ADAPT_DWELL_PASMON_INTVAL_NAME, WLAN_PARAM_Integer,
 		struct hdd_config, adapt_dwell_passive_mon_intval,
 		VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT,
@@ -5614,6 +5621,9 @@ void hdd_cfg_print(hdd_context_t *pHddCtx)
 	hdd_info("Name = [%s] value = [%u]",
 		 CFG_SUB_20_CHANNEL_WIDTH_NAME,
 		 pHddCtx->config->enable_sub_20_channel_width);
+	hdd_info("Name = [%s] Value = [%u]",
+		 CFG_TGT_GTX_USR_CFG_NAME,
+		 pHddCtx->config->tgt_gtx_usr_cfg);
 	hdd_ndp_print_ini_config(pHddCtx);
 	hdd_info("Name = [%s] Value = [%s]",
 		CFG_RM_CAPABILITY_NAME,
@@ -6794,6 +6804,13 @@ bool hdd_update_config_dat(hdd_context_t *pHddCtx)
 		hddLog(LOGE,
 		       "Could not pass on WNI_CFG_VHT_CSN_BEAMFORMEE_ANT_SUPPORTED to CFG");
 	}
+
+	if (sme_cfg_set_int(pHddCtx->hHal, WNI_CFG_TGT_GTX_USR_CFG,
+	    pConfig->tgt_gtx_usr_cfg) == QDF_STATUS_E_FAILURE) {
+		fStatus = false;
+		hddLog(LOGE,
+		       "Could not pass on WNI_CFG_TGT_GTX_USR_CFG to CCM");
+	}
 	return fStatus;
 }
 #ifdef FEATURE_WLAN_SCAN_PNO

core/mac/inc/wni_cfg.h

@@ -250,6 +250,7 @@ enum {
 	WNI_CFG_OBSS_HT40_SCAN_ACTIVE_TOTAL_PER_CHANNEL,
 	WNI_CFG_OBSS_HT40_WIDTH_CH_TRANSITION_DELAY,
 	WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD,
+	WNI_CFG_TGT_GTX_USR_CFG,
 	/* Any new items to be added should be above this strictly */
 	CFG_PARAM_MAX_NUM
 };
@@ -1255,6 +1256,10 @@ enum {
 #define WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD_STAMAX    100
 #define WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD_STADEF    25
 
+#define WNI_CFG_TGT_GTX_USR_CFG_STAMIN 0
+#define WNI_CFG_TGT_GTX_USR_CFG_STAMAX 32
+#define WNI_CFG_TGT_GTX_USR_CFG_STADEF 32
+
 #define CFG_STA_MAGIC_DWORD    0xbeefbeef
 
 #endif

core/mac/src/cfg/cfg_proc_msg.c

@@ -1173,7 +1173,12 @@ cgstatic cfg_static[CFG_PARAM_MAX_NUM] = {
 	CFG_CTL_NTF_LIM,
 	WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD_STAMIN,
 	WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD_STAMAX,
-	WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD_STADEF}
+	WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD_STADEF},
+	{WNI_CFG_TGT_GTX_USR_CFG,
+	CFG_CTL_VALID | CFG_CTL_RE | CFG_CTL_WE | CFG_CTL_INT,
+	WNI_CFG_TGT_GTX_USR_CFG_STAMIN,
+	WNI_CFG_TGT_GTX_USR_CFG_STAMAX,
+	WNI_CFG_TGT_GTX_USR_CFG_STADEF}
 };
 
 

core/wma/src/wma_dev_if.c

@@ -1796,8 +1796,15 @@ QDF_STATUS wma_vdev_start(tp_wma_handle wma,
 		CFG_TGT_DEFAULT_GTX_HT_MASK;
 	intr[params.vdev_id].config.gtx_info.gtxRTMask[1] =
 		CFG_TGT_DEFAULT_GTX_VHT_MASK;
-	intr[params.vdev_id].config.gtx_info.gtxUsrcfg =
-		CFG_TGT_DEFAULT_GTX_USR_CFG;
+
+	if (wlan_cfg_get_int(mac_ctx, WNI_CFG_TGT_GTX_USR_CFG,
+	    &intr[params.vdev_id].config.gtx_info.gtxUsrcfg) != eSIR_SUCCESS) {
+		intr[params.vdev_id].config.gtx_info.gtxUsrcfg =
+						WNI_CFG_TGT_GTX_USR_CFG_STADEF;
+		QDF_TRACE(QDF_MODULE_ID_WMA, QDF_TRACE_LEVEL_WARN,
+			  "Failed to get WNI_CFG_TGT_GTX_USR_CFG");
+	}
+
 	intr[params.vdev_id].config.gtx_info.gtxPERThreshold =
 		CFG_TGT_DEFAULT_GTX_PER_THRESHOLD;
 	intr[params.vdev_id].config.gtx_info.gtxPERMargin =

core/wma/src/wma_scan_roam.c

@@ -2705,8 +2705,15 @@ QDF_STATUS wma_switch_channel(tp_wma_handle wma, struct wma_vdev_start_req *req)
 						CFG_TGT_DEFAULT_GTX_HT_MASK;
 	intr[req->vdev_id].config.gtx_info.gtxRTMask[1] =
 						CFG_TGT_DEFAULT_GTX_VHT_MASK;
-	intr[req->vdev_id].config.gtx_info.gtxUsrcfg =
-						CFG_TGT_DEFAULT_GTX_USR_CFG;
+
+	if (wlan_cfg_get_int(pmac, WNI_CFG_TGT_GTX_USR_CFG,
+	    &intr[req->vdev_id].config.gtx_info.gtxUsrcfg) != eSIR_SUCCESS) {
+		intr[req->vdev_id].config.gtx_info.gtxUsrcfg =
+						WNI_CFG_TGT_GTX_USR_CFG_STADEF;
+		QDF_TRACE(QDF_MODULE_ID_WMA, QDF_TRACE_LEVEL_WARN,
+			  "Failed to get WNI_CFG_TGT_GTX_USR_CFG");
+	}
+
 	intr[req->vdev_id].config.gtx_info.gtxPERThreshold =
 					CFG_TGT_DEFAULT_GTX_PER_THRESHOLD;
 	intr[req->vdev_id].config.gtx_info.gtxPERMargin =

target/inc/wlan_tgt_def_config.h

@@ -218,10 +218,6 @@
  * vht enable highest MCS by default
  */
 #define CFG_TGT_DEFAULT_GTX_VHT_MASK            0x80200
-/*
- * resv for furture use, bit 30 is used for fix tpc, bit0-3 for Power save balance
- */
-#define CFG_TGT_DEFAULT_GTX_USR_CFG             0xa
 /*
  * threshold to enable GTX
  */

target/inc/wlan_tgt_def_config_hl.h

@@ -250,11 +250,6 @@
  * vht enable highest MCS by default
  */
 #define CFG_TGT_DEFAULT_GTX_VHT_MASK        0x80200
-/*
- * resv for furture use, bit 30 is used for fix tpc, bit0-3 for Power save
- * balance
- */
-#define CFG_TGT_DEFAULT_GTX_USR_CFG     0xa
 /*
  * threshold to enable GTX
  */