qcacmn: Add support to handle BAR frames in host

Due to recent FW changes not filtering out BAR frames, redirect these
frames to REO exception ring and handle as normal data packets.

Change-Id: I4540929fddab14de57a23f6364fc916a70057cbe
CRs-Fixed: 2795499

hal/wifi3.0/qca6490/hal_6490.c

@@ -1471,9 +1471,18 @@ hal_reo_set_err_dst_remap_6490(void *hal_soc)
 		HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) |
 		HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) |
 		HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) |
-		HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 6) |
+		HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) |
 		HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7);
 
+	uint32_t dst_remap_ix1 =
+		HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 14) |
+		HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 13) |
+		HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 12) |
+		HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 11) |
+		HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 10) |
+		HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 9) |
+		HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8);
+
 		HAL_REG_WRITE(hal_soc,
 			      HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
 			      SEQ_WCSS_UMAC_REO_REG_OFFSET),
@@ -1484,6 +1493,17 @@ hal_reo_set_err_dst_remap_6490(void *hal_soc)
 			 hal_soc,
 			 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
 			 SEQ_WCSS_UMAC_REO_REG_OFFSET)));
+
+		HAL_REG_WRITE(hal_soc,
+			      HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(
+			      SEQ_WCSS_UMAC_REO_REG_OFFSET),
+			      dst_remap_ix1);
+
+		hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x",
+			 HAL_REG_READ(
+			 hal_soc,
+			 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(
+			 SEQ_WCSS_UMAC_REO_REG_OFFSET)));
 }
 
 /**

hal/wifi3.0/qca6490/hal_6490_rx.h

@@ -307,6 +307,17 @@
 			      HWIO_REO_R0_MISC_CTL_ADDR( \
 			      SEQ_WCSS_UMAC_REO_REG_OFFSET), \
 			      (reg_val)); \
+		reg_val = \
+			HAL_REG_READ((soc), \
+				     HWIO_REO_R0_GENERAL_ENABLE_ADDR(	\
+				     SEQ_WCSS_UMAC_REO_REG_OFFSET)); \
+		reg_val &= \
+			(~HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK |\
+				(REO_REMAP_TCL << HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT)); \
+		HAL_REG_WRITE((soc), \
+			      HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
+			      SEQ_WCSS_UMAC_REO_REG_OFFSET), \
+			      (reg_val)); \
 	} while (0)
 
 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \