msm: camera: cpas: Add support for Crow Camera

This change adds camnoc interface changes and CPAS version
change for Crow camera.

CRs-Fixed: 3426117
Change-Id: I8735dc87ccd0ebcde98a53f6d695167fedb4cc35
Signed-off-by: Ayush Kumar <[email protected]>

Kbuild

@@ -14,10 +14,6 @@ ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
 include $(CAMERA_KERNEL_ROOT)/config/pineapple.mk
 endif
 
-ifeq ($(CONFIG_ARCH_KALAMA), y)
-include $(CAMERA_KERNEL_ROOT)/config/kalama.mk
-endif
-
 ifeq ($(CONFIG_ARCH_WAIPIO), y)
 include $(CAMERA_KERNEL_ROOT)/config/waipio.mk
 endif
@@ -58,6 +54,16 @@ ifeq ($(CONFIG_ARCH_PARROT), y)
 include $(CAMERA_KERNEL_ROOT)/config/parrot.mk
 endif
 
+# For some targets which have binary compatible gki kernel with another one,
+# we cannot rely on CONFIG_ARCH_* symbol which is defined in Kernel defconfig
+ifeq ($(BOARD_PLATFORM), kalama)
+include $(CAMERA_KERNEL_ROOT)/config/kalama.mk
+endif
+
+ifeq ($(BOARD_PLATFORM), crow)
+include $(CAMERA_KERNEL_ROOT)/config/crow.mk
+endif
+
 ifneq ($(KBUILD_EXTRA_CONFIGS),)
 include $(KBUILD_EXTRA_CONFIGS)
 endif

config/crow.mk

@@ -0,0 +1,17 @@
+# Settings for compiling crow camera architecture
+
+# Localized KCONFIG settings
+CONFIG_SPECTRA_ISP := y
+CONFIG_SPECTRA_ICP := y
+CONFIG_SPECTRA_TFE := y
+CONFIG_SPECTRA_JPEG := y
+CONFIG_SPECTRA_CRE := y
+CONFIG_SPECTRA_SENSOR := y
+
+# Flags to pass into C preprocessor
+ccflags-y += -DCONFIG_SPECTRA_ISP=1
+ccflags-y += -DCONFIG_SPECTRA_ICP=1
+ccflags-y += -DCONFIG_SPECTRA_TFE=1
+ccflags-y += -DCONFIG_SPECTRA_JPEG=1
+ccflags-y += -DCONFIG_SPECTRA_CRE=1
+ccflags-y += -DCONFIG_SPECTRA_SENSOR=1

drivers/cam_cpas/cpas_top/cam_cpastop_hw.c

@@ -39,6 +39,7 @@
 #include "cpastop_v880_100.h"
 #include "cpastop_v980_100.h"
 #include "cpastop_v860_100.h"
+#include "cpastop_v770_100.h"
 #include "cam_req_mgr_workq.h"
 #include "cam_common_util.h"
 
@@ -210,6 +211,15 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 	},
+	/* for camera_770 */
+	{
+		CAM_CPAS_TITAN_770_V100,
+		0,
+		0,
+		0,
+		0,
+		0,
+	},
 };
 
 static char *cam_cpastop_get_camnoc_name(enum cam_camnoc_hw_type type)
@@ -294,6 +304,9 @@ static int cam_cpas_translate_camera_cpas_version_id(
 	case CAM_CPAS_CAMERA_VERSION_860:
 		*cam_version_id = CAM_CPAS_CAMERA_VERSION_ID_860;
 		break;
+	case CAM_CPAS_CAMERA_VERSION_770:
+		*cam_version_id = CAM_CPAS_CAMERA_VERSION_ID_770;
+		break;
 	default:
 		CAM_ERR(CAM_CPAS, "Invalid cam version %u",
 			cam_version);
@@ -1439,6 +1452,11 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw,
 		cpas_info = &cam860_cpas100_cpas_info;
 		cesta_info = &cam_v860_cesta_info;
 		break;
+	case CAM_CPAS_TITAN_770_V100:
+		alloc_camnoc_info[CAM_CAMNOC_HW_COMBINED] = &cam770_cpas100_camnoc_info;
+		cpas_info = &cam770_cpas100_cpas_info;
+		cpas_top_info = &cam770_cpas100_cpas_top_info;
+		break;
 	default:
 		CAM_ERR(CAM_CPAS, "Camera Version not supported %d.%d.%d",
 			hw_caps->camera_version.major,

drivers/cam_cpas/cpas_top/cpastop_v770_100.h

@@ -0,0 +1,689 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CPASTOP_V770_100_H_
+#define _CPASTOP_V770_100_H_
+
+#define TEST_IRQ_ENABLE 0
+
+static struct cam_camnoc_irq_sbm cam_cpas_v770_100_irq_sbm = {
+	.sbm_enable = {
+		.access_type = CAM_REG_TYPE_READ_WRITE,
+		.enable = true,
+		.offset = 0x240, /* CAM_NOC_SBM_FAULTINEN0_LOW */
+		.value = 0x2 |    /* SBM_FAULTINEN0_LOW_PORT1_MASK */
+			0x04 |     /* SBM_FAULTINEN0_LOW_PORT2_MASK */
+			0x08 |     /* SBM_FAULTINEN0_LOW_PORT3_MASK */
+			0x10 |    /* SBM_FAULTINEN0_LOW_PORT4_MASK */
+			0x20 |    /* SBM_FAULTINEN0_LOW_PORT5_MASK */
+			(TEST_IRQ_ENABLE ?
+			0x80 :    /* SBM_FAULTINEN0_LOW_PORT7_MASK */
+			0x0),
+	},
+	.sbm_status = {
+		.access_type = CAM_REG_TYPE_READ,
+		.enable = true,
+		.offset = 0x248, /* CAM_NOC_SBM_FAULTINSTATUS0_LOW */
+	},
+	.sbm_clear = {
+		.access_type = CAM_REG_TYPE_WRITE,
+		.enable = true,
+		.offset = 0x280, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
+		.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
+	}
+};
+
+static struct cam_camnoc_irq_err
+	cam_cpas_v770_100_irq_err[] = {
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
+		.enable = false,
+		.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x8, /* CAM_NOC_ERL_MAINCTL_LOW */
+			.value = 1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x10, /* CAM_NOC_ERL_ERRVLD_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x18, /* CAM_NOC_ERL_ERRCLR_LOW */
+			.value = 1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x89A0, /* WR_NIU_ENCERREN_LOW */
+			.value = 0XF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x8990, /* WR_NIU_ENCERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x8998, /* WR_NIU_ENCERRCLR_LOW */
+			.value = 0X1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x8720, /* CAM_NOC_IPE_0_RD_NIU_DECERREN_LOW */
+			.value = 0xFF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x8710, /* CAM_NOC_IPE_0_RD_NIU_DECERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x8718, /* CAM_NOC_IPE_0_RD_NIU_DECERRCLR_LOW */
+			.value = 0X1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
+		.enable = false,
+		.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x288, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */
+			.value = 0x1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x290, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */
+		},
+		.err_clear = {
+			.enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
+		.enable = false,
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
+		.enable = false,
+	},
+};
+
+static struct cam_camnoc_specific
+	cam_cpas_v770_100_camnoc_specific[] = {
+	{
+		.port_type = CAM_CAMNOC_TFE_BAYER_STATS,
+		.port_name = "TFE_BAYER",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8A30, /* TFE_BAYER_NIU_PRIORITYLUT_LOW */
+			.value = 0x55554433,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8A34, /* TFE_BAYER_NIU_PRIORITYLUT_HIGH */
+			.value = 0x66666666,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8A38, /* TFE_BAYER_NIU_URGENCY_LOW */
+			.value = 0x00001030,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8A40, /* TFE_BAYER_NIU_DANGERLUT_LOW */
+			.value = 0xffffff00,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8A48, /* TFE_BAYER_NIU_SAFELUT_LOW */
+			.value = 0x0000000f,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x9008, /* TFE_BAYER_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x9020, /* TFE_BAYER_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x9024, /* TFE_BAYER_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x8A20, /* TFE_BAYER_NIU_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_TFE_RAW,
+		.port_name = "TFE_RDI_RAW",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8C30, /* TFE_RDI_NIU_PRIORITYLUT_LOW */
+			.value = 0x55554433,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8C34, /* TFE_RDI_NIU_PRIORITYLUT_HIGH */
+			.value = 0x66666666,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8C38, /* TFE_RDI_RAW_URGENCY_LOW */
+			.value = 0x00001030,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8C40, /* TFE_RDI_NIU_DANGERLUT_LOW */
+			.value = 0xffffff00,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8C48, /* TFE_RDI_NIU_SAFELUT_LOW */
+			.value = 0x000f,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x9088, /* TFE_RDI_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x90A0, /* TFE_RDI_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x90A4, /* TFE_RDI_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x8C20, /* TFE_RDI_NIU_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_OPE_BPS_WR,
+		.port_name = "OPE_BPS_WR",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8830, /* OFFLINE_WR_NIU_PRIORITYLUT_LOW */
+			.value = 0x33333333,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8834, /* OFFLINE_WR_NIU_PRIORITYLUT_HIGH */
+			.value = 0x33333333,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8838, /* OFFLINE_WR_NIU_URGENCY_LOW */
+			.value = 0x00000030,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8840, /* OFFLINE_WR_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8848, /* OFFLINE_WR_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8F88, /* OFFLINE_WR_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8FA0, /* OFFLINE_WR_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8FA4, /* OFFLINE_WR_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x8820, /* OFFLINE_WR_NIU_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_OPE_BPS_CDM_RD,
+		.port_name = "OPE_BPS_CDM_RD",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8630, /* OFFLINE_RD_NIU_PRIORITYLUT_LOW */
+			.value = 0x33333333,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8634, /* OFFLINE_RD_NIU_PRIORITYLUT_HIGH */
+			.value = 0x33333333,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8638, /* OFFLINE_RD_NIU_URGENCY_LOW */
+			.value = 0x3,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8640, /* OFFLINE_RD_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8648, /* OFFLINE_RD_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8F08, /* OFFLINE_RD_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8F20, /* OFFLINE_RD_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8F24, /* OFFLINE_RD_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_CRE,
+		.port_name = "CRE_RD_WR",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8230, /* CRE_NIU_PRIORITYLUT_LOW */
+			.value = 0x33333333,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8234, /* CRE_NIU_PRIORITYLUT_HIGH */
+			.value = 0x33333333,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8238, /* CRE_NIU_URGENCY_LOW */
+			.value = 0x33,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8240, /* CRE_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8248, /* CRE_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8E88, /* CRE_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8EA0, /* CRE_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8EA4, /* CRE_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x8220, /* CRE_NIU_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_JPEG,
+		.port_name = "JPEG",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8430, /* JPEG_NIU_PRIORITYLUT_LOW */
+			.value = 0x33333333,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8434, /* JPEG_NIU_PRIORITYLUT_HIGH */
+			.value = 0x33333333,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8438, /* JPEG_NIU_URGENCY_LOW */
+			.value = 0x33,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8440, /* JPEG_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8448, /* JPEG_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_CDM,
+		.port_name = "CDM",
+		.enable = false,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8030, /* CDM_NIU_PRIORITYLUT_LOW */
+			.value = 0x33333333,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8034, /* CDM_NIU_PRIORITYLUT_HIGH */
+			.value = 0x33333333,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8038, /* CDM_NIU_URGENCY_LOW */
+			.value = 0x33,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8040, /* CDM_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8048, /* CDM_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8E08, /* CDM_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8E20, /* CDM_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8E24, /* CDM_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_ICP,
+		.port_name = "ICP",
+		.enable = false,
+		.flag_out_set0_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_WRITE,
+			.masked_value = 0,
+			.offset = 0x288,
+			.value = 0x100000,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x9108, /* ICP_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x9120, /* ICP_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x9124, /* ICP_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+};
+
+static struct cam_camnoc_err_logger_info cam770_cpas100_err_logger_offsets = {
+	.mainctrl     =  0x8,    /* ERL_MAINCTL_LOW */
+	.errvld       =  0x10,   /* ERl_ERRVLD_LOW */
+	.errlog0_low  =  0x20,   /* ERL_ERRLOG0_LOW */
+	.errlog0_high =  0x24,   /* ERL_ERRLOG0_HIGH */
+	.errlog1_low  =  0x28,   /* ERL_ERRLOG1_LOW */
+	.errlog1_high =  0x2C,   /* ERL_ERRLOG1_HIGH */
+	.errlog2_low  =  0x30,   /* ERL_ERRLOG2_LOW */
+	.errlog2_high =  0x34,   /* ERL_ERRLOG2_HIGH */
+	.errlog3_low  =  0x38,   /* ERL_ERRLOG3_LOW */
+	.errlog3_high =  0x3C,   /* ERL_ERRLOG3_HIGH */
+};
+
+static struct cam_cpas_hw_errata_wa_list cam770_cpas100_errata_wa_list = {
+};
+
+static struct cam_camnoc_info cam770_cpas100_camnoc_info = {
+	.specific = &cam_cpas_v770_100_camnoc_specific[0],
+	.specific_size = ARRAY_SIZE(cam_cpas_v770_100_camnoc_specific),
+	.irq_sbm = &cam_cpas_v770_100_irq_sbm,
+	.irq_err = &cam_cpas_v770_100_irq_err[0],
+	.irq_err_size = ARRAY_SIZE(cam_cpas_v770_100_irq_err),
+	.err_logger = &cam770_cpas100_err_logger_offsets,
+	.errata_wa_list = &cam770_cpas100_errata_wa_list,
+};
+
+static struct cam_cpas_camnoc_qchannel cam770_cpas100_qchannel_info = {
+	.qchannel_ctrl   = 0x14,
+	.qchannel_status = 0x18,
+};
+
+static struct cam_cpas_info cam770_cpas100_cpas_info = {
+	.hw_caps_info = {
+		.num_caps_registers = 1,
+		.hw_caps_offsets = {0x8},
+	},
+	.qchannel_info = {&cam770_cpas100_qchannel_info},
+	.num_qchannel = 1,
+};
+
+static struct cam_cpas_top_regs cam770_cpas100_cpas_top_info = {
+	.tpg_mux_sel_enabled = true,
+	.tpg_mux_sel_shift   = 0x0,
+	.tpg_mux_sel         = 0x1C,
+};
+
+#endif /* _CPASTOP_V770_100_H_ */
+

drivers/cam_cpas/include/cam_cpas_api.h

@@ -87,6 +87,7 @@ enum cam_cpas_camera_version {
 	CAM_CPAS_CAMERA_VERSION_880  = 0x00080800,
 	CAM_CPAS_CAMERA_VERSION_980  = 0x00090800,
 	CAM_CPAS_CAMERA_VERSION_860  = 0x00080600,
+	CAM_CPAS_CAMERA_VERSION_770  = 0x00070700,
 	CAM_CPAS_CAMERA_VERSION_MAX
 };
 
@@ -125,6 +126,7 @@ enum cam_cpas_camera_version_map_id {
 	CAM_CPAS_CAMERA_VERSION_ID_880  = 0xD,
 	CAM_CPAS_CAMERA_VERSION_ID_980  = 0xE,
 	CAM_CPAS_CAMERA_VERSION_ID_860  = 0xF,
+	CAM_CPAS_CAMERA_VERSION_ID_770  = 0x10,
 	CAM_CPAS_CAMERA_VERSION_ID_MAX
 };
 
@@ -171,6 +173,7 @@ enum cam_cpas_hw_version {
 	CAM_CPAS_TITAN_880_V100 = 0x880100,
 	CAM_CPAS_TITAN_980_V100 = 0x980100,
 	CAM_CPAS_TITAN_860_V100 = 0x860100,
+	CAM_CPAS_TITAN_770_V100 = 0x770100,
 	CAM_CPAS_TITAN_MAX
 };
 

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/cam_jpeg_dma_770_hw_info_ver_4_2_0.h

@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef CAM_JPEG_DMA_770_HW_INFO_VER_4_2_0_H
+#define CAM_JPEG_DMA_770_HW_INFO_VER_4_2_0_H
+
+#define CAM_JPEGDMA_HW_IRQ_STATUS_SESSION_DONE (1 << 0)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_RD_BUF_DONE  (1 << 1)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_WR_BUF_DONE  (1 << 5)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT     (1 << 9)
+#define CAM_JPEGDMA_HW_IRQ_STATUS_RST_DONE     (1 << 10)
+
+#define CAM_JPEG_HW_MASK_SCALE_ENABLE 0x1
+
+#define CAM_JPEGDMA_HW_MASK_COMP_FRAMEDONE \
+		CAM_JPEGDMA_HW_IRQ_STATUS_SESSION_DONE
+#define CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK \
+		CAM_JPEGDMA_HW_IRQ_STATUS_RST_DONE
+
+static struct cam_jpeg_dma_device_hw_info cam_jpeg_dma_770_hw_info = {
+	.reg_offset = {
+		.hw_version = 0x0,
+		.int_clr = 0x14,
+		.int_status = 0x10,
+		.int_mask = 0x0C,
+		.hw_cmd = 0x1C,
+		.reset_cmd = 0x08,
+		.encode_size = 0x180,
+		.core_cfg = 0x18,
+		.misr_cfg0 = 0x160,
+		.misr_cfg1 = 0x164,
+	},
+	.reg_val = {
+		.int_clr_clearall = 0xFFFFFFFF,
+		.int_mask_disable_all = 0x00000000,
+		.int_mask_enable_all = 0xFFFFFFFF,
+		.hw_cmd_start = 0x00000001,
+		.reset_cmd = 0x32083,
+		.hw_cmd_stop = 0x00000004,
+		.misr_cfg0 = 0x506,
+	},
+	.int_status = {
+		.framedone = CAM_JPEGDMA_HW_MASK_COMP_FRAMEDONE,
+		.resetdone = CAM_JPEGDMA_HW_MASK_COMP_RESET_ACK,
+		.iserror = 0x0,
+		.stopdone = CAM_JPEGDMA_HW_IRQ_STATUS_AXI_HALT,
+		.scale_enable = CAM_JPEG_HW_MASK_SCALE_ENABLE,
+		.scale_enable_shift = 0x4,
+	},
+	.camnoc_misr_reg_offset = {
+		.main_ctl = 0x8108,
+		.id_mask_low = 0x8120,
+		.id_value_low = 0x8118,
+		.misc_ctl = 0x8110,
+		.sigdata0 = 0x8150,
+	},
+	.camnoc_misr_reg_val = {
+		.main_ctl = 0x7,
+		.id_mask_low = 0xFC0,
+		.id_value_low_rd = 0xD00,
+		.id_value_low_wr = 0xD42,
+		.misc_ctl_start = 0x1,
+		.misc_ctl_stop = 0x2,
+	},
+	.max_misr = 3,
+	.max_misr_rd = 4,
+	.max_misr_wr = 4,
+	.camnoc_misr_sigdata = 4,
+	.master_we_sel = 2,
+	.misr_rd_word_sel = 4,
+	.camnoc_misr_support = 1,
+};
+
+#endif /* CAM_JPEG_DMA_770_HW_INFO_VER_4_2_0_H */

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_dev.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/module.h>
@@ -24,6 +24,7 @@
 #include "cam_jpeg_dma_580_hw_info_ver_4_2_0.h"
 #include "cam_jpeg_dma_680_hw_info_ver_4_2_0.h"
 #include "cam_jpeg_dma_780_hw_info_ver_4_2_0.h"
+#include "cam_jpeg_dma_770_hw_info_ver_4_2_0.h"
 #include "camera_main.h"
 
 static int cam_jpeg_dma_register_cpas(struct cam_hw_soc_info *soc_info,
@@ -260,6 +261,11 @@ static const struct of_device_id cam_jpeg_dma_dt_match[] = {
 		.compatible = "qcom,cam_jpeg_dma_780",
 		.data = &cam_jpeg_dma_780_hw_info,
 	},
+	{
+		.compatible = "qcom,cam_jpeg_dma_770",
+		.data = &cam_jpeg_dma_770_hw_info,
+
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, cam_jpeg_dma_dt_match);

drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_770_hw_info_ver_4_2_0.h

@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef CAM_JPEG_ENC_770_HW_INFO_TITAN170_H
+#define CAM_JPEG_ENC_770_HW_INFO_TITAN170_H
+
+#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK 0x00000001
+#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_SHIFT 0x00000000
+
+#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK 0x10000000
+#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_SHIFT 0x0000000a
+
+#define CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK 0x8000000
+#define CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_SHIFT 0x0000001b
+
+#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_MASK 0x00000800
+#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_SHIFT 0x0000000b
+
+#define CAM_JPEG_HW_MASK_SCALE_ENABLE 0x1
+
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF      (0x1<<19)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR     (0x1<<20)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR   (0x1<<21)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF (0x1<<22)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW    (0x1<<23)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM       (0x1<<24)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ   (0x1<<25)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM       (0x1<<26)
+#define CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK        (0x1<<29)
+
+#define CAM_JPEG_HW_MASK_COMP_FRAMEDONE \
+		CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK
+#define CAM_JPEG_HW_MASK_COMP_RESET_ACK \
+		CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK
+#define CAM_JPEG_HW_MASK_COMP_ERR \
+		(CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ | \
+		CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM | \
+		CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK)
+
+static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_770_hw_info = {
+	.reg_offset = {
+		.hw_version = 0x0,
+		.int_clr = 0x1c,
+		.int_status = 0x20,
+		.int_mask = 0x18,
+		.hw_cmd = 0x10,
+		.reset_cmd = 0x8,
+		.encode_size = 0x180,
+		.core_cfg = 0xc,
+		.misr_cfg = 0x2B4,
+		.misr_rd0 = 0x2B8,
+	},
+	.reg_val = {
+		.int_clr_clearall = 0xFFFFFFFF,
+		.int_mask_disable_all = 0x00000000,
+		.int_mask_enable_all = 0xFFFFFFFF,
+		.hw_cmd_start = 0x00000001,
+		.reset_cmd = 0x200320D3,
+		.hw_cmd_stop = 0x00000002,
+		.misr_cfg = 0x7,
+	},
+	.int_status = {
+		.framedone = CAM_JPEG_HW_MASK_COMP_FRAMEDONE,
+		.resetdone = CAM_JPEG_HW_MASK_COMP_RESET_ACK,
+		.iserror = CAM_JPEG_HW_MASK_COMP_ERR,
+		.stopdone = CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK,
+		.scale_enable = CAM_JPEG_HW_MASK_SCALE_ENABLE,
+		.scale_enable_shift = 0x7,
+	},
+	.reg_dump = {
+		.start_offset = 0x0,
+		.end_offset = 0x33C,
+	},
+	.camnoc_misr_reg_offset = {
+		.main_ctl = 0x8108,
+		.id_mask_low = 0x8120,
+		.id_value_low = 0x8118,
+		.misc_ctl = 0x8110,
+		.sigdata0 = 0x8150,
+	},
+	.camnoc_misr_reg_val = {
+		.main_ctl = 0x7,
+		.id_mask_low = 0xFC0,
+		.id_value_low_rd = 0xD80,
+		.id_value_low_wr = 0xDC2,
+		.misc_ctl_start = 0x1,
+		.misc_ctl_stop = 0x2,
+	},
+	.max_misr = 3,
+	.max_misr_rd = 4,
+	.camnoc_misr_sigdata = 4,
+	.camnoc_misr_support = 1,
+};
+
+#endif /* CAM_JPEG_ENC_770_HW_INFO_TITAN170_H */

drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/module.h>
@@ -24,6 +24,7 @@
 #include "cam_jpeg_enc_580_hw_info_ver_4_2_0.h"
 #include "cam_jpeg_enc_680_hw_info_ver_4_2_0.h"
 #include "cam_jpeg_enc_780_hw_info_ver_4_2_0.h"
+#include "cam_jpeg_enc_770_hw_info_ver_4_2_0.h"
 #include "camera_main.h"
 
 static int cam_jpeg_enc_register_cpas(struct cam_hw_soc_info *soc_info,
@@ -261,6 +262,10 @@ static const struct of_device_id cam_jpeg_enc_dt_match[] = {
 		.compatible = "qcom,cam_jpeg_enc_780",
 		.data = &cam_jpeg_enc_780_hw_info,
 	},
+	{
+		.compatible = "qcom,cam_jpeg_enc_770",
+		.data = &cam_jpeg_enc_770_hw_info,
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, cam_jpeg_enc_dt_match);