asoc: wsa883x: Update low_noise gain for receiver
Add changes to use wsa883x for receiver with low_noise mode settings. Change-Id: Icfa43ebbdb1e366f365053535f541bee03751ca3 Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
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@@ -272,6 +272,7 @@ struct lpass_cdc_wsa2_macro_priv {
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struct snd_soc_component *component;
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int rx_0_count;
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int rx_1_count;
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int wsa_spkrrecv;
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unsigned long active_ch_mask[LPASS_CDC_WSA2_MACRO_MAX_DAIS];
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unsigned long active_ch_cnt[LPASS_CDC_WSA2_MACRO_MAX_DAIS];
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int rx_port_value[LPASS_CDC_WSA2_MACRO_RX_MAX];
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@@ -320,6 +321,10 @@ static const char * const lpass_cdc_wsa2_macro_vbat_bcl_gsm_mode_text[] = {
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"OFF", "ON"
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};
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static const char *const lpass_cdc_wsa2_macro_ear_spkrrecv_text[] = {
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"OFF", "ON"
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};
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static const char * const lpass_cdc_wsa2_macro_comp_mode_text[] = {
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"G_21_DB", "G_19P5_DB", "G_18_DB", "G_16P5_DB", "G_15_DB",
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"G_13P5_DB", "G_12_DB", "G_10P5_DB", "G_9_DB"
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@@ -333,6 +338,8 @@ static const struct snd_kcontrol_new wsa2_int1_vbat_mix_switch[] = {
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SOC_DAPM_SINGLE("WSA2 RX1 VBAT Enable", SND_SOC_NOPM, 0, 1, 0)
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};
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static SOC_ENUM_SINGLE_EXT_DECL(lpass_cdc_wsa2_macro_ear_spkrrecv_enum,
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lpass_cdc_wsa2_macro_ear_spkrrecv_text);
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static SOC_ENUM_SINGLE_EXT_DECL(lpass_cdc_wsa2_macro_vbat_bcl_gsm_mode_enum,
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lpass_cdc_wsa2_macro_vbat_bcl_gsm_mode_text);
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static SOC_ENUM_SINGLE_EXT_DECL(lpass_cdc_wsa2_macro_comp_mode_enum,
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@@ -1526,6 +1533,9 @@ static int lpass_cdc_wsa2_macro_enable_interpolator(struct snd_soc_dapm_widget *
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u8 gain = 0;
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u16 reg = 0;
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if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
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return -EINVAL;
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if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
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return -EINVAL;
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@@ -2027,6 +2037,43 @@ static int lpass_cdc_wsa2_macro_set_compander(struct snd_kcontrol *kcontrol,
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return 0;
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}
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static int lpass_cdc_wsa2_macro_ear_spkrrecv_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component =
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snd_soc_kcontrol_component(kcontrol);
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struct device *wsa2_dev = NULL;
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struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
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if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
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return -EINVAL;
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ucontrol->value.integer.value[0] = wsa2_priv->wsa_spkrrecv;
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dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
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__func__, ucontrol->value.integer.value[0]);
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return 0;
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}
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static int lpass_cdc_wsa2_macro_ear_spkrrecv_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component =
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snd_soc_kcontrol_component(kcontrol);
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struct device *wsa2_dev = NULL;
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struct lpass_cdc_wsa2_macro_priv *wsa2_priv = NULL;
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if (!lpass_cdc_wsa2_macro_get_data(component, &wsa2_dev, &wsa2_priv, __func__))
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return -EINVAL;
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wsa2_priv->wsa_spkrrecv = ucontrol->value.integer.value[0];
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dev_dbg(component->dev, "%s:spkrrecv status = %d\n",
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__func__, wsa2_priv->wsa_spkrrecv);
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return 0;
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}
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static int lpass_cdc_wsa2_macro_comp_mode_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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@@ -2238,6 +2285,9 @@ static int lpass_cdc_wsa2_macro_soft_clip_enable_put(struct snd_kcontrol *kcontr
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}
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static const struct snd_kcontrol_new lpass_cdc_wsa2_macro_snd_controls[] = {
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SOC_ENUM_EXT("WSA2 SPKRRECV", lpass_cdc_wsa2_macro_ear_spkrrecv_enum,
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lpass_cdc_wsa2_macro_ear_spkrrecv_get,
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lpass_cdc_wsa2_macro_ear_spkrrecv_put),
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SOC_ENUM_EXT("WSA2_GSM mode Enable", lpass_cdc_wsa2_macro_vbat_bcl_gsm_mode_enum,
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lpass_cdc_wsa2_macro_vbat_bcl_gsm_mode_func_get,
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lpass_cdc_wsa2_macro_vbat_bcl_gsm_mode_func_put),
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@@ -2658,10 +2708,10 @@ static const struct lpass_cdc_wsa2_macro_reg_mask_val
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lpass_cdc_wsa2_macro_reg_init[] = {
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{LPASS_CDC_WSA2_BOOST0_BOOST_CFG1, 0x3F, 0x12},
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{LPASS_CDC_WSA2_BOOST0_BOOST_CFG2, 0x1C, 0x08},
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{LPASS_CDC_WSA2_COMPANDER0_CTL7, 0x1E, 0x0C},
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{LPASS_CDC_WSA2_COMPANDER0_CTL7, 0x1E, 0x18},
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{LPASS_CDC_WSA2_BOOST1_BOOST_CFG1, 0x3F, 0x12},
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{LPASS_CDC_WSA2_BOOST1_BOOST_CFG2, 0x1C, 0x08},
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{LPASS_CDC_WSA2_COMPANDER1_CTL7, 0x1E, 0x0C},
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{LPASS_CDC_WSA2_COMPANDER1_CTL7, 0x1E, 0x18},
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{LPASS_CDC_WSA2_BOOST0_BOOST_CTL, 0x70, 0x58},
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{LPASS_CDC_WSA2_BOOST1_BOOST_CTL, 0x70, 0x58},
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{LPASS_CDC_WSA2_RX0_RX_PATH_CFG1, 0x08, 0x08},
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