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@@ -62,6 +62,7 @@ MODULE_LICENSE("GPL");
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#define QNS4_PARAMS 0x1124
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#define OVERRIDE 0x112C
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#define VERSION_CONTROL 0x1130
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+#define SPARE 0x1188
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/* read/write register */
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@@ -363,9 +364,12 @@ void ubwcp_hw_one_time_init(void __iomem *base)
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u32 reg;
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/* hack: set dataless hazard override bit */
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- reg = UBWCP_REG_READ(base, OVERRIDE);
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UBWCP_REG_WRITE(base, OVERRIDE, 0x2000);
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- reg = UBWCP_REG_READ(base, OVERRIDE);
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+
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+ /* Spare reg config: set bit-9: SCC & bit-1: padding */
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+ reg = UBWCP_REG_READ(base, SPARE);
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+ reg |= BIT(9) | BIT(1);
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+ UBWCP_REG_WRITE(base, SPARE, reg);
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/* Configure SID */
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reg = UBWCP_REG_READ(base, QNS4_PARAMS);
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@@ -373,7 +377,6 @@ void ubwcp_hw_one_time_init(void __iomem *base)
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reg |= 0x1; /* desc buffer */
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reg |= (0 << 3); /* pixel data */
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UBWCP_REG_WRITE(base, QNS4_PARAMS, reg);
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- reg = UBWCP_REG_READ(base, QNS4_PARAMS);
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ubwcp_hw_decoder_config(base);
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ubwcp_hw_encoder_config(base);
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