disp: pll: fix flags for DSI and DP PLL clocks

Remove the CLK_GET_RATE_NOCACHE flag from all the DP and DSI
pll clocks. This will eliminate the need to recalculate the
clock rates from HW registers when querying the rates for the
PLL clocks. This will ensure that no unclocked register accesses
are done when these clocks are queried while the display core
is power collapsed.

Change-Id: Ia5e993195cadc2bced32c052bb604e9980ecd4d8
Signed-off-by: Aravind Venkateswaran <[email protected]>

pll/dp_pll_7nm.c

@@ -109,7 +109,7 @@ static struct clk_fixed_factor dp_link_clk_divsel_ten = {
 		.parent_names =
 			(const char *[]){ "dp_vco_clk" },
 		.num_parents = 1,
-		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_fixed_factor_ops,
 	},
 };
@@ -123,7 +123,6 @@ static struct clk_fixed_factor dp_vco_divsel_two_clk_src = {
 		.parent_names =
 			(const char *[]){ "dp_vco_clk" },
 		.num_parents = 1,
-		.flags = (CLK_GET_RATE_NOCACHE),
 		.ops = &clk_fixed_factor_ops,
 	},
 };
@@ -137,7 +136,6 @@ static struct clk_fixed_factor dp_vco_divsel_four_clk_src = {
 		.parent_names =
 			(const char *[]){ "dp_vco_clk" },
 		.num_parents = 1,
-		.flags = (CLK_GET_RATE_NOCACHE),
 		.ops = &clk_fixed_factor_ops,
 	},
 };
@@ -151,7 +149,6 @@ static struct clk_fixed_factor dp_vco_divsel_six_clk_src = {
 		.parent_names =
 			(const char *[]){ "dp_vco_clk" },
 		.num_parents = 1,
-		.flags = (CLK_GET_RATE_NOCACHE),
 		.ops = &clk_fixed_factor_ops,
 	},
 };
@@ -223,7 +220,7 @@ static struct clk_regmap_mux dp_vco_divided_clk_src_mux = {
 					"dp_vco_divsel_six_clk_src"},
 			.num_parents = 3,
 			.ops = &mux_clk_ops,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = CLK_SET_RATE_PARENT,
 		},
 	},
 };

pll/dsi_pll_7nm.c

@@ -1467,7 +1467,6 @@ static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
 			.parent_names = (const char *[]){"bi_tcxo"},
 			.num_parents = 1,
 			.ops = &clk_ops_vco_7nm,
-			.flags = CLK_GET_RATE_NOCACHE,
 	},
 };
 
@@ -1480,7 +1479,6 @@ static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
 			.parent_names = (const char *[]){"bi_tcxo"},
 			.num_parents = 1,
 			.ops = &clk_ops_vco_7nm,
-			.flags = CLK_GET_RATE_NOCACHE,
 	},
 };
 
@@ -1494,7 +1492,7 @@ static struct clk_regmap_div dsi0pll_pll_out_div = {
 			.name = "dsi0pll_pll_out_div",
 			.parent_names = (const char *[]){"dsi0pll_vco_clk"},
 			.num_parents = 1,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_regmap_div_ops,
 		},
 	},
@@ -1510,7 +1508,7 @@ static struct clk_regmap_div dsi1pll_pll_out_div = {
 			.name = "dsi1pll_pll_out_div",
 			.parent_names = (const char *[]){"dsi1pll_vco_clk"},
 			.num_parents = 1,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_regmap_div_ops,
 		},
 	},
@@ -1524,7 +1522,7 @@ static struct clk_regmap_div dsi0pll_bitclk_src = {
 			.name = "dsi0pll_bitclk_src",
 			.parent_names = (const char *[]){"dsi0pll_pll_out_div"},
 			.num_parents = 1,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_regmap_div_ops,
 		},
 	},
@@ -1538,7 +1536,7 @@ static struct clk_regmap_div dsi1pll_bitclk_src = {
 			.name = "dsi1pll_bitclk_src",
 			.parent_names = (const char *[]){"dsi1pll_pll_out_div"},
 			.num_parents = 1,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_regmap_div_ops,
 		},
 	},
@@ -1551,7 +1549,7 @@ static struct clk_fixed_factor dsi0pll_post_vco_div = {
 		.name = "dsi0pll_post_vco_div",
 		.parent_names = (const char *[]){"dsi0pll_pll_out_div"},
 		.num_parents = 1,
-		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_fixed_factor_ops,
 	},
 };
@@ -1563,7 +1561,7 @@ static struct clk_fixed_factor dsi1pll_post_vco_div = {
 		.name = "dsi1pll_post_vco_div",
 		.parent_names = (const char *[]){"dsi1pll_pll_out_div"},
 		.num_parents = 1,
-		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_fixed_factor_ops,
 	},
 };
@@ -1575,7 +1573,7 @@ static struct clk_fixed_factor dsi0pll_byteclk_src = {
 		.name = "dsi0pll_byteclk_src",
 		.parent_names = (const char *[]){"dsi0pll_bitclk_src"},
 		.num_parents = 1,
-		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_fixed_factor_ops,
 	},
 };
@@ -1587,7 +1585,7 @@ static struct clk_fixed_factor dsi1pll_byteclk_src = {
 		.name = "dsi1pll_byteclk_src",
 		.parent_names = (const char *[]){"dsi1pll_bitclk_src"},
 		.num_parents = 1,
-		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_fixed_factor_ops,
 	},
 };
@@ -1599,7 +1597,6 @@ static struct clk_fixed_factor dsi0pll_post_bit_div = {
 		.name = "dsi0pll_post_bit_div",
 		.parent_names = (const char *[]){"dsi0pll_bitclk_src"},
 		.num_parents = 1,
-		.flags = CLK_GET_RATE_NOCACHE,
 		.ops = &clk_fixed_factor_ops,
 	},
 };
@@ -1611,7 +1608,6 @@ static struct clk_fixed_factor dsi1pll_post_bit_div = {
 		.name = "dsi1pll_post_bit_div",
 		.parent_names = (const char *[]){"dsi1pll_bitclk_src"},
 		.num_parents = 1,
-		.flags = CLK_GET_RATE_NOCACHE,
 		.ops = &clk_fixed_factor_ops,
 	},
 };
@@ -1624,7 +1620,7 @@ static struct clk_regmap_mux dsi0pll_byteclk_mux = {
 			.name = "dsi0_phy_pll_out_byteclk",
 			.parent_names = (const char *[]){"dsi0pll_byteclk_src"},
 			.num_parents = 1,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_regmap_mux_closest_ops,
 		},
 	},
@@ -1638,7 +1634,7 @@ static struct clk_regmap_mux dsi1pll_byteclk_mux = {
 			.name = "dsi1_phy_pll_out_byteclk",
 			.parent_names = (const char *[]){"dsi1pll_byteclk_src"},
 			.num_parents = 1,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_regmap_mux_closest_ops,
 		},
 	},
@@ -1656,7 +1652,6 @@ static struct clk_regmap_mux dsi0pll_pclk_src_mux = {
 					"dsi0pll_pll_out_div",
 					"dsi0pll_post_vco_div"},
 			.num_parents = 4,
-			.flags = CLK_GET_RATE_NOCACHE,
 			.ops = &clk_regmap_mux_closest_ops,
 		},
 	},
@@ -1674,7 +1669,6 @@ static struct clk_regmap_mux dsi1pll_pclk_src_mux = {
 					"dsi1pll_pll_out_div",
 					"dsi1pll_post_vco_div"},
 			.num_parents = 4,
-			.flags = CLK_GET_RATE_NOCACHE,
 			.ops = &clk_regmap_mux_closest_ops,
 		},
 	},
@@ -1689,7 +1683,7 @@ static struct clk_regmap_div dsi0pll_pclk_src = {
 			.parent_names = (const char *[]){
 					"dsi0pll_pclk_src_mux"},
 			.num_parents = 1,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_regmap_div_ops,
 		},
 	},
@@ -1704,7 +1698,7 @@ static struct clk_regmap_div dsi1pll_pclk_src = {
 			.parent_names = (const char *[]){
 					"dsi1pll_pclk_src_mux"},
 			.num_parents = 1,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_regmap_div_ops,
 		},
 	},
@@ -1718,7 +1712,7 @@ static struct clk_regmap_mux dsi0pll_pclk_mux = {
 			.name = "dsi0_phy_pll_out_dsiclk",
 			.parent_names = (const char *[]){"dsi0pll_pclk_src"},
 			.num_parents = 1,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_regmap_mux_closest_ops,
 		},
 	},
@@ -1732,7 +1726,7 @@ static struct clk_regmap_mux dsi1pll_pclk_mux = {
 			.name = "dsi1_phy_pll_out_dsiclk",
 			.parent_names = (const char *[]){"dsi1pll_pclk_src"},
 			.num_parents = 1,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_regmap_mux_closest_ops,
 		},
 	},