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disp: msm: use upstream dsc config data

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This change enforces dp, dsi and the sde drivers to use the
drm framework defined dsc_config data structure. As a part of this,
it introduces the sde_dsc_helper API to configure the dsc params
and creating a PPS command. Earlier each driver implemented it's
private versions leading to duplication of code. Additionaly the
helper api supports DSC spec 1.2 422 and 420 mode.

Change-Id: I25933fab08cdabbc6787079926885d1a78945e97
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This commit is contained in:
Abhijit Kulkarni
2019-05-14 10:21:07 -07:00
rodzic 673ebb896c
commit acb8d98e66
14 zmienionych plików z 705 dodań i 930 usunięć
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4
msm/sde/sde_encoder.c
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@@ -3492,6 +3492,7 @@ static void _sde_encoder_setup_dither(struct sde_encoder_phys *phys)
struct msm_display_dsc_info *dsc = NULL;
struct sde_encoder_virt *sde_enc;
struct sde_hw_pingpong *hw_pp;
u16 bpp;
if (!phys || !phys->connector || !phys->hw_pp ||
!phys->hw_pp->ops.setup_dither || !phys->parent)
@@ -3506,7 +3507,8 @@ static void _sde_encoder_setup_dither(struct sde_encoder_phys *phys)
sde_enc = to_sde_encoder_virt(drm_enc);
dsc = &sde_enc->mode_info.comp_info.dsc_info;
/* disable dither for 10 bpp or 10bpc dsc config */
if (dsc->bpp == 10 || dsc->bpc == 10) {
bpp = DSC_BPP(dsc->config);
if (bpp == 10 || dsc->config.bits_per_component == 10) {
phys->hw_pp->ops.setup_dither(phys->hw_pp, NULL, 0);
return;
}

72
msm/sde/sde_encoder_dce.c
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@@ -23,6 +23,7 @@
#include "sde_crtc.h"
#include "sde_trace.h"
#include "sde_core_irq.h"
#include "sde_dsc_helper.h"
#define SDE_DEBUG_DCE(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
(e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
@@ -55,7 +56,6 @@ bool sde_encoder_is_dsc_merge(struct drm_encoder *drm_enc)
}
static int _dce_dsc_update_pic_dim(struct msm_display_dsc_info *dsc,
int pic_width, int pic_height)
{
if (!dsc || !pic_width || !pic_height) {
@@ -64,53 +64,20 @@ static int _dce_dsc_update_pic_dim(struct msm_display_dsc_info *dsc,
return -EINVAL;
}
if ((pic_width % dsc->slice_width) ||
(pic_height % dsc->slice_height)) {
if ((pic_width % dsc->config.slice_width) ||
(pic_height % dsc->config.slice_height)) {
SDE_ERROR("pic_dim=%dx%d has to be multiple of slice=%dx%d\n",
pic_width, pic_height,
dsc->slice_width, dsc->slice_height);
dsc->config.slice_width, dsc->config.slice_height);
return -EINVAL;
}
dsc->pic_width = pic_width;
dsc->pic_height = pic_height;
dsc->config.pic_width = pic_width;
dsc->config.pic_height = pic_height;
return 0;
}
static void _dce_dsc_pclk_param_calc(struct msm_display_dsc_info *dsc,
int intf_width)
{
int slice_per_pkt, slice_per_intf;
int bytes_in_slice, total_bytes_per_intf;
if (!dsc || !dsc->slice_width || !dsc->slice_per_pkt ||
(intf_width < dsc->slice_width)) {
SDE_ERROR("invalid input: intf_width=%d slice_width=%d\n",
intf_width, dsc ? dsc->slice_width : -1);
return;
}
slice_per_pkt = dsc->slice_per_pkt;
slice_per_intf = DIV_ROUND_UP(intf_width, dsc->slice_width);
/*
* If slice_per_pkt is greater than slice_per_intf then default to 1.
* This can happen during partial update.
*/
if (slice_per_pkt > slice_per_intf)
slice_per_pkt = 1;
bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * dsc->bpp, 8);
total_bytes_per_intf = bytes_in_slice * slice_per_intf;
dsc->eol_byte_num = total_bytes_per_intf % 3;
dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
dsc->bytes_in_slice = bytes_in_slice;
dsc->bytes_per_pkt = bytes_in_slice * slice_per_pkt;
dsc->pkt_per_line = slice_per_intf / slice_per_pkt;
}
static int _dce_dsc_initial_line_calc(struct msm_display_dsc_info *dsc,
int enc_ip_width,
int dsc_cmn_mode)
@@ -124,20 +91,23 @@ static int _dce_dsc_initial_line_calc(struct msm_display_dsc_info *dsc,
int output_rate_ratio_complement, container_slice_width;
int rtl_num_components, multi_hs_c, multi_hs_d;
int bpc = dsc->config.bits_per_component;
int bpp = DSC_BPP(dsc->config);
int num_of_active_ss = dsc->config.slice_count;
bool native_422 = dsc->config.native_422;
bool native_420 = dsc->config.native_420;
/* Hardent core config */
int multiplex_mode_enable = 0, split_panel_enable = 0;
int rtl_max_bpc = 10, rtl_output_data_width = 64;
int pipeline_latency = 28;
int bpc = dsc->bpc, bpp = dsc->bpp;
int num_of_active_ss = dsc->full_frame_slices;
bool native_422 = false, native_420 = false;
if (dsc_cmn_mode & DSC_MODE_MULTIPLEX)
multiplex_mode_enable = 1;
if (dsc_cmn_mode & DSC_MODE_SPLIT_PANEL)
split_panel_enable = 0;
container_slice_width = (native_422 ?
dsc->slice_width / 2 : dsc->slice_width);
dsc->config.slice_width / 2 : dsc->config.slice_width);
max_muxword_size = ((rtl_max_bpc >= 12) ? 64 : 48);
max_se_size = 4 * (rtl_max_bpc + 1);
max_ssm_delay = max_se_size + max_muxword_size - 1;
@@ -156,9 +126,9 @@ static int _dce_dsc_initial_line_calc(struct msm_display_dsc_info *dsc,
ob_data_width_4comps : ob_data_width_3comps);
obuf_latency = DIV_ROUND_UP((9 * ob_data_width + mux_word_size),
compress_bpp_group) + 1;
base_hs_latency = dsc->initial_xmit_delay + input_ssm_out_latency
+ obuf_latency;
chunk_bits = 8 * dsc->chunk_size;
base_hs_latency = dsc->config.initial_xmit_delay +
input_ssm_out_latency + obuf_latency;
chunk_bits = 8 * dsc->config.slice_chunk_size;
output_rate_ratio_complement = ob_data_width - compress_bpp_group;
output_rate_extra_budget_bits =
(output_rate_ratio_complement * chunk_bits) >>
@@ -196,8 +166,8 @@ static bool _dce_dsc_ich_reset_override_needed(bool pu_en,
* then HW will generate ich_reset at end of the slice. This is a
* mismatch. Prevent this by overriding HW's decision.
*/
return pu_en && dsc && (dsc->full_frame_slices > 1) &&
(dsc->slice_width == dsc->pic_width);
return pu_en && dsc && (dsc->config.slice_count > 1) &&
(dsc->config.slice_width == dsc->config.pic_width);
}
static void _dce_dsc_pipe_cfg(struct sde_hw_dsc *hw_dsc,
@@ -330,13 +300,13 @@ static int _dce_dsc_setup(struct sde_encoder_virt *sde_enc,
if (enc_master->intf_mode == INTF_MODE_VIDEO)
dsc_common_mode |= DSC_MODE_VIDEO;
this_frame_slices = roi->w / dsc->slice_width;
intf_ip_w = this_frame_slices * dsc->slice_width;
this_frame_slices = roi->w / dsc->config.slice_width;
intf_ip_w = this_frame_slices * dsc->config.slice_width;
if ((!half_panel_partial_update) && (num_intf > 1))
intf_ip_w /= 2;
_dce_dsc_pclk_param_calc(dsc, intf_ip_w);
sde_dsc_populate_dsc_private_params(dsc, intf_ip_w);
/*
* in dsc merge case: when using 2 encoders for the same stream,

86
msm/sde/sde_hw_dsc.c
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/
#include "sde_hw_mdss.h"
@@ -58,101 +58,101 @@ static void sde_hw_dsc_config(struct sde_hw_dsc *hw_dsc,
data |= (initial_lines << 20);
data |= (dsc->slice_last_group_size << 18);
data |= (dsc->bpp << 12);
data |= (dsc->block_pred_enable << 7);
data |= (dsc->line_buf_depth << 3);
data |= (dsc->enable_422 << 2);
data |= (dsc->convert_rgb << 1);
data |= dsc->input_10_bits;
/* integer bpp support only */
data |= (dsc->config.bits_per_pixel << 8);
data |= (dsc->config.block_pred_enable << 7);
data |= (dsc->config.line_buf_depth << 3);
data |= (dsc->config.simple_422 << 2);
data |= (dsc->config.convert_rgb << 1);
if (dsc->config.bits_per_component == 10)
data |= BIT(0);
SDE_REG_WRITE(dsc_c, DSC_ENC, data);
data = dsc->pic_width << 16;
data |= dsc->pic_height;
data = dsc->config.pic_width << 16;
data |= dsc->config.pic_height;
SDE_REG_WRITE(dsc_c, DSC_PICTURE, data);
data = dsc->slice_width << 16;
data |= dsc->slice_height;
data = dsc->config.slice_width << 16;
data |= dsc->config.slice_height;
SDE_REG_WRITE(dsc_c, DSC_SLICE, data);
data = dsc->chunk_size << 16;
data = dsc->config.slice_chunk_size << 16;
SDE_REG_WRITE(dsc_c, DSC_CHUNK_SIZE, data);
data = dsc->initial_dec_delay << 16;
data |= dsc->initial_xmit_delay;
data = dsc->config.initial_dec_delay << 16;
data |= dsc->config.initial_xmit_delay;
SDE_REG_WRITE(dsc_c, DSC_DELAY, data);
data = dsc->initial_scale_value;
data = dsc->config.initial_scale_value;
SDE_REG_WRITE(dsc_c, DSC_SCALE_INITIAL, data);
data = dsc->scale_decrement_interval;
data = dsc->config.scale_decrement_interval;
SDE_REG_WRITE(dsc_c, DSC_SCALE_DEC_INTERVAL, data);
data = dsc->scale_increment_interval;
data = dsc->config.scale_increment_interval;
SDE_REG_WRITE(dsc_c, DSC_SCALE_INC_INTERVAL, data);
data = dsc->first_line_bpg_offset;
data = dsc->config.first_line_bpg_offset;
SDE_REG_WRITE(dsc_c, DSC_FIRST_LINE_BPG_OFFSET, data);
data = dsc->nfl_bpg_offset << 16;
data |= dsc->slice_bpg_offset;
data = dsc->config.nfl_bpg_offset << 16;
data |= dsc->config.slice_bpg_offset;
SDE_REG_WRITE(dsc_c, DSC_BPG_OFFSET, data);
data = dsc->initial_offset << 16;
data |= dsc->final_offset;
data = dsc->config.initial_offset << 16;
data |= dsc->config.final_offset;
SDE_REG_WRITE(dsc_c, DSC_DSC_OFFSET, data);
data = dsc->det_thresh_flatness << 10;
data |= dsc->max_qp_flatness << 5;
data |= dsc->min_qp_flatness;
data |= dsc->config.flatness_max_qp << 5;
data |= dsc->config.flatness_min_qp;
SDE_REG_WRITE(dsc_c, DSC_FLATNESS, data);
data = dsc->rc_model_size;
data = dsc->config.rc_model_size;
SDE_REG_WRITE(dsc_c, DSC_RC_MODEL_SIZE, data);
data = dsc->tgt_offset_lo << 18;
data |= dsc->tgt_offset_hi << 14;
data |= dsc->quant_incr_limit1 << 9;
data |= dsc->quant_incr_limit0 << 4;
data |= dsc->edge_factor;
data = dsc->config.rc_tgt_offset_low << 18;
data |= dsc->config.rc_tgt_offset_high << 14;
data |= dsc->config.rc_quant_incr_limit1 << 9;
data |= dsc->config.rc_quant_incr_limit0 << 4;
data |= dsc->config.rc_edge_factor;
SDE_REG_WRITE(dsc_c, DSC_RC, data);
}
static void sde_hw_dsc_config_thresh(struct sde_hw_dsc *hw_dsc,
struct msm_display_dsc_info *dsc)
{
u32 *lp;
char *cp;
u16 *lp;
int i;
struct sde_hw_blk_reg_map *dsc_c = &hw_dsc->hw;
u32 off = 0x0;
struct drm_dsc_rc_range_parameters *rc =
dsc->config.rc_range_params;
lp = dsc->buf_thresh;
lp = dsc->config.rc_buf_thresh;
off = DSC_RC_BUF_THRESH;
for (i = 0; i < 14; i++) {
for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
SDE_REG_WRITE(dsc_c, off, *lp++);
off += 4;
}
cp = dsc->range_min_qp;
off = DSC_RANGE_MIN_QP;
for (i = 0; i < 15; i++) {
SDE_REG_WRITE(dsc_c, off, *cp++);
for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
SDE_REG_WRITE(dsc_c, off, rc[i].range_min_qp);
off += 4;
}
cp = dsc->range_max_qp;
off = DSC_RANGE_MAX_QP;
for (i = 0; i < 15; i++) {
SDE_REG_WRITE(dsc_c, off, *cp++);
for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
SDE_REG_WRITE(dsc_c, off, rc[i].range_max_qp);
off += 4;
}
cp = dsc->range_bpg_offset;
off = DSC_RANGE_BPG_OFFSET;
for (i = 0; i < 15; i++) {
SDE_REG_WRITE(dsc_c, off, *cp++);
for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
SDE_REG_WRITE(dsc_c, off, rc[i].range_bpg_offset);
off += 4;
}
}