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Merge "msm: ipa3: EoGRE feature"

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This commit is contained in:
qctecmdr
2021-06-03 20:47:00 -07:00
committed by Gerrit - the friendly Code Review server
parent 4e50a61fc3 706a1de8cc
commit ab5ba65d1e
9 changed files with 462 additions and 14 deletions
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68
drivers/platform/msm/ipa/ipa_v3/ipa.c
View File

@@ -2314,6 +2314,8 @@ static long ipa3_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
struct ipa_ioc_nat_dma_cmd *table_dma_cmd;
struct ipa_ioc_get_vlan_mode vlan_mode;
struct ipa_ioc_wigig_fst_switch fst_switch;
struct ipa_ioc_eogre_info eogre_info;
bool send2uC, send2ipacm;
size_t sz;
int pre_entry;
int hdl;
@@ -3618,6 +3620,66 @@ static long ipa3_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
if (ipa3_send_pkt_threshold(arg))
retval = -EFAULT;
break;
case IPA_IOC_ADD_EoGRE_MAPPING:
if (copy_from_user(
&eogre_info,
(const void __user *) arg,
sizeof(struct ipa_ioc_eogre_info))) {
IPAERR_RL("copy_from_user fails\n");
retval = -EFAULT;
break;
}
retval = ipa3_check_eogre(&eogre_info, &send2uC, &send2ipacm);
if (retval == 0 && send2uC == true) {
/*
* Send map to uC...
*/
retval = ipa3_add_dscp_vlan_pcp_map(
&eogre_info.map_info);
}
if (retval == 0 && send2ipacm == true) {
/*
* Send ip addrs to ipacm...
*/
retval = ipa3_send_eogre_info(IPA_EoGRE_UP_EVENT, &eogre_info);
}
if (retval == 0) {
ipa3_ctx->eogre_enabled = true;
}
break;
case IPA_IOC_DEL_EoGRE_MAPPING:
memset(&eogre_info, 0, sizeof(eogre_info));
retval = ipa3_check_eogre(&eogre_info, &send2uC, &send2ipacm);
if (retval == 0 && send2uC == true) {
/*
* Send map clear to uC...
*/
retval = ipa3_add_dscp_vlan_pcp_map(
&eogre_info.map_info);
}
if (retval == 0 && send2ipacm == true) {
/*
* Send null ip addrs to ipacm...
*/
retval = ipa3_send_eogre_info(IPA_EoGRE_DOWN_EVENT, &eogre_info);
}
if (retval == 0) {
ipa3_ctx->eogre_enabled = false;
}
break;
default:
IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
return -ENOTTY;
@@ -5702,6 +5764,12 @@ long compat_ipa3_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
case IPA_IOC_APP_CLOCK_VOTE32:
cmd = IPA_IOC_APP_CLOCK_VOTE;
break;
case IPA_IOC_ADD_EoGRE_MAPPING32:
cmd = IPA_IOC_ADD_EoGRE_MAPPING;
break;
case IPA_IOC_DEL_EoGRE_MAPPING32:
cmd = IPA_IOC_DEL_EoGRE_MAPPING;
break;
case IPA_IOC_COMMIT_HDR:
case IPA_IOC_RESET_HDR:
case IPA_IOC_COMMIT_RT:

5
drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c
View File

@@ -92,6 +92,8 @@ const char *ipa3_event_name[IPA_EVENT_MAX_NUM] = {
__stringify(IPA_MAC_FLT_EVENT),
__stringify(IPA_DONE_RESTORE_EVENT),
__stringify(IPA_SW_FLT_EVENT),
__stringify(IPA_EoGRE_UP_EVENT),
__stringify(IPA_EoGRE_DOWN_EVENT),
};
const char *ipa3_hdr_l2_type_name[] = {
@@ -112,6 +114,9 @@ const char *ipa3_hdr_proc_type_name[] = {
__stringify(IPA_HDR_PROC_ETHII_TO_ETHII_EX),
__stringify(IPA_HDR_PROC_L2TP_UDP_HEADER_ADD),
__stringify(IPA_HDR_PROC_L2TP_UDP_HEADER_REMOVE),
__stringify(IPA_HDR_PROC_SET_DSCP),
__stringify(IPA_HDR_PROC_EoGRE_HEADER_ADD),
__stringify(IPA_HDR_PROC_EoGRE_HEADER_REMOVE),
};
static struct dentry *dent;

2
drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c
View File

@@ -107,6 +107,7 @@ static int ipa3_hdr_proc_ctx_to_hw_format(struct ipa_mem_buffer *mem,
(entry->hdr->is_lcl) ? hdr_lcl_addr : hdr_sys_addr,
entry->hdr->offset_entry,
&entry->l2tp_params,
&entry->eogre_params,
&entry->generic_params,
ipa3_ctx->use_64_bit_dma_mask);
if (ret)
@@ -448,6 +449,7 @@ static int __ipa_add_hdr_proc_ctx(struct ipa_hdr_proc_ctx_add *proc_ctx,
entry->type = proc_ctx->type;
entry->hdr = hdr_entry;
entry->l2tp_params = proc_ctx->l2tp_params;
entry->eogre_params = proc_ctx->eogre_params;
entry->generic_params = proc_ctx->generic_params;
if (add_ref_hdr)
hdr_entry->ref_cnt++;

32
drivers/platform/msm/ipa/ipa_v3/ipa_i.h
View File

@@ -498,6 +498,12 @@ enum {
#define IPA_IOC_APP_CLOCK_VOTE32 _IOWR(IPA_IOC_MAGIC, \
IPA_IOCTL_APP_CLOCK_VOTE, \
compat_uptr_t)
#define IPA_IOC_ADD_EoGRE_MAPPING32 _IOWR(IPA_IOC_MAGIC, \
IPA_IOCTL_ADD_EoGRE_MAPPING, \
compat_uptr_t)
#define IPA_IOC_DEL_EoGRE_MAPPING32 _IOWR(IPA_IOC_MAGIC, \
IPA_IOCTL_DEL_EoGRE_MAPPING, \
compat_uptr_t)
#endif /* #ifdef CONFIG_COMPAT */
#define IPA_TZ_UNLOCK_ATTRIBUTE 0x0C0311
@@ -836,6 +842,7 @@ struct ipa3_hdr_proc_ctx_entry {
u32 cookie;
enum ipa_hdr_proc_type type;
struct ipa_l2tp_hdr_proc_ctx_params l2tp_params;
struct ipa_eogre_hdr_proc_ctx_params eogre_params;
struct ipa_eth_II_to_eth_II_ex_procparams generic_params;
struct ipa3_hdr_proc_ctx_offset_entry *offset_entry;
struct ipa3_hdr_entry *hdr;
@@ -2308,6 +2315,8 @@ struct ipa3_context {
u32 gsi_rmnet_ll_evt_ring_intvec;
u32 gsi_rmnet_ll_evt_ring_irq;
bool use_tput_est_ep;
struct ipa_ioc_eogre_info eogre_cache;
bool eogre_enabled;
};
struct ipa3_plat_drv_res {
@@ -3495,4 +3504,27 @@ bool ipa3_is_modem_up(void);
/* set modem is up */
void ipa3_set_modem_up(bool is_up);
int ipa3_qmi_reg_dereg_for_bw(bool bw_reg_dereg);
/*
* To check if the eogre is worthy of sending to recipients who would
* use the data.
*/
int ipa3_check_eogre(
struct ipa_ioc_eogre_info *eogre_info,
bool *send2uC,
bool *send2ipacm );
/*
* To send map information to uC
*/
int ipa3_add_dscp_vlan_pcp_map(
struct IpaDscpVlanPcpMap_t *map );
/*
* To send enable/disable information to ipacm
*/
int ipa3_send_eogre_info(
enum ipa_eogre_event etype,
struct ipa_ioc_eogre_info *info );
#endif /* _IPA3_I_H_ */

66
drivers/platform/msm/ipa/ipa_v3/ipa_uc.c
View File

@@ -55,6 +55,7 @@
* IPA_CPU_2_HW_CMD_DEL_HOLB_MONITOR: Command to delete GSI channel to HOLB
* monitor.
* IPA_CPU_2_HW_CMD_DISABLE_HOLB_MONITOR: Command to disable HOLB monitoring.
* IPA_CPU_2_HW_CMD_ADD_EOGRE_MAPPING: Command to create/update GRE mapping
*/
enum ipa3_cpu_2_hw_commands {
IPA_CPU_2_HW_CMD_NO_OP =
@@ -97,6 +98,8 @@ enum ipa3_cpu_2_hw_commands {
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 19),
IPA_CPU_2_HW_CMD_DISABLE_HOLB_MONITOR =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 20),
IPA_CPU_2_HW_CMD_ADD_EOGRE_MAPPING =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 21),
};
/**
@@ -1079,8 +1082,8 @@ send_cmd:
goto send_cmd;
}
IPAERR("Received status %u, Expected status %u\n",
ipa3_ctx->uc_ctx.uc_status, expected_status);
IPAERR("uC cmd(%u): Received status %u, Expected status %u\n",
opcode, ipa3_ctx->uc_ctx.uc_status, expected_status);
IPA3_UC_UNLOCK(flags);
return -EFAULT;
}
@@ -1983,3 +1986,62 @@ int ipa3_uc_send_update_flow_control(uint32_t bitmask,
IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
return res;
}
/**
* ipa3_add_dscp_vlan_pcp_map() - Feed "vlan/pcp to dscp" map into the IPA uC
* @map: The mapping data destined for the uC
*
* Returns: 0 on success, negative on failure
*/
int ipa3_add_dscp_vlan_pcp_map(
struct IpaDscpVlanPcpMap_t *map )
{
struct ipa_mem_buffer mem;
struct IpaDscpVlanPcpMap_t *cmd;
int res;
if (!map) {
IPAERR("null argument (ie. map) passed\n");
return -EINVAL;
}
IPADBG("map add attempt. num_vlan: %u\n", map->num_vlan);
mem.size = sizeof(struct IpaDscpVlanPcpMap_t);
mem.base = dma_alloc_coherent(
ipa3_ctx->uc_pdev, mem.size,
&mem.phys_base, GFP_KERNEL);
if (!mem.base) {
IPAERR("Fail to alloc DMA buff of size %d\n", mem.size);
return -ENOMEM;
}
cmd = (struct IpaDscpVlanPcpMap_t *) mem.base;
memcpy(cmd, map, sizeof(struct IpaDscpVlanPcpMap_t));
IPA_ACTIVE_CLIENTS_INC_SIMPLE();
res = ipa3_uc_send_cmd(
(u32) mem.phys_base,
IPA_CPU_2_HW_CMD_ADD_EOGRE_MAPPING,
0, true, 10 * HZ);
if (res) {
IPAERR("ipa3_uc_send_cmd failed %d\n", res);
goto free_coherent;
}
IPADBG("map add success\n");
res = 0;
free_coherent:
dma_free_coherent(ipa3_ctx->uc_pdev, mem.size, mem.base, mem.phys_base);
IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
return res;
}

166
drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
View File

@@ -8478,6 +8478,16 @@ int ipa3_cfg_ep_metadata(u32 clnt_hdl, const struct ipa_ep_cfg_metadata *ep_md)
/* copy over EP cfg */
ipa3_ctx->ep[clnt_hdl].cfg.meta = *ep_md;
if (ipa3_ctx->eogre_enabled &&
ipa3_ctx->ep[clnt_hdl].client == IPA_CLIENT_ETHERNET_PROD) {
/* reconfigure ep metadata reg to override mux-id */
ipa3_ctx->ep[clnt_hdl].cfg.hdr.hdr_ofst_metadata_valid = 0;
ipa3_ctx->ep[clnt_hdl].cfg.hdr.hdr_ofst_metadata = 0;
ipa3_ctx->ep[clnt_hdl].cfg.hdr.hdr_metadata_reg_valid = 1;
ipahal_write_reg_n_fields(IPA_ENDP_INIT_HDR_n, clnt_hdl,
&ipa3_ctx->ep[clnt_hdl].cfg.hdr);
}
IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl));
ep_md_reg_wrt = *ep_md;
@@ -12155,3 +12165,159 @@ bool ipa3_is_ulso_supported(void)
return ipa3_ctx->ulso_supported;
}
EXPORT_SYMBOL(ipa3_is_ulso_supported);
static void ipa3_eogre_info_free_cb(
void *buff,
u32 len,
u32 type)
{
if (buff) {
kfree(buff);
}
}
/**
* ipa3_check_eogre() - Check if the eogre is worthy of sending to
* recipients who would use the data.
*
* Returns: 0 on success, negative on failure
*/
int ipa3_check_eogre(
struct ipa_ioc_eogre_info *eogre_info,
bool *send2uC,
bool *send2ipacm )
{
struct ipa_ioc_eogre_info null_eogre;
bool cache_is_null, eogre_is_null, same;
int ret = 0;
if (eogre_info == NULL || send2uC == NULL || send2ipacm == NULL) {
IPAERR("NULL ptr: eogre_info(%p) and/or "
"send2uC(%p) and/or send2ipacm(%p)\n",
eogre_info, send2uC, send2ipacm);
ret = -EIO;
goto done;
}
memset(&null_eogre, 0, sizeof(null_eogre));
cache_is_null =
!memcmp(
&ipa3_ctx->eogre_cache,
&null_eogre,
sizeof(null_eogre));
eogre_is_null =
!memcmp(
eogre_info,
&null_eogre,
sizeof(null_eogre));
*send2uC = *send2ipacm = false;
if (cache_is_null) {
if (eogre_is_null) {
IPAERR(
"Attempting to disable EoGRE. EoGRE is "
"already disabled. No work needs to be done.\n");
ret = -EIO;
goto done;
}
*send2uC = *send2ipacm = true;
} else { /* (!cache_is_null) */
if (!eogre_is_null) {
IPAERR(
"EoGRE is already enabled for iptype(%d). "
"No work needs to be done.\n",
ipa3_ctx->eogre_cache.ipgre_info.iptype);
ret = -EIO;
goto done;
}
same = !memcmp(
&ipa3_ctx->eogre_cache.map_info,
&eogre_info->map_info,
sizeof(struct IpaDscpVlanPcpMap_t));
*send2uC = !same;
same = !memcmp(
&ipa3_ctx->eogre_cache.ipgre_info,
&eogre_info->ipgre_info,
sizeof(struct ipa_ipgre_info));
*send2ipacm = !same;
}
ipa3_ctx->eogre_cache = *eogre_info;
IPADBG("send2uC(%u) send2ipacm(%u)\n",
*send2uC, *send2ipacm);
done:
return ret;
}
/**
* ipa3_send_eogre_info() - Notify ipacm of incoming eogre event
*
* Returns: 0 on success, negative on failure
*
* Note: Should not be called from atomic context
*/
int ipa3_send_eogre_info(
enum ipa_eogre_event etype,
struct ipa_ioc_eogre_info *info )
{
struct ipa_msg_meta msg_meta;
struct ipa_ipgre_info *eogre_info;
int res = 0;
if (!info) {
IPAERR("Bad arg: info is NULL\n");
res = -EIO;
goto done;
}
/*
* Prep and send msg to ipacm
*/
memset(&msg_meta, 0, sizeof(struct ipa_msg_meta));
eogre_info = kzalloc(
sizeof(struct ipa_ipgre_info), GFP_KERNEL);
if (!eogre_info) {
IPAERR("eogre_info memory allocation failed !\n");
res = -ENOMEM;
goto done;
}
memcpy(eogre_info,
&(info->ipgre_info),
sizeof(struct ipa_ipgre_info));
msg_meta.msg_type = etype;
msg_meta.msg_len = sizeof(struct ipa_ipgre_info);
/*
* Post event to ipacm
*/
res = ipa3_send_msg(&msg_meta, eogre_info, ipa3_eogre_info_free_cb);
if (res) {
IPAERR_RL("ipa3_send_msg failed: %d\n", res);
kfree(eogre_info);
goto done;
}
done:
return res;
}

63
drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c
View File

@@ -1691,6 +1691,7 @@ static void ipahal_cp_hdr_to_hw_buff_v3(void *const base, u32 offset,
* @hdr_base_addr: base address in table
* @offset_entry: offset from hdr_base_addr in table
* @l2tp_params: l2tp parameters
* @eogre_params: eogre parameters
* @generic_params: generic proc_ctx params
* @is_64: Indicates whether header base address/dma base address is 64 bit.
*/
@@ -1700,6 +1701,7 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type,
dma_addr_t phys_base, u64 hdr_base_addr,
struct ipa_hdr_offset_entry *offset_entry,
struct ipa_l2tp_hdr_proc_ctx_params *l2tp_params,
struct ipa_eogre_hdr_proc_ctx_params *eogre_params,
struct ipa_eth_II_to_eth_II_ex_procparams *generic_params,
bool is_64)
{
@@ -1877,6 +1879,55 @@ static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type,
ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END;
ctx->end.length = 0;
ctx->end.value = 0;
} else if (type == IPA_HDR_PROC_EoGRE_HEADER_ADD) {
struct ipa_hw_hdr_proc_ctx_add_eogre_hdr_cmd_seq *ctx =
(struct ipa_hw_hdr_proc_ctx_add_eogre_hdr_cmd_seq *)
(base + offset);
ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD;
ctx->hdr_add.tlv.length = 2;
ctx->hdr_add.tlv.value = hdr_len;
hdr_addr = is_hdr_proc_ctx ? phys_base :
hdr_base_addr + offset_entry->offset;
IPAHAL_DBG("header address 0x%llx\n",
hdr_addr);
IPAHAL_CP_PROC_CTX_HEADER_UPDATE(ctx->hdr_add.hdr_addr,
ctx->hdr_add.hdr_addr_hi, hdr_addr);
if (!is_64)
ctx->hdr_add.hdr_addr_hi = 0;
ctx->eogre_params.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD;
ctx->eogre_params.tlv.length = 1;
ctx->eogre_params.tlv.value = IPA_HDR_UCP_EoGRE_HEADER_ADD;
ctx->eogre_params.eogre_params.eth_hdr_retained =
eogre_params->hdr_add_param.eth_hdr_retained;
ctx->eogre_params.eogre_params.input_ip_version =
eogre_params->hdr_add_param.input_ip_version;
ctx->eogre_params.eogre_params.output_ip_version =
eogre_params->hdr_add_param.output_ip_version;
ctx->eogre_params.eogre_params.second_pass =
eogre_params->hdr_add_param.second_pass;
IPAHAL_DBG("command id %d\n", ctx->eogre_params.tlv.value);
IPAHAL_DBG("eth_hdr_retained %d input_ip_version %d output_ip_version %d second_pass %d\n",
eogre_params->hdr_add_param.eth_hdr_retained,
eogre_params->hdr_add_param.input_ip_version,
eogre_params->hdr_add_param.output_ip_version,
eogre_params->hdr_add_param.second_pass);
ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END;
ctx->end.length = 0;
ctx->end.value = 0;
} else if (type == IPA_HDR_PROC_EoGRE_HEADER_REMOVE) {
struct ipa_hw_hdr_proc_ctx_remove_eogre_hdr_cmd_seq *ctx =
(struct ipa_hw_hdr_proc_ctx_remove_eogre_hdr_cmd_seq *)
(base + offset);
ctx->eogre_params.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD;
ctx->eogre_params.tlv.length = 1;
ctx->eogre_params.tlv.value = IPA_HDR_UCP_EoGRE_HEADER_REMOVE;
ctx->eogre_params.eogre_params.hdr_len_remove =
eogre_params->hdr_remove_param.hdr_len_remove;
ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END;
ctx->end.length = 0;
ctx->end.value = 0;
} else {
struct ipa_hw_hdr_proc_ctx_add_hdr_cmd_seq *ctx;
@@ -1963,6 +2014,13 @@ static int ipahal_get_proc_ctx_needed_len_v3(enum ipa_hdr_proc_type type)
case IPA_HDR_PROC_ETHII_TO_ETHII_EX:
ret = sizeof(struct ipa_hw_hdr_proc_ctx_add_hdr_cmd_seq_ex);
break;
case IPA_HDR_PROC_EoGRE_HEADER_ADD:
ret = sizeof(struct ipa_hw_hdr_proc_ctx_add_eogre_hdr_cmd_seq);
break;
case IPA_HDR_PROC_EoGRE_HEADER_REMOVE:
ret =
sizeof(struct ipa_hw_hdr_proc_ctx_remove_eogre_hdr_cmd_seq);
break;
default:
/* invalid value to make sure failure */
IPAHAL_ERR_RL("invalid ipa_hdr_proc_type %d\n", type);
@@ -1987,6 +2045,7 @@ struct ipahal_hdr_funcs {
u64 hdr_base_addr,
struct ipa_hdr_offset_entry *offset_entry,
struct ipa_l2tp_hdr_proc_ctx_params *l2tp_params,
struct ipa_eogre_hdr_proc_ctx_params *eogre_params,
struct ipa_eth_II_to_eth_II_ex_procparams
*generic_params,
bool is_64);
@@ -2055,6 +2114,7 @@ void ipahal_cp_hdr_to_hw_buff(void *base, u32 offset, u8 *const hdr,
* @hdr_base_addr: base address in table
* @offset_entry: offset from hdr_base_addr in table
* @l2tp_params: l2tp parameters
* @eogre_params: eogre parameters
* @generic_params: generic proc_ctx params
* @is_64: Indicates whether header base address/dma base address is 64 bit.
*/
@@ -2063,6 +2123,7 @@ int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type,
bool is_hdr_proc_ctx, dma_addr_t phys_base,
u64 hdr_base_addr, struct ipa_hdr_offset_entry *offset_entry,
struct ipa_l2tp_hdr_proc_ctx_params *l2tp_params,
struct ipa_eogre_hdr_proc_ctx_params *eogre_params,
struct ipa_eth_II_to_eth_II_ex_procparams *generic_params,
bool is_64)
{
@@ -2086,7 +2147,7 @@ int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type,
return hdr_funcs.ipahal_cp_proc_ctx_to_hw_buff(type, base, offset,
hdr_len, is_hdr_proc_ctx, phys_base,
hdr_base_addr, offset_entry, l2tp_params,
generic_params, is_64);
eogre_params, generic_params, is_64);
}
/*

2
drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.h
View File

@@ -741,6 +741,7 @@ void ipahal_cp_hdr_to_hw_buff(void *base, u32 offset, u8 *hdr, u32 hdr_len);
* @hdr_base_addr: base address in table
* @offset_entry: offset from hdr_base_addr in table
* @l2tp_params: l2tp parameters
* @eogre_params: eogre parameters
* @generic_params: generic proc_ctx params
* @is_64: Indicates whether header base address/dma base address is 64 bit.
*/
@@ -750,6 +751,7 @@ int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type,
u64 hdr_base_addr,
struct ipa_hdr_offset_entry *offset_entry,
struct ipa_l2tp_hdr_proc_ctx_params *l2tp_params,
struct ipa_eogre_hdr_proc_ctx_params *eogre_params,
struct ipa_eth_II_to_eth_II_ex_procparams *generic_params,
bool is_64);

50
drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_i.h
View File

@@ -889,6 +889,8 @@ union ipa_pkt_status_hw_v5_0 {
#define IPA_HDR_UCP_L2TP_UDP_HEADER_REMOVE 13
#define IPA_HDR_UCP_ETHII_TO_ETHII_EX 14
#define IPA_HDR_UCP_SET_DSCP 16
#define IPA_HDR_UCP_EoGRE_HEADER_ADD 17
#define IPA_HDR_UCP_EoGRE_HEADER_REMOVE 18
/* Processing context TLV type */
#define IPA_PROC_CTX_TLV_TYPE_END 0
@@ -1037,4 +1039,52 @@ struct ipa_hw_hdr_proc_ctx_remove_l2tp_udp_hdr_cmd_seq {
struct ipa_hw_hdr_proc_ctx_tlv end;
};
/**
* struct ipa_hw_hdr_proc_ctx_eogre_add_hdr -
* HW structure of IPA processing context - add eogre header tlv
* @tlv: IPA processing context TLV
* @eogre_params: eogre parameters
*/
struct ipa_hw_hdr_proc_ctx_eogre_add_hdr {
struct ipa_hw_hdr_proc_ctx_tlv tlv;
struct ipa_eogre_header_add_procparams eogre_params;
};
/**
* struct ipa_hw_hdr_proc_ctx_eogre_remove_hdr -
* HW structure of IPA processing context - remove eogre header tlv
* @tlv: IPA processing context TLV
* @eogre_params: eogre parameters
*/
struct ipa_hw_hdr_proc_ctx_eogre_remove_hdr {
struct ipa_hw_hdr_proc_ctx_tlv tlv;
struct ipa_eogre_header_remove_procparams eogre_params;
};
/**
* struct ipa_hw_hdr_proc_ctx_add_eogre_hdr_cmd_seq -
* IPA processing context header - process command sequence
* @hdr_add: add header command
* @eogre_params: eogre params for header addition
* @end: tlv end command (cmd.type must be 0)
*/
struct ipa_hw_hdr_proc_ctx_add_eogre_hdr_cmd_seq {
struct ipa_hw_hdr_proc_ctx_hdr_add hdr_add;
struct ipa_hw_hdr_proc_ctx_eogre_add_hdr eogre_params;
struct ipa_hw_hdr_proc_ctx_tlv end;
};
/**
* struct ipa_hw_hdr_proc_ctx_remove_eogre_hdr_cmd_seq -
* IPA processing context header - process command sequence
* @hdr_add: add header command
* @eogre_params: eogre params for header removal
* @end: tlv end command (cmd.type must be 0)
*/
struct ipa_hw_hdr_proc_ctx_remove_eogre_hdr_cmd_seq {
struct ipa_hw_hdr_proc_ctx_hdr_add hdr_add;
struct ipa_hw_hdr_proc_ctx_eogre_remove_hdr eogre_params;
struct ipa_hw_hdr_proc_ctx_tlv end;
};
#endif /* _IPAHAL_I_H_ */