Merge "qcacmn: Move FISA FST table to CMEM on Kiwi"

dp/wifi3.0/be/dp_be.c

@@ -144,6 +144,35 @@ void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
 }
 #endif
 
+#if defined(WLAN_SUPPORT_RX_FISA)
+static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
+{
+	dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
+		soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
+	/* get CMEM for cookie conversion */
+	if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) {
+		dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size);
+		return QDF_STATUS_E_NOMEM;
+	}
+
+	soc->fst_cmem_size = DP_CMEM_FST_SIZE;
+
+	soc->fst_cmem_base = soc->cmem_base +
+			     (soc->cmem_total_size - soc->cmem_avail_size);
+	soc->cmem_avail_size -= soc->fst_cmem_size;
+
+	dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx",
+		soc->fst_cmem_base, soc->fst_cmem_size);
+
+	return QDF_STATUS_SUCCESS;
+}
+#else /* !WLAN_SUPPORT_RX_FISA */
+static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
+{
+	return QDF_STATUS_SUCCESS;
+}
+#endif
+
 /**
  * dp_cc_reg_cfg_init() - initialize and configure HW cookie
 			  conversion register
@@ -209,19 +238,42 @@ static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
 {
 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
 
-	dp_info("cmem base 0x%llx, size 0x%llx",
-		soc->cmem_base, soc->cmem_size);
+	dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
+		soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
 	/* get CMEM for cookie conversion */
-	if (soc->cmem_size < DP_CC_PPT_MEM_SIZE) {
-		dp_err("cmem_size %llu bytes < 4K", soc->cmem_size);
+	if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) {
+		dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size);
 		return QDF_STATUS_E_RESOURCES;
 	}
 	be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
 					  DP_CC_MEM_OFFSET_IN_CMEM);
 
+	soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE;
+
+	dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx",
+		be_soc->cc_cmem_base, soc->cmem_avail_size);
 	return QDF_STATUS_SUCCESS;
 }
 
+static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
+					 uint8_t for_feature)
+{
+	QDF_STATUS status = QDF_STATUS_E_NOMEM;
+
+	switch (for_feature) {
+	case COOKIE_CONVERSION:
+		status = dp_hw_cc_cmem_addr_init(soc);
+		break;
+	case FISA_FST:
+		status = dp_fisa_fst_cmem_addr_init(soc);
+		break;
+	default:
+		dp_err("Invalid CMEM request");
+	}
+
+	return status;
+}
+
 #else
 
 static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
@@ -236,6 +288,13 @@ static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
 {
 	return QDF_STATUS_SUCCESS;
 }
+
+static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
+					 uint8_t for_feature)
+{
+	return QDF_STATUS_SUCCESS;
+}
+
 #endif
 
 QDF_STATUS
@@ -510,7 +569,7 @@ static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
 
 	soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
 
-	qdf_status = dp_hw_cc_cmem_addr_init(soc);
+	qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
 	if (!QDF_IS_STATUS_SUCCESS(qdf_status))
 		goto fail;
 
@@ -527,6 +586,10 @@ static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
 			goto fail;
 	}
 
+	qdf_status = dp_get_cmem_allocation(soc, FISA_FST);
+	if (!QDF_IS_STATUS_SUCCESS(qdf_status))
+		goto fail;
+
 	for (i = 0; i < MAX_RXDESC_POOLS; i++) {
 		num_entries =
 			wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);

dp/wifi3.0/be/dp_be.h

@@ -28,6 +28,11 @@
 #endif
 #include <dp_mon.h>
 
+enum CMEM_MEM_CLIENTS {
+	COOKIE_CONVERSION,
+	FISA_FST,
+};
+
 /* maximum number of entries in one page of secondary page table */
 #define DP_CC_SPT_PAGE_MAX_ENTRIES 512
 
@@ -47,6 +52,9 @@
 #define DP_FST_MEM_OFFSET_IN_CMEM \
 	(DP_CC_MEM_OFFSET_IN_CMEM + DP_CC_PPT_MEM_SIZE)
 
+/* CMEM size for FISA FST 16K */
+#define DP_CMEM_FST_SIZE 16384
+
 /* lower 9 bits in Desc ID for offset in page of SPT */
 #define DP_CC_DESC_ID_SPT_VA_OS_SHIFT 0
 

dp/wifi3.0/dp_main.c

@@ -6118,13 +6118,29 @@ dp_rx_target_fst_config(struct dp_soc *soc)
  */
 static inline QDF_STATUS dp_rx_target_fst_config(struct dp_soc *soc)
 {
+	QDF_STATUS status;
+	struct dp_rx_fst *fst = soc->rx_fst;
+
 	/* Check if it is enabled in the INI */
 	if (!soc->fisa_enable) {
 		dp_err("RX FISA feature is disabled");
 		return QDF_STATUS_E_NOSUPPORT;
 	}
 
-	return dp_rx_flow_send_fst_fw_setup(soc, soc->pdev_list[0]);
+	status = dp_rx_flow_send_fst_fw_setup(soc, soc->pdev_list[0]);
+	if (QDF_IS_STATUS_ERROR(status)) {
+		dp_err("dp_rx_flow_send_fst_fw_setup failed %d",
+		       status);
+		return status;
+	}
+
+	if (soc->fst_cmem_base) {
+		soc->fst_in_cmem = true;
+		dp_rx_fst_update_cmem_params(soc, fst->max_entries,
+					     soc->fst_cmem_base & 0xffffffff,
+					     soc->fst_cmem_base >> 32);
+	}
+	return status;
 }
 
 #define FISA_MAX_TIMEOUT 0xffffffff
@@ -6138,6 +6154,7 @@ static QDF_STATUS dp_rx_fisa_config(struct dp_soc *soc)
 
 	return dp_htt_rx_fisa_config(soc->pdev_list[0], &fisa_config);
 }
+
 #else /* !WLAN_SUPPORT_RX_FISA */
 static inline QDF_STATUS dp_rx_target_fst_config(struct dp_soc *soc)
 {
@@ -13710,7 +13727,8 @@ dp_soc_attach(struct cdp_ctrl_objmgr_psoc *ctrl_psoc,
 
 	hif_get_cmem_info(soc->hif_handle,
 			  &soc->cmem_base,
-			  &soc->cmem_size);
+			  &soc->cmem_total_size);
+	soc->cmem_avail_size = soc->cmem_total_size;
 	int_ctx = 0;
 	soc->device_id = device_id;
 	soc->cdp_soc.ops =

dp/wifi3.0/dp_types.h

@@ -2263,6 +2263,13 @@ struct dp_soc {
 		qdf_atomic_t skip_fisa;
 		uint8_t fisa_force_flush[MAX_REO_DEST_RINGS];
 	} skip_fisa_param;
+
+	/**
+	 * CMEM address and size for FST in CMEM, This is the address
+	 * shared during init time.
+	 */
+	uint64_t fst_cmem_base;
+	uint64_t fst_cmem_size;
 #endif
 #endif /* WLAN_SUPPORT_RX_FLOW_TAG || WLAN_SUPPORT_RX_FISA */
 	/* SG supported for msdu continued packets from wbm release ring */
@@ -2345,7 +2352,9 @@ struct dp_soc {
 	/* CMEM buffer target reserved for host usage */
 	uint64_t cmem_base;
 	/* CMEM size in bytes */
-	uint64_t cmem_size;
+	uint64_t cmem_total_size;
+	/* CMEM free size in bytes */
+	uint64_t cmem_avail_size;
 
 	/* SOC level feature flags */
 	struct dp_soc_features features;

hal/wifi3.0/hal_rx_flow.c

@@ -399,7 +399,8 @@ struct hal_rx_fst *
 hal_rx_fst_attach(hal_soc_handle_t hal_soc_hdl,
 		  qdf_device_t qdf_dev,
 		  uint64_t *hal_fst_base_paddr, uint16_t max_entries,
-		  uint16_t max_search, uint8_t *hash_key)
+		  uint16_t max_search, uint8_t *hash_key,
+		  uint64_t fst_cmem_base)
 {
 	struct hal_rx_fst *fst = qdf_mem_malloc(sizeof(struct hal_rx_fst));
 	uint32_t fst_entry_size;
@@ -423,29 +424,39 @@ hal_rx_fst_attach(hal_soc_handle_t hal_soc_hdl,
 		  "HAL FST allocation %pK %d * %d\n", fst,
 		  fst->max_entries, fst_entry_size);
 
+	if (fst_cmem_base == 0) {
+		/* FST is in DDR */
+		fst->base_vaddr = (uint8_t *)qdf_mem_alloc_consistent(qdf_dev,
+				    qdf_dev->dev,
+				    (fst->max_entries * fst_entry_size),
+				    &fst->base_paddr);
+
+		if (!fst->base_vaddr) {
+			QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
+				  FL("hal fst->base_vaddr allocation failed"));
+			qdf_mem_free(fst);
+			return NULL;
+		}
 
-	fst->base_vaddr = (uint8_t *)qdf_mem_alloc_consistent(qdf_dev,
-				qdf_dev->dev,
-				(fst->max_entries * fst_entry_size),
-				&fst->base_paddr);
+		*hal_fst_base_paddr = (uint64_t)fst->base_paddr;
+	} else {
+		*hal_fst_base_paddr = fst_cmem_base;
+		goto out;
+	}
 
 	QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO,
 		  "hal_rx_fst base address 0x%pK", (void *)fst->base_paddr);
-	if (!fst->base_vaddr) {
-		QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
-			  FL("hal fst->base_vaddr allocation failed"));
-		qdf_mem_free(fst);
-		return NULL;
-	}
+
 	QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_ANY, QDF_TRACE_LEVEL_DEBUG,
 			   (void *)fst->key, HAL_FST_HASH_KEY_SIZE_BYTES);
 
 	qdf_mem_set((uint8_t *)fst->base_vaddr,
 		    (fst->max_entries * fst_entry_size), 0);
 
+out:
 	hal_rx_fst_key_configure(fst);
 	hal_flow_toeplitz_create_cache(fst);
-	*hal_fst_base_paddr = (uint64_t)fst->base_paddr;
+
 	return fst;
 }
 qdf_export_symbol(hal_rx_fst_attach);
@@ -459,20 +470,21 @@ qdf_export_symbol(hal_rx_fst_attach);
  *
  * Return:
  */
-void hal_rx_fst_detach(hal_soc_handle_t hal_soc_hdl,
-		       struct hal_rx_fst *rx_fst,
-		       qdf_device_t qdf_dev)
+void hal_rx_fst_detach(hal_soc_handle_t hal_soc_hdl, struct hal_rx_fst *rx_fst,
+		       qdf_device_t qdf_dev, uint64_t fst_cmem_base)
 {
 	uint32_t fst_entry_size;
 
 	if (!rx_fst || !qdf_dev)
 		return;
 
-	fst_entry_size = hal_rx_fst_get_fse_size(hal_soc_hdl);
-
-	qdf_mem_free_consistent(qdf_dev, qdf_dev->dev,
-				rx_fst->max_entries * fst_entry_size,
-				rx_fst->base_vaddr, rx_fst->base_paddr, 0);
+	if (fst_cmem_base == 0 && rx_fst->base_vaddr) {
+		fst_entry_size = hal_rx_fst_get_fse_size(hal_soc_hdl);
+		qdf_mem_free_consistent(qdf_dev, qdf_dev->dev,
+					rx_fst->max_entries * fst_entry_size,
+					rx_fst->base_vaddr, rx_fst->base_paddr,
+					0);
+	}
 
 	qdf_mem_free(rx_fst);
 }

hal/wifi3.0/hal_rx_flow.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -145,7 +145,8 @@ struct hal_rx_fst *
 hal_rx_fst_attach(hal_soc_handle_t hal_soc_hdl,
 		  qdf_device_t qdf_dev,
 		  uint64_t *hal_fst_base_paddr, uint16_t max_entries,
-		  uint16_t max_search, uint8_t *hash_key);
+		  uint16_t max_search, uint8_t *hash_key,
+		  uint64_t fst_cmem_base);
 
 /**
  * hal_rx_fst_detach() - De-init the Rx flow search table from HW
@@ -156,8 +157,8 @@ hal_rx_fst_attach(hal_soc_handle_t hal_soc_hdl,
  *
  * Return:
  */
-void hal_rx_fst_detach(hal_soc_handle_t hal_soc_hdl,
-		       struct hal_rx_fst *rx_fst, qdf_device_t qdf_dev);
+void hal_rx_fst_detach(hal_soc_handle_t hal_soc_hdl, struct hal_rx_fst *rx_fst,
+		       qdf_device_t qdf_dev, uint64_t fst_cmem_base);
 
 /**
  * hal_rx_insert_flow_entry() - Add a flow into the FST table

hal/wifi3.0/kiwi/hal_kiwi.c

@@ -1476,6 +1476,139 @@ hal_rx_flow_setup_fse_kiwi(uint8_t *rx_fst, uint32_t table_offset,
 	return fse;
 }
 
+/*
+ * hal_rx_flow_setup_cmem_fse_kiwi() - Setup a flow search entry in HW CMEM FST
+ * @hal_soc: hal_soc reference
+ * @cmem_ba: CMEM base address
+ * @table_offset: offset into the table where the flow is to be setup
+ * @flow: Flow Parameters
+ *
+ * Return: Success/Failure
+ */
+static uint32_t
+hal_rx_flow_setup_cmem_fse_kiwi(struct hal_soc *hal_soc, uint32_t cmem_ba,
+				uint32_t table_offset, uint8_t *rx_flow)
+{
+	struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
+	uint32_t fse_offset;
+	uint32_t value;
+
+	fse_offset = cmem_ba + (table_offset * HAL_RX_FST_ENTRY_SIZE);
+
+	/* Reset the Valid bit */
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							VALID), 0);
+
+	value  = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96,
+				(flow->tuple_info.src_ip_127_96));
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							SRC_IP_127_96), value);
+
+	value  = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64,
+				(flow->tuple_info.src_ip_95_64));
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							SRC_IP_95_64), value);
+
+	value  = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32,
+				(flow->tuple_info.src_ip_63_32));
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							SRC_IP_63_32), value);
+
+	value  = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0,
+				(flow->tuple_info.src_ip_31_0));
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							SRC_IP_31_0), value);
+
+	value  = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96,
+				(flow->tuple_info.dest_ip_127_96));
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							DEST_IP_127_96), value);
+
+	value  = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64,
+				(flow->tuple_info.dest_ip_95_64));
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							DEST_IP_95_64), value);
+
+	value  = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32,
+				(flow->tuple_info.dest_ip_63_32));
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							DEST_IP_63_32), value);
+
+	value  = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0,
+				(flow->tuple_info.dest_ip_31_0));
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							DEST_IP_31_0), value);
+
+	value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT,
+				(flow->tuple_info.dest_port));
+	value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT,
+				(flow->tuple_info.src_port));
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							SRC_PORT), value);
+
+	value  = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA,
+				(flow->fse_metadata));
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							METADATA), value);
+
+	/* Reset all the other fields in FSE */
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							MSDU_COUNT), 0);
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							MSDU_BYTE_COUNT), 0);
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							TIMESTAMP), 0);
+
+	value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL,
+				   flow->tuple_info.l4_protocol);
+	value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER,
+				flow->reo_destination_handler);
+	value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY,
+				REO_DESTINATION_INDICATION,
+				flow->reo_destination_indication);
+	value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1);
+	HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
+							L4_PROTOCOL), value);
+
+	return fse_offset;
+}
+
+/**
+ * hal_rx_flow_get_cmem_fse_ts_kiwi() - Get timestamp field from CMEM FSE
+ * @hal_soc: hal_soc reference
+ * @fse_offset: CMEM FSE offset
+ *
+ * Return: Timestamp
+ */
+static uint32_t hal_rx_flow_get_cmem_fse_ts_kiwi(struct hal_soc *hal_soc,
+						 uint32_t fse_offset)
+{
+	return HAL_CMEM_READ(hal_soc, fse_offset +
+			     HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, TIMESTAMP));
+}
+
+/**
+ * hal_rx_flow_get_cmem_fse_kiwi() - Get FSE from CMEM
+ * @hal_soc: hal_soc reference
+ * @fse_offset: CMEM FSE offset
+ * @fse: referece where FSE will be copied
+ * @len: length of FSE
+ *
+ * Return: If read is succesfull or not
+ */
+static void
+hal_rx_flow_get_cmem_fse_kiwi(struct hal_soc *hal_soc, uint32_t fse_offset,
+			      uint32_t *fse, qdf_size_t len)
+{
+	int i;
+
+	if (len != HAL_RX_FST_ENTRY_SIZE)
+		return;
+
+	for (i = 0; i < NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY; i++)
+		fse[i] = HAL_CMEM_READ(hal_soc, fse_offset + i * 4);
+}
+
 static
 void hal_compute_reo_remap_ix2_ix3_kiwi(uint32_t *ring_map,
 					uint32_t num_rings, uint32_t *remap1,
@@ -1863,9 +1996,11 @@ static void hal_hw_txrx_ops_attach_kiwi(struct hal_soc *hal_soc)
 	hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be;
 	hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
 					hal_compute_reo_remap_ix2_ix3_kiwi;
-	hal_soc->ops->hal_rx_flow_setup_cmem_fse = NULL;
-	hal_soc->ops->hal_rx_flow_get_cmem_fse_ts = NULL;
-	hal_soc->ops->hal_rx_flow_get_cmem_fse = NULL;
+	hal_soc->ops->hal_rx_flow_setup_cmem_fse =
+						hal_rx_flow_setup_cmem_fse_kiwi;
+	hal_soc->ops->hal_rx_flow_get_cmem_fse_ts =
+					hal_rx_flow_get_cmem_fse_ts_kiwi;
+	hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_kiwi;
 	hal_soc->ops->hal_cmem_write = hal_cmem_write_kiwi;
 	hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
 		hal_rx_msdu_get_reo_destination_indication_be;