disp: msm: sde: parametrize RC minimum region width

Parametrize RC minimum region width restriction as it
differs starting from Kailua.

Change-Id: I41e7cd6812ed2fadb5719ee51f4db0723be632fe
Signed-off-by: Amine Najahi <[email protected]>
Signed-off-by: Renchao Liu <[email protected]>

msm/sde/sde_hw_catalog.c

@@ -431,6 +431,7 @@ enum {
 	RC_LEN,
 	RC_VERSION,
 	RC_MEM_TOTAL_SIZE,
+	RC_MIN_REGION_WIDTH,
 	RC_PROP_MAX,
 };
 
@@ -818,6 +819,7 @@ static struct sde_prop_type rc_prop[] = {
 	{RC_LEN, "qcom,sde-dspp-rc-size", false, PROP_TYPE_U32},
 	{RC_VERSION, "qcom,sde-dspp-rc-version", false, PROP_TYPE_U32},
 	{RC_MEM_TOTAL_SIZE, "qcom,sde-dspp-rc-mem-size", false, PROP_TYPE_U32},
+	{RC_MIN_REGION_WIDTH, "qcom,sde-dspp-rc-min-region-width", false, PROP_TYPE_U32},
 };
 
 static struct sde_prop_type spr_prop[] = {
@@ -2779,6 +2781,13 @@ static int _sde_rc_parse_dt(struct device_node *np,
 					RC_VERSION, 0);
 			sblk->rc.mem_total_size = PROP_VALUE_ACCESS(
 					props->values, RC_MEM_TOTAL_SIZE, 0);
+
+			if (!props->exists[RC_MIN_REGION_WIDTH])
+				sblk->rc.min_region_width = 4;
+			else
+				sblk->rc.min_region_width = PROP_VALUE_ACCESS(
+						props->values, RC_MIN_REGION_WIDTH, 0);
+
 			sblk->rc.idx = i;
 			set_bit(SDE_DSPP_RC, &dspp->features);
 		}

msm/sde/sde_hw_catalog.h

@@ -993,12 +993,14 @@ struct sde_lm_sub_blks {
  * @version: HW Algorithm version.
  * @idx: HW block instance id.
  * @mem_total_size: data memory size.
+ * @min_region_width: minimum region width in pixels.
  */
 struct sde_dspp_rc {
 	SDE_HW_SUBBLK_INFO;
 	u32 version;
 	u32 idx;
 	u32 mem_total_size;
+	u32 min_region_width;
 };
 
 struct sde_dspp_sub_blks {

msm/sde/sde_hw_rc.c

@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -577,6 +578,7 @@ static int sde_hw_rc_check_mask_cfg(
 	int rc = 0;
 	u32 i = 0;
 	u32 half_panel_width;
+	u32 mem_total_size, min_region_width;
 	u64 flags;
 	u32 cfg_param_01, cfg_param_02, cfg_param_03;
 	u32 cfg_param_07, cfg_param_08;
@@ -607,7 +609,10 @@ static int sde_hw_rc_check_mask_cfg(
 	r1_enable = ((flags & SDE_HW_RC_DISABLE_R1) != SDE_HW_RC_DISABLE_R1);
 	r2_enable = ((flags & SDE_HW_RC_DISABLE_R2) != SDE_HW_RC_DISABLE_R2);
 
-	if (cfg_param_07 > hw_dspp->cap->sblk->rc.mem_total_size) {
+	mem_total_size = hw_dspp->cap->sblk->rc.mem_total_size;
+	min_region_width = hw_dspp->cap->sblk->rc.min_region_width;
+
+	if (cfg_param_07 > mem_total_size) {
 		SDE_ERROR("invalid cfg_param_07:%d\n", cfg_param_07);
 		return -EINVAL;
 	}
@@ -617,11 +622,9 @@ static int sde_hw_rc_check_mask_cfg(
 		return -EINVAL;
 	}
 
-	if ((cfg_param_07 + cfg_param_08) >
-			hw_dspp->cap->sblk->rc.mem_total_size) {
+	if ((cfg_param_07 + cfg_param_08) > mem_total_size) {
 		SDE_ERROR("invalid cfg_param_08:%d, cfg_param_07:%d, max:%u\n",
-				cfg_param_08, cfg_param_07,
-				hw_dspp->cap->sblk->rc.mem_total_size);
+				cfg_param_08, cfg_param_07, mem_total_size);
 		return -EINVAL;
 	}
 
@@ -631,7 +634,7 @@ static int sde_hw_rc_check_mask_cfg(
 	}
 
 	for (i = 0; i < cfg_param_03; i++) {
-		if (cfg_param_04[i] < 4) {
+		if (cfg_param_04[i] < min_region_width) {
 			SDE_ERROR("invalid cfg_param_04[%d]:%d\n", i,
 					cfg_param_04[i]);
 			return -EINVAL;