qcacmn: add RRI on DDR support for WCN6450

Add required changes for RRI on DDR support for wcn6450 as
it support SRRI/DRRI updates over DDR.

Change-Id: I734e177660069e1e21996f1c4489567b3527cabc
CRs-Fixed: 3383301

hif/src/ce/ce_main.c

@@ -3912,8 +3912,8 @@ static inline QDF_STATUS hif_alloc_rri_on_ddr(struct hif_softc *scn)
 	qdf_dma_addr_t paddr_rri_on_ddr = 0;
 
 	scn->vaddr_rri_on_ddr =
-		(uint32_t *)qdf_mem_alloc_consistent(scn->qdf_dev,
-		scn->qdf_dev->dev, (CE_COUNT * sizeof(uint32_t)),
+		(void *)qdf_mem_alloc_consistent(scn->qdf_dev,
+		scn->qdf_dev->dev, RRI_ON_DDR_MEM_SIZE,
 		&paddr_rri_on_ddr);
 
 	if (!scn->vaddr_rri_on_ddr) {
@@ -3923,7 +3923,7 @@ static inline QDF_STATUS hif_alloc_rri_on_ddr(struct hif_softc *scn)
 
 	scn->paddr_rri_on_ddr = paddr_rri_on_ddr;
 
-	qdf_mem_zero(scn->vaddr_rri_on_ddr, CE_COUNT * sizeof(uint32_t));
+	qdf_mem_zero(scn->vaddr_rri_on_ddr, RRI_ON_DDR_MEM_SIZE);
 
 	return QDF_STATUS_SUCCESS;
 }
@@ -3949,8 +3949,8 @@ static inline void hif_config_rri_on_ddr(struct hif_softc *scn)
 	if (hif_alloc_rri_on_ddr(scn) != QDF_STATUS_SUCCESS)
 		return;
 
-	low_paddr  = BITS0_TO_31(scn->paddr_rri_on_ddr);
-	high_paddr = BITS32_TO_35(scn->paddr_rri_on_ddr);
+	low_paddr  = RRI_ON_DDR_PADDR_LOW(scn->paddr_rri_on_ddr);
+	high_paddr = RRI_ON_DDR_PADDR_HIGH(scn->paddr_rri_on_ddr);
 
 	hif_debug("using srri and drri from DDR");
 

hif/src/ce/ce_reg.h

@@ -284,11 +284,24 @@ uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct hif_softc *scn,
 #define BITS32_TO_35(val) ((uint32_t)(((uint64_t)(val)\
 				     & (uint64_t)(0xF00000000))>>32))
 
-#define VADDR_FOR_CE(scn, CE_ctrl_addr)\
-	((scn->vaddr_rri_on_ddr) + COPY_ENGINE_ID(CE_ctrl_addr))
+#ifdef WLAN_40BIT_ADDRESSING_SUPPORT
+#define RRI_ON_DDR_PADDR_HIGH(val) (uint32_t)(((uint64_t)(val) >> 32) & 0xFF)
+#else
+#define RRI_ON_DDR_PADDR_HIGH(val) BITS32_TO_35(val)
+#endif
+#define RRI_ON_DDR_PADDR_LOW(val) BITS0_TO_31(val)
 
+#ifdef WLAN_64BIT_DATA_SUPPORT
+#define VADDR_FOR_CE(scn, CE_ctrl_addr)\
+	(((uint64_t *)((scn)->vaddr_rri_on_ddr)) + COPY_ENGINE_ID(CE_ctrl_addr))
+#define SRRI_FROM_DDR_ADDR(addr) ((*(addr)) & 0xFFFF)
+#define DRRI_FROM_DDR_ADDR(addr) (((*(addr)) >> 32) & 0xFFFF)
+#else
+#define VADDR_FOR_CE(scn, CE_ctrl_addr)\
+	(((uint32_t *)((scn)->vaddr_rri_on_ddr)) + COPY_ENGINE_ID(CE_ctrl_addr))
 #define SRRI_FROM_DDR_ADDR(addr) ((*(addr)) & 0xFFFF)
 #define DRRI_FROM_DDR_ADDR(addr) (((*(addr))>>16) & 0xFFFF)
+#endif
 
 #define CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \
 	A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)

hif/src/hif_main.c

@@ -1169,7 +1169,7 @@ void hif_uninit_rri_on_ddr(struct hif_softc *scn)
 {
 	if (scn->vaddr_rri_on_ddr)
 		qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev,
-					(CE_COUNT * sizeof(uint32_t)),
+					RRI_ON_DDR_MEM_SIZE,
 					scn->vaddr_rri_on_ddr,
 					scn->paddr_rri_on_ddr, 0);
 	scn->vaddr_rri_on_ddr = NULL;

hif/src/hif_main.h

@@ -159,6 +159,12 @@
 
 #define CE_INTERRUPT_IDX(x) x
 
+#ifdef WLAN_64BIT_DATA_SUPPORT
+#define RRI_ON_DDR_MEM_SIZE CE_COUNT * sizeof(uint64_t)
+#else
+#define RRI_ON_DDR_MEM_SIZE CE_COUNT * sizeof(uint32_t)
+#endif
+
 struct ce_int_assignment {
 	uint8_t msi_idx[NUM_CE_AVAILABLE];
 };
@@ -290,7 +296,7 @@ struct hif_softc {
 	atomic_t active_tasklet_cnt;
 	atomic_t active_grp_tasklet_cnt;
 	atomic_t link_suspended;
-	uint32_t *vaddr_rri_on_ddr;
+	void *vaddr_rri_on_ddr;
 	qdf_dma_addr_t paddr_rri_on_ddr;
 #ifdef CONFIG_BYPASS_QMI
 	uint32_t *vaddr_qmi_bypass;