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@@ -44,11 +44,6 @@
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#define ICP_MSG_BUF_SIZE 256
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#define ICP_DBG_BUF_SIZE 102400
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-#define ICP_CLK_HW_IPE 0x0
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-#define ICP_CLK_HW_BPS 0x1
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-#define ICP_CLK_HW_OFE 0x2
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-#define ICP_DEV_CLK_MAX 0x3
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-
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#define ICP_OVER_CLK_THRESHOLD 5
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#define ICP_TWO_DEV_BW_SHARE_RATIO 2
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@@ -74,17 +69,6 @@
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#define CAM_ICP_HW_MGR_NAME_SIZE 32
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-#define CAM_ICP_GET_HW_DEV_TYPE_FROM_HW_CLK_TYPE(hw_clk_type) \
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-({ \
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- (hw_clk_type) + (CAM_ICP_DEV_START_IDX); \
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-})
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-
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-#define CAM_ICP_GET_HW_CLK_TYPE_FROM_HW_DEV_TYPE(hw_dev_type) \
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-({ \
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- (hw_dev_type) - (CAM_ICP_DEV_START_IDX); \
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-})
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-
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-#define CAM_ICP_GET_DEV_INFO_IDX(hw_dev_type) ((hw_dev_type) - (CAM_ICP_DEV_START_IDX))
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#define CAM_ICP_IS_DEV_HW_EXIST(hw_cap_mask, hw_dev_type) \
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({ \
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(hw_cap_mask) & BIT((hw_dev_type)); \
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@@ -95,6 +79,8 @@
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((type) >= CAM_ICP_HW_ICP_V1) && ((type) < CAM_ICP_HW_MAX); \
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})
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+#define CAM_ICP_MAX_ICP_PROC_PER_DEV 1
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+
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struct hfi_mini_dump_info;
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/**
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@@ -305,10 +291,72 @@ struct cam_ctx_clk_info {
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bool bw_included;
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};
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+/**
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+ * struct icp_cmd_generic_blob
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+ * @ctx: Current context info
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+ * @frame_info_idx: Index used for frame process info
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+ * @io_buf_addr: pointer to io buffer address
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+ */
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+struct icp_cmd_generic_blob {
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+ struct cam_icp_hw_ctx_data *ctx;
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+ uint32_t frame_info_idx;
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+ dma_addr_t *io_buf_addr;
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+};
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+
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+/**
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+ * struct cam_icp_clk_info
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+ * @base_clk: Base clock to process request
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+ * @curr_clk: Current clock of hadrware
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+ * @prev_clk: Previous clock of hadrware
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+ * @threshold: Threshold for overclk count
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+ * @over_clked: Over clock count
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+ * @uncompressed_bw: Current bandwidth voting
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+ * @compressed_bw: Current compressed bandwidth voting
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+ * @num_paths: Number of AXI vote paths
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+ * @axi_path: Current per path bw vote info
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+ * @watch_dog: watchdog timer handle
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+ * @watch_dog_reset_counter: Counter for watch dog reset
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+ * @timeout_cb_data: private cb data to be used when device timeouts
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+ */
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+struct cam_icp_clk_info {
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+ uint32_t base_clk;
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+ uint32_t curr_clk;
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+ uint32_t prev_clk;
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+ uint32_t threshold;
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+ uint32_t over_clked;
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+ uint64_t uncompressed_bw;
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+ uint64_t compressed_bw;
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+ uint32_t num_paths;
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+ struct cam_cpas_axi_per_path_bw_vote axi_path[CAM_ICP_MAX_PER_PATH_VOTES];
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+ struct cam_req_mgr_timer *watch_dog;
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+ uint32_t watch_dog_reset_counter;
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+ void *timeout_cb_data;
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+};
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+
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+/**
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+ * struct cam_icp_hw_device_info
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+ * @dev_name: name of IPE/BPS/OFE device
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+ * @hw_dev_type: type of IPE/BPS/OFE device
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+ * @dev_intf: interface to device hardware layer
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+ * @clk_info: clock info for the device
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+ * @dev_ctx_info: context related info for the device
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+ * @hw_dev_cnt: number of devices for this particular device type
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+ * Exa - for IPE device - IPE0 and IPE1
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+ */
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+struct cam_icp_hw_device_info {
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+ char *dev_name;
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+ enum cam_icp_hw_type hw_dev_type;
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+ struct cam_hw_intf **dev_intf;
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+ struct cam_icp_clk_info clk_info;
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+ struct cam_icp_hw_ctx_dev_info dev_ctx_info;
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+ uint32_t hw_dev_cnt;
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+};
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+
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/**
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* struct cam_icp_hw_ctx_data
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* @context_priv: Context private data
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* @hw_mgr_priv: HW MGR of the context
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+ * @device_info: device info associated with this ctx
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* @ctx_mutex: Mutex for context
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* @fw_handle: Firmware handle
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* @scratch_mem_size: Scratch memory size
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@@ -325,15 +373,15 @@ struct cam_ctx_clk_info {
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* @watch_dog: watchdog timer handle
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* @watch_dog_reset_counter: Counter for watch dog reset
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* @last_flush_req: last flush req for this ctx
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+ * @ctx_id_string: string helps to identify context (primarily used for logging)
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* @perf_stats: performance statistics info
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* @evt_inject_params: Event injection data for hw_mgr_ctx
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- * @hw_dev_type: hardware device type of this context
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- * @hw_clk_type: hardware clock type for this context
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* @abort_timed_out: Indicates if abort timed out
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*/
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struct cam_icp_hw_ctx_data {
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void *context_priv;
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void *hw_mgr_priv;
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+ struct cam_icp_hw_device_info *device_info;
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struct mutex ctx_mutex;
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uint32_t fw_handle;
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uint32_t scratch_mem_size;
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@@ -353,68 +401,22 @@ struct cam_icp_hw_ctx_data {
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char ctx_id_string[128];
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struct cam_icp_ctx_perf_stats perf_stats;
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struct cam_hw_inject_evt_param evt_inject_params;
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- enum cam_icp_hw_type hw_dev_type;
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- uint32_t hw_clk_type;
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bool abort_timed_out;
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};
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-/**
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- * struct icp_cmd_generic_blob
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- * @ctx: Current context info
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- * @frame_info_idx: Index used for frame process info
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- * @io_buf_addr: pointer to io buffer address
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- */
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-struct icp_cmd_generic_blob {
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- struct cam_icp_hw_ctx_data *ctx;
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- uint32_t frame_info_idx;
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- dma_addr_t *io_buf_addr;
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-};
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-
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-/**
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- * struct cam_icp_clk_info
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- * @base_clk: Base clock to process request
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- * @curr_clk: Current clock of hadrware
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- * @prev_clk: Previous clock of hadrware
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- * @threshold: Threshold for overclk count
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- * @over_clked: Over clock count
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- * @uncompressed_bw: Current bandwidth voting
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- * @compressed_bw: Current compressed bandwidth voting
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- * @num_paths: Number of AXI vote paths
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- * @axi_path: Current per path bw vote info
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- * @hw_type: IPE/BPS device type
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- * @watch_dog: watchdog timer handle
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- * @watch_dog_reset_counter: Counter for watch dog reset
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- * @timeout_cb_data: private cb data to be used when device timeouts
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- */
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-struct cam_icp_clk_info {
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- uint32_t base_clk;
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- uint32_t curr_clk;
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- uint32_t prev_clk;
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- uint32_t threshold;
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- uint32_t over_clked;
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- uint64_t uncompressed_bw;
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- uint64_t compressed_bw;
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- uint32_t num_paths;
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- struct cam_cpas_axi_per_path_bw_vote axi_path[CAM_ICP_MAX_PER_PATH_VOTES];
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- uint32_t hw_type;
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- struct cam_req_mgr_timer *watch_dog;
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- uint32_t watch_dog_reset_counter;
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- void *timeout_cb_data;
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-};
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-
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/**
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* struct cam_icp_hw_mgr
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* @hw_mgr_mutex: Mutex for ICP hardware manager
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* @hw_mgr_lock: Spinlock for ICP hardware manager
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- * @devices: Devices of ICP hardware manager
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+ * @dev_info: array of available device info (IPE/BPS/OFE)
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+ * for the hw mgr
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+ * @num_dev_info: number of device info for available device for the hw mgr
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+ * @dev_info_idx: map hw dev type to index for device info array indexing
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* @icp_dev_intf: ICP device interface
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- * @hw_dev_cnt: count number of each hw type
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* @ctx_data: Context data
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* @mini_dump_cb: Mini dump cb
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* @hw_mgr_name: name of the hw mgr
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* @hw_mgr_id: ID of the hw mgr, equivalent to hw mgr index
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- * @icp_booted: Processor is booted i.e. firmware loaded
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- * @icp_resumed: Processor is powered on
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* @iommu_hdl: Non secure IOMMU handle
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* @iommu_sec_hdl: Secure IOMMU handle
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* @hfi_handle: hfi handle for this ICP hw mgr
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@@ -430,45 +432,44 @@ struct cam_icp_clk_info {
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* @timer_work_data: Pointer to timer work queue task
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* @ctxt_cnt: Active context count
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* @dentry: Debugfs entry
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- * @icp_pc_flag: Flag to enable/disable power collapse
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- * @dev_pc_flag: Flag to enable/disable
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- * power collapse for ipe & bps
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- * @icp_use_pil: Flag to indicate usage of PIL framework
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* @icp_debug_clk: Set clock based on debug value
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* @icp_default_clk: Set this clok if user doesn't supply
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- * @clk_info: Clock info of hardware
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* @secure_mode: Flag to enable/disable secure camera
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- * @icp_jtag_debug: entry to enable ICP JTAG debugging
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* @icp_debug_type : entry to enable FW debug message/qdss
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* @icp_dbg_lvl : debug level set to FW.
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* @icp_fw_dump_lvl : level set for dumping the FW data
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* @icp_fw_ramdump_lvl : level set for FW ram dumps
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- * @dev_info: book keeping info relevant to devices
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- * @disable_ubwc_comp: Disable UBWC compression
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* @recovery: Flag to validate if in previous session FW
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* reported a fatal error or wdt. If set FW is
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* re-downloaded for new camera session.
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* @frame_in_process: Counter for frames in process
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* @frame_in_process_ctx_id: Contxt id processing frame
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- * @synx_signaling_en: core to core fencing is enabled
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- * using synx
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* @hw_cap_mask: device capability mask to indicate which devices type
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* are available in this hw mgr
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+ * @icp_booted: Processor is booted i.e. firmware loaded
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+ * @icp_resumed: Processor is powered on
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+ * @icp_pc_flag: Flag to enable/disable power collapse
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+ * @dev_pc_flag: Flag to enable/disable
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+ * power collapse for ipe & bps
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+ * @icp_use_pil: Flag to indicate usage of PIL framework
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+ * @icp_jtag_debug: entry to enable ICP JTAG debugging
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+ * @disable_ubwc_comp: Disable UBWC compression
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+ * @synx_signaling_en: core to core fencing is enabled
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+ * using synx
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*/
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struct cam_icp_hw_mgr {
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struct mutex hw_mgr_mutex;
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spinlock_t hw_mgr_lock;
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- struct cam_hw_intf **devices[CAM_ICP_HW_MAX];
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+ struct cam_icp_hw_device_info *dev_info;
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+ uint32_t num_dev_info;
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+ int8_t dev_info_idx[CAM_ICP_HW_MAX];
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struct cam_hw_intf *icp_dev_intf;
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- uint32_t hw_dev_cnt[CAM_ICP_HW_MAX];
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struct cam_icp_hw_ctx_data ctx_data[CAM_ICP_CTX_MAX];
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cam_icp_mini_dump_cb mini_dump_cb;
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char hw_mgr_name[CAM_ICP_HW_MGR_NAME_SIZE];
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uint32_t hw_mgr_id;
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- bool icp_booted;
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- bool icp_resumed;
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int32_t iommu_hdl;
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int32_t iommu_sec_hdl;
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int32_t hfi_handle;
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@@ -484,26 +485,26 @@ struct cam_icp_hw_mgr {
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struct hfi_msg_work_data *timer_work_data;
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uint32_t ctxt_cnt;
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struct dentry *dentry;
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- bool icp_pc_flag;
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- bool dev_pc_flag;
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- bool icp_use_pil;
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uint64_t icp_debug_clk;
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uint64_t icp_default_clk;
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- struct cam_icp_clk_info clk_info[ICP_DEV_CLK_MAX];
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uint32_t secure_mode;
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- bool icp_jtag_debug;
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u64 icp_debug_type;
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u64 icp_dbg_lvl;
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u64 icp_fw_dump_lvl;
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u32 icp_fw_ramdump_lvl;
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- struct cam_icp_hw_ctx_dev_info dev_info[CAM_ICP_DEV_NUM];
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- bool disable_ubwc_comp;
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atomic_t recovery;
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uint64_t icp_svs_clk;
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atomic_t frame_in_process;
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int frame_in_process_ctx_id;
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- bool synx_signaling_en;
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uint32_t hw_cap_mask;
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+ bool icp_booted;
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+ bool icp_resumed;
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+ bool icp_pc_flag;
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+ bool dev_pc_flag;
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+ bool icp_use_pil;
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+ bool icp_jtag_debug;
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+ bool disable_ubwc_comp;
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+ bool synx_signaling_en;
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};
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/**
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@@ -566,9 +567,11 @@ struct cam_icp_hw_ctx_mini_dump {
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* @ctx: Context for minidump
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* @hfi_info: hfi info
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* @hfi_mem_info: hfi mem info
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- * @dev_info: book keeping info relevant to devices
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+ * @dev_info: array of device info
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* @fw_img: FW image
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* @recovery: To indicate if recovery is on
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+ * @num_context: number of active context
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+ * @num_device_info: number of available device info
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* @icp_booted: Indicate if ICP is booted
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* @icp_resumed: Indicate if ICP is resumed
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* @disable_ubwc_comp: Indicate if ubws comp is disabled
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@@ -581,10 +584,11 @@ struct cam_icp_hw_mini_dump_info {
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struct cam_icp_hw_ctx_mini_dump *ctx[CAM_ICP_CTX_MAX];
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struct hfi_mini_dump_info hfi_info;
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struct icp_hfi_mem_info hfi_mem_info;
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- struct cam_icp_hw_ctx_dev_info dev_info[CAM_ICP_DEV_NUM];
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+ struct cam_icp_hw_device_info dev_info[CAM_ICP_DEV_NUM];
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void *fw_img;
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uint32_t recovery;
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uint32_t num_context;
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+ uint32_t num_device_info;
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bool icp_booted;
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bool icp_resumed;
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bool disable_ubwc_comp;
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Sokchetra Eung