Merge "disp: msm: fix rscc branch offset for lito"

msm/sde_rsc_hw.h

@@ -11,6 +11,7 @@
 #include <linux/sde_rsc.h>
 
 /* display rsc offset */
+#define SDE_RSCC_RSC_ID_DRV0				0x0
 #define SDE_RSCC_PDC_SEQ_START_ADDR_REG_OFFSET_DRV0	0x020
 #define SDE_RSCC_PDC_MATCH_VALUE_LO_REG_OFFSET_DRV0	0x024
 #define SDE_RSCC_PDC_MATCH_VALUE_HI_REG_OFFSET_DRV0	0x028

msm/sde_rsc_hw_v3.c

@@ -84,6 +84,7 @@ static int _rsc_hw_seq_memory_init_v3(struct sde_rsc_priv *rsc)
 	const u32 mode_0_start_addr = 0x0;
 	const u32 mode_1_start_addr = 0xc;
 	const u32 mode_2_start_addr = 0x18;
+	u32 br_offset = 0;
 
 	pr_debug("rsc sequencer memory init v2\n");
 
@@ -130,9 +131,12 @@ static int _rsc_hw_seq_memory_init_v3(struct sde_rsc_priv *rsc)
 						0x00209ce7, rsc->debug_mode);
 
 	/* branch address */
-	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_CFG_BR_ADDR_0_DRV0,
+	if (rsc->hw_drv_ver >= SDE_RSC_HW_MAJOR_MINOR_STEP(2,0,5))
+		br_offset = 0xf0;
+
+	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_CFG_BR_ADDR_0_DRV0 + br_offset,
 						0x34, rsc->debug_mode);
-	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_CFG_BR_ADDR_1_DRV0,
+	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_CFG_BR_ADDR_1_DRV0 + br_offset,
 						0x3c, rsc->debug_mode);
 
 	/* start address */
@@ -477,6 +481,9 @@ int rsc_hw_init_v3(struct sde_rsc_priv *rsc)
 {
 	int rc = 0;
 
+	rsc->hw_drv_ver = dss_reg_r(&rsc->drv_io,
+		SDE_RSCC_RSC_ID_DRV0, rsc->debug_mode);
+
 	rc = _rsc_hw_qtimer_init(rsc);
 	if (rc) {
 		pr_err("rsc hw qtimer init failed\n");

msm/sde_rsc_priv.h

@@ -28,6 +28,11 @@
 #define SDE_RSC_REV_2			0x2
 #define SDE_RSC_REV_3			0x3
 
+#define SDE_RSC_HW_MAJOR_MINOR_STEP(major, minor, step) \
+	(((major & 0xff) << 16) |\
+	((minor & 0xff) << 8) | \
+	(step & 0xff))
+
 struct sde_rsc_priv;
 
 /**
@@ -140,6 +145,7 @@ struct sde_rsc_bw_config {
 /**
  * struct sde_rsc_priv: sde resource state coordinator(rsc) private handle
  * @version:		rsc sequence version
+ * @hw_drv_ver:		rscc hw version
  * @phandle:		module power handle for clocks
  * @fs:			"MDSS GDSC" handle
  * @sw_fs_enabled:	track "MDSS GDSC" sw vote during probe
@@ -182,6 +188,7 @@ struct sde_rsc_bw_config {
  */
 struct sde_rsc_priv {
 	u32 version;
+	u32 hw_drv_ver;
 	struct sde_power_handle phandle;
 	struct regulator *fs;
 	bool sw_fs_enabled;