samsung-sm8650/android_kernel_samsung_sm8650-modules
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disp: msm: dsi: Fix pll delay calculation during clock switch

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During clock switch, Pll delay is calculated considering escape
clock to be in KHz. But escape clock is in Hz. This leads to wrong
pll delay calculation.

Change-Id: I616d16cc3d775a37e77c7c35bb860c23b1f9e37a
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
This commit is contained in:
Ritesh Kumar
2020-06-24 02:00:36 +05:30
committad av Steve Cohen
förälder d8ffbf3d39
incheckning a81e6a55fe
3 ändrade filer med 9 tillägg och 9 borttagningar
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8
msm/dsi/dsi_display.c
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@@ -4332,12 +4332,12 @@ static void _dsi_display_calc_pipe_delay(struct dsi_display *display,
cfg = &(m_ctrl->phy->cfg);
esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate * 1000;
pclk_to_esc_ratio = ((dsi_ctrl->clk_freq.pix_clk_rate * 1000) /
esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate;
pclk_to_esc_ratio = (dsi_ctrl->clk_freq.pix_clk_rate /
esc_clk_rate_hz);
byte_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 1000) /
byte_to_esc_ratio = (dsi_ctrl->clk_freq.byte_clk_rate /
esc_clk_rate_hz);
hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4 * 1000) /
hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4) /
esc_clk_rate_hz);
hsync_period = dsi_h_total_dce(&mode->timing);