disp: msm: dsi: Fix pll delay calculation during clock switch

During clock switch, Pll delay is calculated considering escape
clock to be in KHz. But escape clock is in Hz. This leads to wrong
pll delay calculation.

Change-Id: I616d16cc3d775a37e77c7c35bb860c23b1f9e37a
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>

msm/dsi/dsi_defs.h

@@ -556,7 +556,7 @@ struct dsi_cmd_engine_cfg {
  * @common_config:         Host configuration common to both Video and Cmd mode.
  * @video_engine:          Video engine configuration if panel is in video mode.
  * @cmd_engine:            Cmd engine configuration if panel is in cmd mode.
- * @esc_clk_rate_khz:      Esc clock frequency in Hz.
+ * @esc_clk_rate_hz:      Esc clock frequency in Hz.
  * @bit_clk_rate_hz:       Bit clock frequency in Hz.
  * @bit_clk_rate_hz_override: DSI bit clk rate override from dt/sysfs.
  * @video_timing:          Video timing information of a frame.