disp: msm: dsi: Fix pll delay calculation during clock switch

During clock switch, Pll delay is calculated considering escape
clock to be in KHz. But escape clock is in Hz. This leads to wrong
pll delay calculation.

Change-Id: I616d16cc3d775a37e77c7c35bb860c23b1f9e37a
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>

msm/dsi/dsi_clk.h

@@ -105,10 +105,10 @@ struct dsi_link_lp_clk_info {
 
 /**
  * struct link_clk_freq - Clock frequency information for Link clocks
- * @byte_clk_rate:   Frequency of DSI byte_clk in KHz.
- * @byte_intf_clk_rate:   Frequency of DSI byte_intf_clk in KHz.
- * @pixel_clk_rate:  Frequency of DSI pixel_clk in KHz.
- * @esc_clk_rate:    Frequency of DSI escape clock in KHz.
+ * @byte_clk_rate:   Frequency of DSI byte_clk in Hz.
+ * @byte_intf_clk_rate:   Frequency of DSI byte_intf_clk in Hz.
+ * @pixel_clk_rate:  Frequency of DSI pixel_clk in Hz.
+ * @esc_clk_rate:    Frequency of DSI escape clock in Hz.
  */
 struct link_clk_freq {
 	u32 byte_clk_rate;