qcacmn: Bypass GLINK/QMI for 8998 RUMI bring up

Bypass QMI for 8998 RUMI bring up as it doesn't support
QMI for now.
Increase regulatory timeout for slow RUMI setup.

Change-Id: Ie4d790a79aaa166731c876bdecf0f4f6970caae4
CRs-Fixed: 978953

hif/inc/regtable_pcie.h

@@ -272,6 +272,10 @@ struct targetdef_s {
 	uint32_t d_Q6_CLEAR_REGISTER_0;
 	uint32_t d_Q6_CLEAR_REGISTER_1;
 #endif
+
+#ifdef CONFIG_BYPASS_QMI
+	uint32_t d_BYPASS_QMI_TEMP_REGISTER;
+#endif
 };
 
 #define A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK \
@@ -699,6 +703,11 @@ struct targetdef_s {
 	(scn->targetdef->d_Q6_CLEAR_REGISTER_1)
 #endif
 
+#ifdef CONFIG_BYPASS_QMI
+#define BYPASS_QMI_TEMP_REGISTER \
+	(scn->targetdef->d_BYPASS_QMI_TEMP_REGISTER)
+#endif
+
 struct hostdef_s {
 	uint32_t d_INT_STATUS_ENABLE_ERROR_LSB;
 	uint32_t d_INT_STATUS_ENABLE_ERROR_MASK;

hif/src/adrastea_reg_def.h

@@ -1815,6 +1815,8 @@
 #define ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK        0x0
 /* end: Q6 iHelium emulation registers */
 
+#define ADRASTEA_BYPASS_QMI_TEMP_REGISTER    0x00032064
+
 struct targetdef_s adrastea_targetdef = {
 	.d_RTC_SOC_BASE_ADDRESS = ADRASTEA_RTC_SOC_BASE_ADDRESS,
 	.d_RTC_WMAC_BASE_ADDRESS = ADRASTEA_RTC_WMAC_BASE_ADDRESS,
@@ -2090,6 +2092,10 @@ struct targetdef_s adrastea_targetdef = {
 	.d_Q6_CLEAR_REGISTER_0 = ADRASTEA_Q6_CLEAR_REGISTER_0,
 	.d_Q6_CLEAR_REGISTER_1 = ADRASTEA_Q6_CLEAR_REGISTER_1,
 #endif
+
+#ifdef CONFIG_BYPASS_QMI
+	.d_BYPASS_QMI_TEMP_REGISTER = ADRASTEA_BYPASS_QMI_TEMP_REGISTER,
+#endif
 };
 
 struct hostdef_s adrastea_hostdef = {

hif/src/ce/ce_main.c

@@ -63,6 +63,12 @@ static int hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info);
 /* #define BMI_RSP_POLLING */
 #define BMI_RSP_TO_MILLISEC  1000
 
+#ifdef CONFIG_BYPASS_QMI
+#define BYPASS_QMI 1
+#else
+#define BYPASS_QMI 0
+#endif
+
 
 static int hif_post_recv_buffers(struct hif_softc *scn);
 static void hif_config_rri_on_ddr(struct hif_softc *scn);
@@ -1570,7 +1576,10 @@ int hif_wlan_enable(struct hif_softc *scn)
 	else
 		mode = ICNSS_MISSION;
 
-	return icnss_wlan_enable(&cfg, mode, QWLAN_VERSIONSTR);
+	if (BYPASS_QMI)
+		return 0;
+	else
+		return icnss_wlan_enable(&cfg, mode, QWLAN_VERSIONSTR);
 }
 
 /**
@@ -1647,6 +1656,46 @@ void hif_unconfig_ce(struct hif_softc *hif_sc)
 	}
 }
 
+#ifdef CONFIG_BYPASS_QMI
+#define FW_SHARED_MEM (2 * 1024 * 1024)
+
+/**
+ * hif_post_static_buf_to_target() - post static buffer to WLAN FW
+ * @scn: pointer to HIF structure
+ *
+ * WLAN FW needs 2MB memory from DDR when QMI is disabled.
+ *
+ * Return: void
+ */
+static void hif_post_static_buf_to_target(struct hif_softc *scn)
+{
+	uint32_t CE_data;
+	uint8_t *g_fw_mem;
+	uint32_t phys_addr;
+
+	g_fw_mem = kzalloc(FW_SHARED_MEM, GFP_KERNEL);
+
+	CE_data = dma_map_single(scn->cdf_dev->dev, g_fw_mem,
+				 FW_SHARED_MEM, CDF_DMA_FROM_DEVICE);
+	HIF_TRACE("g_fw_mem %p physical 0x%x\n", g_fw_mem, CE_data);
+
+	if (dma_mapping_error(scn->cdf_dev->dev, CE_data)) {
+		pr_err("DMA map failed\n");
+		return;
+	}
+
+	phys_addr = virt_to_phys((scn->mem + BYPASS_QMI_TEMP_REGISTER));
+	hif_write32_mb(scn->mem + BYPASS_QMI_TEMP_REGISTER, CE_data);
+	HIF_TRACE("Write phy address 0x%x into scratch reg %p phy add 0x%x",
+		  CE_data, (scn->mem + BYPASS_QMI_TEMP_REGISTER), phys_addr);
+}
+#else
+static inline void hif_post_static_buf_to_target(struct hif_softc *scn)
+{
+	return;
+}
+#endif
+
 /**
  * hif_config_ce() - configure copy engines
  * @scn: hif context
@@ -1671,6 +1720,8 @@ int hif_config_ce(struct hif_softc *scn)
 
 	scn->notice_send = true;
 
+	hif_post_static_buf_to_target(scn);
+
 	hif_state->fw_indicator_address = FW_INDICATOR_ADDRESS;
 
 	hif_config_rri_on_ddr(scn);