ipa: added more missing registers to ipa_reg_save struct

Added more DEBUG registers, checked and fixed existing structs
in ipa_reg_save

Change-Id: I95add61146e45d1faf8fd1c625cdb34749395f1e
Signed-off-by: Dima Birenbaum <[email protected]>
Signed-off-by: Ilia Lin <[email protected]>

drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/gsi_hwio_def.h

@@ -4987,5 +4987,166 @@ union gsi_hwio_def_ipa_0_gsi_top_xpu3_rgn_wacr_u
   u32 value;
 };
 
+/*===========================================================================*/
+/*!
+  @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_LSB
+*/
+/*===========================================================================*/
+/* Structure definition of register */
+struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_s
+{
+  u32 bp_cnt_lsb : 32;
+};
+
+/* Union definition of register */
+union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_u
+{
+  struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_s def;
+  u32 value;
+};
+
+/*===========================================================================*/
+/*!
+  @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_CNT_MSB
+*/
+/*===========================================================================*/
+/* Structure definition of register */
+struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_msb_s
+{
+  u32 bp_cnt_msb : 32;
+};
+
+/* Union definition of register */
+union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_msb_u
+{
+  struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_msb_s def;
+  u32 value;
+};
+
+/*===========================================================================*/
+/*!
+  @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB
+*/
+/*===========================================================================*/
+/* Structure definition of register */
+struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s
+{
+  u32 bp_and_pending_cnt_lsb : 32;
+};
+
+/* Union definition of register */
+union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_u
+{
+  struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s def;
+  u32 value;
+};
+
+/*===========================================================================*/
+/*!
+  @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB
+*/
+/*===========================================================================*/
+/* Structure definition of register */
+struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_s
+{
+  u32 bp_and_pending_cnt_msb : 32;
+};
+
+/* Union definition of register */
+union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_u
+{
+  struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_s def;
+  u32 value;
+};
+
+/*===========================================================================*/
+/*!
+  @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB
+*/
+/*===========================================================================*/
+/* Structure definition of register */
+struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_s
+{
+  u32 mcs_busy_cnt_lsb : 32;
+};
+
+/* Union definition of register */
+union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_u
+{
+  struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_s def;
+  u32 value;
+};
+
+/*===========================================================================*/
+/*!
+  @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB
+*/
+/*===========================================================================*/
+/* Structure definition of register */
+struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_s
+{
+  u32 mcs_busy_cnt_msb : 32;
+};
+
+/* Union definition of register */
+union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_u
+{
+  struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_s def;
+  u32 value;
+};
+
+/*===========================================================================*/
+/*!
+  @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB
+*/
+/*===========================================================================*/
+/* Structure definition of register */
+struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_s
+{
+  u32 mcs_idle_cnt_lsb : 32;
+};
+
+/* Union definition of register */
+union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_u
+{
+  struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_s def;
+  u32 value;
+};
+
+/*===========================================================================*/
+/*!
+  @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB
+*/
+/*===========================================================================*/
+/* Structure definition of register */
+struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_s
+{
+  u32 mcs_idle_cnt_msb : 32;
+};
+
+/* Union definition of register */
+union gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_u
+{
+  struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_s def;
+  u32 value;
+};
+
+/*===========================================================================*/
+/*!
+  @brief Bit Field definition of register: IPA_0_GSI_TOP_GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD
+*/
+/*===========================================================================*/
+/* Structure definition of register */
+struct gsi_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_s
+{
+  u32 msk_reg : 32;
+};
+
+/* Union definition of register */
+union gsi_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_u
+{
+  struct gsi_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_s def;
+  u32 value;
+};
 
 #endif /* __GSI_HWIO_DEF_H__ */

drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hw_common_ex.h

@@ -488,7 +488,11 @@ enum ipa_hw_irq_srcs_e {
 /*
  * SHRAM Bytes per ch
  */
+#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
+#define IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM         20
+#else
 #define IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM         12
+#endif
 
 /*
  * Total number of rx splt cmdq's see:

drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hwio_def.h

@@ -19044,5 +19044,48 @@ union ipa_hwio_def_ipa_ms_mpu_cfg_xpu3_rgn_end0_u
   u32 value;
 };
 
+/*===========================================================================*/
+/*!
+  @brief Bit Field definition of register: IPA_0_IPA_RSRC_GRP_CFG_EXT
+*/
+/*===========================================================================*/
+/* Structure definition of register */
+struct ipa_hwio_def_ipa_0_ipa_rsrc_grp_cfg_ext_s
+{
+  u32 src_grp_2nd_priority_special_valid : 1;
+  u32 reserved0 : 3;
+  u32 src_grp_2nd_priority_special_index : 3;
+  u32 reserved1 : 25;
+};
+
+/* Union definition of register */
+union ipa_hwio_def_ipa_0_ipa_rsrc_grp_cfg_ext_u
+{
+  struct ipa_hwio_def_ipa_0_ipa_rsrc_grp_cfg_ext_s def;
+  u32 value;
+};
+
+/*===========================================================================*/
+/*!
+  @brief Bit Field definition of fc_stats
+*/
+/*===========================================================================*/
+/* Structure definition of register */
+struct ipa_hwio_def_fc_stats_state_s
+{
+  u32 reserved0 : 16;
+  u32 flow_control : 1;
+  u32 flow_control_primary : 1;
+  u32 flow_control_secondary : 1;
+  u32 pending_flow_control : 1;
+  u32 reserved1 : 12;
+};
+
+/* Union definition of register */
+union ipa_hwio_def_fc_stats_state_u
+{
+  struct ipa_hwio_def_fc_stats_state_s def;
+  u32 value;
+};
 
 #endif /* __IPA_HWIO_DEF_H__ */

drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c

@@ -325,6 +325,11 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
 	GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_CFG,
 			     ipa.gen,
 			     ipa_filt_rout_cfg),
+#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
+	GEN_SRC_DST_ADDR_MAP(IPA_RSRC_GRP_CFG_EXT,
+			     ipa.gen,
+			     ipa_rsrc_grp_cfg_ext),
+#endif
 #endif
 
 	/* Debug Registers */
@@ -644,7 +649,32 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
 	GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID,
 			     gsi.debug,
 			     ipa_gsi_top_gsi_debug_qsb_log_err_trns_id),
-
+#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
+	GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_CNT_LSB,
+			     gsi.debug.gsi_mcs_prof_regs,
+			     gsi_top_gsi_mcs_profiling_bp_cnt_lsb),
+	GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_CNT_MSB,
+			     gsi.debug.gsi_mcs_prof_regs,
+			     gsi_top_gsi_mcs_profiling_bp_cnt_msb),
+	GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB,
+			     gsi.debug.gsi_mcs_prof_regs,
+			     gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb),
+	GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB,
+			     gsi.debug.gsi_mcs_prof_regs,
+			     gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb),
+	GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB,
+			     gsi.debug.gsi_mcs_prof_regs,
+			     gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb),
+	GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB,
+			     gsi.debug.gsi_mcs_prof_regs,
+			     gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb),
+	GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB,
+			     gsi.debug.gsi_mcs_prof_regs,
+			     gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb),
+	GEN_SRC_DST_ADDR_MAP(GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB,
+			     gsi.debug.gsi_mcs_prof_regs,
+			     gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb),
+#endif
 	IPA_REG_SAVE_CFG_ENTRY_GSI_QSB_DEBUG(
 		GSI_DEBUG_QSB_LOG_LAST_MISC_IDn, qsb_log_last_misc),
 
@@ -811,6 +841,20 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
 					    ee_n_gsi_ch_k_scratch_2),
 	IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_3,
 					    ee_n_gsi_ch_k_scratch_3),
+#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
+	IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_4,
+					    ee_n_gsi_ch_k_scratch_4),
+	IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_5,
+					    ee_n_gsi_ch_k_scratch_5),
+	IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_6,
+					    ee_n_gsi_ch_k_scratch_6),
+	IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_7,
+					    ee_n_gsi_ch_k_scratch_7),
+	IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_8,
+					    ee_n_gsi_ch_k_scratch_8),
+	IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_9,
+					    ee_n_gsi_ch_k_scratch_9),
+#endif
 	IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(GSI_MAP_EE_n_CH_k_VP_TABLE,
 					    gsi_map_ee_n_ch_k_vp_table),
 
@@ -850,6 +894,12 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
 	IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(GSI_DEBUG_EE_n_EV_k_VP_TABLE,
 					     gsi_debug_ee_n_ev_k_vp_table),
 
+#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
+/* GSI Debug SW MSK Registers */
+	IPA_REG_SAVE_GSI_DEBUG_MSK_REG_ENTRY(GSI_DEBUG_SW_MSK_REG_n_SEC_k_RD,
+			                    regs),
+#endif
+
 #if defined(CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS) && \
 	CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS > 0
 	/* Endp Registers for remaining pipes */
@@ -1047,6 +1097,8 @@ void ipa_save_gsi_ver(void)
 void ipa_save_registers(void)
 {
 	u32 i = 0;
+	u32 phys_ch_idx = 0;
+	u32 n = 0;
 	/* Fetch the number of registers configured to be saved */
 	u32 num_regs = ARRAY_SIZE(ipa_regs_to_save_array);
 	u32 num_uc_per_regs = ARRAY_SIZE(ipa_uc_regs_to_save_array);
@@ -1156,70 +1208,90 @@ void ipa_save_registers(void)
 			(u16)IPA_READ_1xVECTOR_REG(GSI_DEBUG_COUNTERn, i);
 
 	for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7; i++) {
-		u32 phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.a7[
+		phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.a7[
 			i].gsi_map_ee_n_ch_k_vp_table.phy_ch;
-		u32 n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM;
+		n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM;
 
 		if (!ipa_reg_save.gsi.ch_cntxt.a7[
 				i].gsi_map_ee_n_ch_k_vp_table.valid)
 			continue;
 
 		ipa_reg_save.gsi.ch_cntxt.a7[
-			i].mcs_channel_scratch.scratch4.shram =
+			i].mcs_channel_scratch.scratch_for_seq_low.shram =
 			IPA_READ_1xVECTOR_REG(
 				GSI_SHRAM_n,
-				n + IPA_GSI_OFFSET_WORDS_SCRATCH4);
+				n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW);
 
 		ipa_reg_save.gsi.ch_cntxt.a7[
-			i].mcs_channel_scratch.scratch5.shram =
+			i].mcs_channel_scratch.scratch_for_seq_high.shram =
 			IPA_READ_1xVECTOR_REG(
 				GSI_SHRAM_n,
-				n + IPA_GSI_OFFSET_WORDS_SCRATCH5);
+				n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH);
+#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
+		ipa_reg_save.gsi.ch_cntxt.a7[
+			i].fc_stats_state.value = IPA_READ_1xVECTOR_REG(
+				GSI_SHRAM_n,
+				n + IPA_REG_SAVE_FC_STATE_OFFSET);
 	}
+#endif
 
 	for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC; i++) {
-		u32 phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.uc[
+		phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.uc[
 			i].gsi_map_ee_n_ch_k_vp_table.phy_ch;
-		u32 n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM;
+		n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM;
 
 		if (!ipa_reg_save.gsi.ch_cntxt.uc[
 				i].gsi_map_ee_n_ch_k_vp_table.valid)
 			continue;
 
 		ipa_reg_save.gsi.ch_cntxt.uc[
-			i].mcs_channel_scratch.scratch4.shram =
+			i].mcs_channel_scratch.scratch_for_seq_low.shram =
 			IPA_READ_1xVECTOR_REG(
 				GSI_SHRAM_n,
-				n + IPA_GSI_OFFSET_WORDS_SCRATCH4);
+				n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW);
 
 		ipa_reg_save.gsi.ch_cntxt.uc[
-			i].mcs_channel_scratch.scratch5.shram =
+			i].mcs_channel_scratch.scratch_for_seq_high.shram =
 			IPA_READ_1xVECTOR_REG(
 				GSI_SHRAM_n,
-				n + IPA_GSI_OFFSET_WORDS_SCRATCH5);
+				n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH);
+
+#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
+		ipa_reg_save.gsi.ch_cntxt.uc[
+			i].fc_stats_state.value = IPA_READ_1xVECTOR_REG(
+				GSI_SHRAM_n,
+				n + IPA_REG_SAVE_FC_STATE_OFFSET);
 	}
+#endif
 
 	for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6; i++) {
-		u32 phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.q6[
+		phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.q6[
 			i].gsi_map_ee_n_ch_k_vp_table.phy_ch;
-		u32 n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM;
+		n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM;
 
 		if (!ipa_reg_save.gsi.ch_cntxt.q6[
 				i].gsi_map_ee_n_ch_k_vp_table.valid)
 			continue;
 
 		ipa_reg_save.gsi.ch_cntxt.q6[
-			i].mcs_channel_scratch.scratch4.shram =
+			i].mcs_channel_scratch.scratch_for_seq_low.shram =
 			IPA_READ_1xVECTOR_REG(
-			GSI_SHRAM_n,
-			n + IPA_GSI_OFFSET_WORDS_SCRATCH4);
+				GSI_SHRAM_n,
+				n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW);
 
 		ipa_reg_save.gsi.ch_cntxt.q6[
-			i].mcs_channel_scratch.scratch5.shram =
+			i].mcs_channel_scratch.scratch_for_seq_high.shram =
 			IPA_READ_1xVECTOR_REG(
-			GSI_SHRAM_n,
-			n + IPA_GSI_OFFSET_WORDS_SCRATCH5);
+				GSI_SHRAM_n,
+				n + IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH);
+
+#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
+		ipa_reg_save.gsi.ch_cntxt.q6[
+			i].fc_stats_state.value = IPA_READ_1xVECTOR_REG(
+				GSI_SHRAM_n,
+				n + IPA_REG_SAVE_FC_STATE_OFFSET);
 	}
+#endif
 
 	/*
 	 * On targets that support SSR, we generally want to disable
@@ -1329,20 +1401,17 @@ void ipa_save_registers(void)
  */
 static void ipa_reg_save_gsi_fifo_status(void)
 {
-	union ipa_hwio_def_ipa_gsi_fifo_status_ctrl_u gsi_fifo_status_ctrl;
 	u8 i;
-
-	memset(&gsi_fifo_status_ctrl, 0, sizeof(gsi_fifo_status_ctrl));
-
 	for (i = 0; i < IPA_HW_PIPE_ID_MAX; i++) {
-		gsi_fifo_status_ctrl.def.ipa_gsi_fifo_status_en = 1;
-		gsi_fifo_status_ctrl.def.ipa_gsi_fifo_status_port_sel = i;
+		memset(&ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl,
+		       0, sizeof(ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl));
+
+		ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl.def.ipa_gsi_fifo_status_en = 1;
+		ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl.def.ipa_gsi_fifo_status_port_sel = i;
 
 		IPA_MASKED_WRITE_SCALER_REG(IPA_GSI_FIFO_STATUS_CTRL,
-				     gsi_fifo_status_ctrl.value);
+				     ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl.value);
 
-		ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl.value =
-			IPA_READ_SCALER_REG(IPA_GSI_FIFO_STATUS_CTRL);
 		ipa_reg_save.gsi_fifo_status[i].gsi_tlv_fifo_status.value =
 			IPA_READ_SCALER_REG(IPA_GSI_TLV_FIFO_STATUS);
 		ipa_reg_save.gsi_fifo_status[i].gsi_aos_fifo_status.value =

drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h

@@ -25,84 +25,85 @@
 #include "gsi_hwio_def.h"
 #include "ipa_gcc_hwio_def.h"
 
-#define IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS     0x6
-#define IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS     0x4
-#define IPA_DEBUG_TESTBUS_RSRC_NUM_EP            7
-#define IPA_DEBUG_TESTBUS_RSRC_NUM_GRP           3
-#define IPA_TESTBUS_SEL_EP_MAX                   0x1F
-#define IPA_TESTBUS_SEL_EXTERNAL_MAX             0x40
-#define IPA_TESTBUS_SEL_INTERNAL_MAX             0xFF
-#define IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX        0x40
-#define IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS     0x9
-#define IPA_RSCR_MNGR_DB_RSRC_ID_MAX             0x3F
-#define IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX           0xA
-
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_ZEROS   (0x0)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_0   (0x1)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_1   (0x2)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_2   (0x3)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_3   (0x4)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_4   (0x5)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_DB_ENG  (0x9)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_0   (0xB)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_1   (0xC)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_2   (0xD)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_3   (0xE)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_4   (0xF)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_5   (0x10)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_6   (0x11)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_7   (0x12)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_0   (0x13)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_1   (0x14)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_2   (0x15)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_3   (0x16)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_4   (0x17)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_5   (0x18)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_0    (0x1B)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_1    (0x1C)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_0    (0x1F)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_1    (0x20)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_2    (0x21)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_3    (0x22)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_4    (0x23)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_0  (0x27)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_1  (0x28)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_2  (0x29)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_3  (0x2A)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_0   (0x2B)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_1   (0x2C)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_2   (0x2D)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_3   (0x2E)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_0 (0x33)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_1 (0x34)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_2 (0x35)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_3 (0x36)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR     (0x3A)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_0  (0x3C)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_1  (0x3D)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_2    (0x1D)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_1   (0x3E)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_2   (0x3F)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_5   (0x40)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_5    (0x41)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_3   (0x42)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TLV_0   (0x43)
-#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_8   (0x44)
-
-#define IPA_DEBUG_TESTBUS_DEF_EXTERNAL           50
-#define IPA_DEBUG_TESTBUS_DEF_INTERNAL           6
-
-#define IPA_REG_SAVE_GSI_NUM_EE                  3
-
-#define IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS         22
-
-#define IPA_GSI_OFFSET_WORDS_SCRATCH4            6
-#define IPA_GSI_OFFSET_WORDS_SCRATCH5            7
-
-#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_BIT_MASK 0x7E000
-#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_SHIFT    13
-
-#define IPA_REG_SAVE_HWP_GSI_EE                  2
+#define IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS              0x6
+#define IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS              0x4
+#define IPA_DEBUG_TESTBUS_RSRC_NUM_EP                     7
+#define IPA_DEBUG_TESTBUS_RSRC_NUM_GRP                    3
+#define IPA_TESTBUS_SEL_EP_MAX                            0x1F
+#define IPA_TESTBUS_SEL_EXTERNAL_MAX                      0x40
+#define IPA_TESTBUS_SEL_INTERNAL_MAX                      0xFF
+#define IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX                 0x40
+#define IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS              0x9
+#define IPA_RSCR_MNGR_DB_RSRC_ID_MAX                      0x3F
+#define IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX                    0xA
+#define IPA_REG_SAVE_FC_STATE_OFFSET                      7
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_ZEROS            (0x0)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_0            (0x1)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_1            (0x2)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_2            (0x3)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_3            (0x4)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_4            (0x5)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_DB_ENG           (0x9)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_0            (0xB)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_1            (0xC)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_2            (0xD)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_3            (0xE)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_4            (0xF)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_5            (0x10)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_6            (0x11)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_7            (0x12)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_0            (0x13)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_1            (0x14)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_2            (0x15)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_3            (0x16)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_4            (0x17)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_5            (0x18)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_0             (0x1B)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_1             (0x1C)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_0             (0x1F)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_1             (0x20)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_2             (0x21)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_3             (0x22)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_4             (0x23)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_0           (0x27)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_1           (0x28)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_2           (0x29)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_3           (0x2A)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_0            (0x2B)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_1            (0x2C)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_2            (0x2D)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_3            (0x2E)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_0          (0x33)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_1          (0x34)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_2          (0x35)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_3          (0x36)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR              (0x3A)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_0           (0x3C)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_1           (0x3D)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_2             (0x1D)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_1            (0x3E)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_2            (0x3F)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_5            (0x40)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_5             (0x41)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_3            (0x42)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TLV_0            (0x43)
+#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_8            (0x44)
+#define IPA_DEBUG_TESTBUS_DEF_EXTERNAL                    50
+#define IPA_DEBUG_TESTBUS_DEF_INTERNAL                    6
+#define IPA_REG_SAVE_GSI_NUM_EE                           3
+#define IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS                  22
+#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
+#define IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW          18
+#define IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH         19
+#else
+#define IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_LOW          6
+#define IPA_GSI_OFFSET_WORDS_SCRATCH_FOR_SEQ_HIGH         7
+#endif
+#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_BIT_MASK          0x7E000
+#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_SHIFT             13
+#define IPA_REG_SAVE_HWP_GSI_EE                           2
+#define GSI_HW_DEBUG_SW_MSK_REG_ARRAY_LENGTH              9
+#define GSI_HW_DEBUG_SW_MSK_REG_MAXk                      2
 
 /*
  * A structure used to map a source address to destination address...
@@ -509,6 +510,66 @@ struct map_src_dst_addr_s {
 		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[10].var_name, \
 		GEN_REG_ATTR(reg_name) }
 
+/*
+ * Macro to define a debug SW MSK register entry for all (n, k)
+ * k bound by GSI_HW_DEBUG_SW_MSK_REG_MAXk
+ */
+#define IPA_REG_SAVE_GSI_DEBUG_MSK_REG_ENTRY(reg_name, var_name) \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 0, 0), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[0].var_name[0], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 0, 1), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[0].var_name[1], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 1, 0), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[1].var_name[0], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 1, 1), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[1].var_name[1], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 2, 0), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[2].var_name[0], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 2, 1), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[2].var_name[1], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 3, 0), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[3].var_name[0], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 3, 1), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[3].var_name[1], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 4, 0), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[4].var_name[0], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 4, 1), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[4].var_name[1], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 5, 0), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[5].var_name[0], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 5, 1), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[5].var_name[1], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 6, 0), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[6].var_name[0], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 6, 1), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[6].var_name[1], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 7, 0), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[7].var_name[0], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 7, 1), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[7].var_name[1], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 8, 0), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[8].var_name[0], \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, 8, 1), \
+		(u32 *)&ipa_reg_save.gsi.debug.debug_sw_msk.mask_reg[8].var_name[1], \
+		GEN_REG_ATTR(reg_name) }
+
 #define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \
 	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
 		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name, \
@@ -1002,6 +1063,10 @@ struct ipa_gen_regs_s {
 	  ipa_local_pkt_proc_cntxt_base;
 	struct ipa_hwio_def_ipa_rsrc_grp_cfg_s
 	  ipa_rsrc_grp_cfg;
+#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
+	struct ipa_hwio_def_ipa_0_ipa_rsrc_grp_cfg_ext_s
+	  ipa_rsrc_grp_cfg_ext;
+#endif
 	struct ipa_hwio_def_ipa_comp_cfg_s
 	  ipa_comp_cfg;
 	struct ipa_hwio_def_ipa_state_dpl_fifo_s
@@ -1639,6 +1704,25 @@ struct ipa_reg_save_gsi_mcs_regs_s {
 		mcs_reg[HWIO_GSI_DEBUG_SW_RF_n_READ_MAXn + 1];
 };
 
+struct ipa_reg_save_gsi_mcs_prof_regs_s {
+        struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_lsb_s
+	       gsi_top_gsi_mcs_profiling_bp_cnt_lsb;
+	struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_cnt_msb_s
+	       gsi_top_gsi_mcs_profiling_bp_cnt_msb;
+	struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb_s
+	       gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_lsb;
+	struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb_s
+	       gsi_top_gsi_mcs_profiling_bp_and_pending_cnt_msb;
+	struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb_s
+	       gsi_top_gsi_mcs_profiling_mcs_busy_cnt_lsb;
+	struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb_s
+	       gsi_top_gsi_mcs_profiling_mcs_busy_cnt_msb;
+	struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb_s
+	       gsi_top_gsi_mcs_profiling_mcs_idle_cnt_lsb;
+	struct gsi_hwio_def_ipa_0_gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb_s
+	       gsi_top_gsi_mcs_profiling_mcs_idle_cnt_msb;
+};
+
 /* GSI debug counters save data struct */
 struct ipa_reg_save_gsi_debug_cnt_s {
 	struct
@@ -1681,6 +1765,17 @@ struct ipa_reg_save_gsi_iram_ptr_regs_s {
 #endif
 };
 
+/* GSI Debug SW registers save data struct */
+struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_entry_rd_s{
+	struct gsi_hwio_def_ipa_0_gsi_top_gsi_debug_sw_msk_reg_n_sec_k_rd_s
+		regs[GSI_HW_DEBUG_SW_MSK_REG_MAXk];
+};
+
+struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_rd_s{
+	struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_entry_rd_s
+		mask_reg[GSI_HW_DEBUG_SW_MSK_REG_ARRAY_LENGTH];
+};
+
 /* GSI SHRAM pointers save data struct */
 struct ipa_reg_save_gsi_shram_ptr_regs_s {
 	struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s
@@ -1717,20 +1812,27 @@ struct ipa_reg_save_gsi_debug_s {
 	  ipa_gsi_top_gsi_debug_pc_for_debug;
 	struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_s
 	  ipa_gsi_top_gsi_debug_qsb_log_err_trns_id;
-	struct ipa_reg_save_gsi_qsb_debug_s	gsi_qsb_debug;
+	struct ipa_reg_save_gsi_qsb_debug_s		gsi_qsb_debug;
 	struct ipa_reg_save_gsi_test_bus_s		gsi_test_bus;
 	struct ipa_reg_save_gsi_mcs_regs_s		gsi_mcs_regs;
+#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
+	struct ipa_reg_save_gsi_mcs_prof_regs_s		gsi_mcs_prof_regs;
+#endif
 	struct ipa_reg_save_gsi_debug_cnt_s		gsi_cnt_regs;
 	struct ipa_reg_save_gsi_iram_ptr_regs_s		gsi_iram_ptrs;
 	struct ipa_reg_save_gsi_shram_ptr_regs_s	gsi_shram_ptrs;
+#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
+	struct gsi_hwio_gsi_top_gsi_debug_sw_msk_regs_rd_s
+	       debug_sw_msk;
+#endif
 };
 
 /* GSI MCS channel scratch registers save data struct */
 struct ipa_reg_save_gsi_mcs_channel_scratch_regs_s {
 	struct gsi_hwio_def_gsi_shram_n_s
-	  scratch4;
+	  scratch_for_seq_low;
 	struct gsi_hwio_def_gsi_shram_n_s
-	  scratch5;
+	  scratch_for_seq_high;
 };
 
 /* GSI Channel Context register save data struct */
@@ -1765,9 +1867,28 @@ struct ipa_reg_save_gsi_ch_cntxt_per_ep_s {
 	  ee_n_gsi_ch_k_scratch_2;
 	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s
 	  ee_n_gsi_ch_k_scratch_3;
+#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
+	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_4_s
+	  ee_n_gsi_ch_k_scratch_4;
+	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_5_s
+	  ee_n_gsi_ch_k_scratch_5;
+	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_6_s
+	  ee_n_gsi_ch_k_scratch_6;
+	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_7_s
+	  ee_n_gsi_ch_k_scratch_7;
+	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_8_s
+	  ee_n_gsi_ch_k_scratch_8;
+	struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_9_s
+	  ee_n_gsi_ch_k_scratch_9;
+#endif
 	struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s
 	  gsi_map_ee_n_ch_k_vp_table;
-	struct ipa_reg_save_gsi_mcs_channel_scratch_regs_s mcs_channel_scratch;
+	struct ipa_reg_save_gsi_mcs_channel_scratch_regs_s
+	  mcs_channel_scratch;
+#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
+	union ipa_hwio_def_fc_stats_state_u
+	  fc_stats_state;
+#endif
 };
 
 /* GSI Event Context register save data struct */