disp: msm: sde: add support for stale llcc APIs

This change adds support for enabling the system cache
slices with staling. This allows back to back static display
cache usecases to self evict prior to using cache.

Change-Id: Iea71da26a8f7a450822624305dc20a3bab323d4b
Signed-off-by: Nilaan Gunabalachandran <[email protected]>

msm/sde/sde_core_perf.c

@@ -13,7 +13,6 @@
 #include <linux/clk.h>
 #include <linux/bitmap.h>
 #include <linux/sde_rsc.h>
-#include <linux/soc/qcom/llcc-qcom.h>
 
 #include "msm_prop.h"
 
@@ -311,6 +310,56 @@ static inline enum sde_crtc_client_type _get_sde_client_type(
 		return RT_CLIENT;
 }
 
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0))
+void sde_core_perf_llcc_stale_configure(struct sde_mdss_cfg *sde_cfg, struct llcc_slice_desc *slice)
+{
+	struct llcc_staling_mode_params params = {0};
+
+	if (!sde_cfg || !slice || !test_bit(SDE_FEATURE_SYS_CACHE_STALING, sde_cfg->features))
+		return;
+
+	llcc_configure_staling_mode(slice, &params);
+}
+
+void sde_core_perf_llcc_stale_frame(struct drm_crtc *crtc, enum sde_sys_cache_type type)
+{
+	struct llcc_slice_desc *slice;
+	struct sde_kms *kms;
+
+	if (!crtc) {
+		SDE_ERROR("invalid crtc\n");
+		return;
+	}
+
+	kms = _sde_crtc_get_kms(crtc);
+	if (!kms || !kms->catalog) {
+		SDE_ERROR("invalid kms\n");
+		return;
+	}
+
+	if (!test_bit(SDE_FEATURE_SYS_CACHE_STALING, kms->catalog->features) ||
+			!kms->perf.llcc_active[type])
+		return;
+
+	slice =  llcc_slice_getd(kms->catalog->sc_cfg[type].llcc_uid);
+	if (IS_ERR_OR_NULL(slice)) {
+		SDE_DEBUG("failed to get system cache for scid:%u", type);
+		return;
+	}
+
+	llcc_notif_staling_inc_counter(slice);
+
+	llcc_slice_putd(slice);
+}
+#else
+void sde_core_perf_llcc_stale_configure(struct sde_mdss_cfg *sde_cfg, struct llcc_slice_desc *slice)
+{
+}
+void sde_core_perf_llcc_stale_frame(struct drm_crtc *crtc, enum sde_sys_cache_type type)
+{
+}
+#endif
+
 /**
  * @_sde_core_perf_activate_llcc() - Activates/deactivates the system llcc
  * @kms - pointer to the kms

msm/sde/sde_core_perf.h

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -10,6 +11,7 @@
 #include <linux/dcache.h>
 #include <linux/mutex.h>
 #include <drm/drm_crtc.h>
+#include <linux/soc/qcom/llcc-qcom.h>
 
 #include "sde_hw_catalog.h"
 #include "sde_power_handle.h"
@@ -102,6 +104,21 @@ struct sde_core_perf {
 	u32 sys_cache_enabled;
 };
 
+/**
+ * sde_core_perf_llcc_stale_configure - configure llcc staling feature
+ * @sde_cfg: Pointer to sde catalog
+ * @slice:   Pointer to llcc slice
+ */
+void sde_core_perf_llcc_stale_configure(struct sde_mdss_cfg *sde_cfg,
+		struct llcc_slice_desc *slice);
+
+/**
+ * sde_core_perf_llcc_stale_frame - update llcc stale frame
+ * @crtc: Pointer to crtc
+ * @type: System Cache type
+ */
+void sde_core_perf_llcc_stale_frame(struct drm_crtc *crtc, enum sde_sys_cache_type type);
+
 /**
  * sde_core_perf_crtc_update_llcc - update llcc performance for crtc
  * @crtc: Pointer to crtc

msm/sde/sde_crtc.c

@@ -7845,6 +7845,7 @@ void sde_crtc_static_img_control(struct drm_crtc *crtc,
 
 		kthread_cancel_delayed_work_sync(
 				&sde_crtc->static_cache_read_work);
+		sde_core_perf_llcc_stale_frame(crtc, SDE_SYS_CACHE_DISP);
 		break;
 	case CACHE_STATE_FRAME_WRITE:
 		if (sde_crtc->cache_state != CACHE_STATE_NORMAL)
@@ -7860,7 +7861,8 @@ void sde_crtc_static_img_control(struct drm_crtc *crtc,
 		return;
 	}
 
-	if (test_bit(SDE_SYS_CACHE_DISP_1, sde_kms->catalog->sde_sys_cache_type_map)) {
+	if (test_bit(SDE_SYS_CACHE_DISP_1, sde_kms->catalog->sde_sys_cache_type_map) &&
+			!test_bit(SDE_FEATURE_SYS_CACHE_STALING, sde_kms->catalog->features)) {
 		if (state == CACHE_STATE_FRAME_WRITE)
 			sde_crtc->cache_type = (sde_crtc->cache_type == SDE_SYS_CACHE_DISP) ?
 					SDE_SYS_CACHE_DISP_1 : SDE_SYS_CACHE_DISP;

msm/sde/sde_encoder_phys_wb.c

@@ -1319,12 +1319,15 @@ static void _sde_encoder_phys_wb_setup_sys_cache(struct sde_encoder_phys *phys_e
 	if (phys_enc->in_clone_mode) {
 		/* toggle system cache SCID between consecutive CWB writes */
 		if (test_bit(SDE_SYS_CACHE_DISP_1, hw_wb->catalog->sde_sys_cache_type_map)
-				&& cfg->type == SDE_SYS_CACHE_DISP) {
+				&& cfg->type == SDE_SYS_CACHE_DISP &&
+				!test_bit(SDE_FEATURE_SYS_CACHE_STALING,
+						hw_wb->catalog->features)) {
 			cache_wr_type = SDE_SYS_CACHE_DISP_1;
 			cache_rd_type = SDE_SYS_CACHE_DISP_1;
 		} else {
 			cache_wr_type = SDE_SYS_CACHE_DISP;
 			cache_rd_type = SDE_SYS_CACHE_DISP;
+			sde_core_perf_llcc_stale_frame(&sde_crtc->base, cache_wr_type);
 		}
 	} else {
 		cache_rd_type = SDE_SYS_CACHE_DISP_WB;

msm/sde/sde_hw_catalog.c

@@ -3688,6 +3688,8 @@ static int sde_cache_parse_dt(struct device_node *np,
 		sc_cfg->llcc_uid = usecase_id;
 		sc_cfg->llcc_scid = llcc_get_slice_id(slice);
 		sc_cfg->llcc_slice_size = llcc_get_slice_size(slice);
+		sde_core_perf_llcc_stale_configure(sde_cfg, slice);
+
 		SDE_DEBUG("img cache:%d usecase_id:%d, scid:%d slice_size:%zu kb\n",
 				i, usecase_id, sc_cfg->llcc_scid, sc_cfg->llcc_slice_size);
 		llcc_slice_putd(slice);
@@ -5388,6 +5390,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		set_bit(SDE_FEATURE_TRUSTED_VM, sde_cfg->features);
 		set_bit(SDE_SYS_CACHE_DISP, sde_cfg->sde_sys_cache_type_map);
 		set_bit(SDE_SYS_CACHE_DISP_WB, sde_cfg->sde_sys_cache_type_map);
+		set_bit(SDE_FEATURE_SYS_CACHE_NSE, sde_cfg->features);
+		set_bit(SDE_FEATURE_SYS_CACHE_STALING, sde_cfg->features);
 		set_bit(SDE_FEATURE_WB_ROTATION, sde_cfg->features);
 		sde_cfg->allowed_dsc_reservation_switch = SDE_DP_DSC_RESERVATION_SWITCH;
 		sde_cfg->autorefresh_disable_seq = AUTOREFRESH_DISABLE_SEQ2;

msm/sde/sde_hw_catalog.h

@@ -769,6 +769,7 @@ enum {
  * @SDE_FEATURE_VBIF_CLK_SPLIT VBIF clock split supported
  * @SDE_FEATURE_CTL_DONE       Support for CTL DONE irq
  * @SDE_FEATURE_SYS_CACHE_NSE  Support for no-self-evict feature
+ * @SDE_FEATURE_SYS_CACHE_STALING  Support for sys cache staling feature
  * @SDE_FEATURE_HW_FENCE_IPCC  HW fence supports ipcc signaling in dpu
  * @SDE_FEATURE_EMULATED_ENV   Emulated environment supported
  * @SDE_FEATURE_UCSC_SUPPORTED  UCSC pipe format supported
@@ -814,6 +815,7 @@ enum sde_mdss_features {
 	SDE_FEATURE_VBIF_CLK_SPLIT,
 	SDE_FEATURE_CTL_DONE,
 	SDE_FEATURE_SYS_CACHE_NSE,
+	SDE_FEATURE_SYS_CACHE_STALING,
 	SDE_FEATURE_HW_FENCE_IPCC,
 	SDE_FEATURE_EMULATED_ENV,
 	SDE_FEATURE_UCSC_SUPPORTED,