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disp: msm: sde: use common naming for version/revision in catalog

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Align the HW catalog to use common naming amongst the "revision"
and "version" structure members.

Change-Id: Ib6c81aee6cb49208b0699db4a75b4eb9dc79e800
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
This commit is contained in:
Steve Cohen
2021-04-07 23:07:29 -04:00
committed by Jeykumar Sankaran
parent 7f0c843da4
commit a683fba2e8
25 changed files with 95 additions and 110 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
msm/sde/sde_crtc.c
View File

@@ -5671,7 +5671,7 @@ static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info,
{
sde_kms_info_reset(info);
sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion);
sde_kms_info_add_keyint(info, "hw_version", catalog->hw_rev);
sde_kms_info_add_keyint(info, "max_linewidth",
catalog->max_mixer_width);
sde_kms_info_add_keyint(info, "max_blendstages",
@@ -5684,9 +5684,8 @@ static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info,
if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3LITE)
sde_kms_info_add_keystr(info, "qseed_type", "qseed3lite");
if (catalog->ubwc_version) {
sde_kms_info_add_keyint(info, "UBWC version",
catalog->ubwc_version);
if (catalog->ubwc_rev) {
sde_kms_info_add_keyint(info, "UBWC version", catalog->ubwc_rev);
sde_kms_info_add_keyint(info, "UBWC macrotile_mode",
catalog->macrotile_mode);
sde_kms_info_add_keyint(info, "UBWC highest banking bit",
@@ -5760,9 +5759,8 @@ static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info,
sde_kms_info_add_keyint(info, "sec_ui_blendstage",
catalog->sui_supported_blendstage);
if (catalog->ubwc_bw_calc_version)
sde_kms_info_add_keyint(info, "ubwc_bw_calc_ver",
catalog->ubwc_bw_calc_version);
if (catalog->ubwc_bw_calc_rev)
sde_kms_info_add_keyint(info, "ubwc_bw_calc_ver", catalog->ubwc_bw_calc_rev);
}
/**

42
msm/sde/sde_hw_catalog.c
View File

@@ -1716,7 +1716,7 @@ static void _sde_sspp_setup_cursor(struct sde_mdss_cfg *sde_cfg,
struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
struct sde_prop_value *prop_value, u32 *cursor_count)
{
if (!IS_SDE_MAJOR_MINOR_SAME(sde_cfg->hwversion, SDE_HW_VER_300))
if (!IS_SDE_MAJOR_MINOR_SAME(sde_cfg->hw_rev, SDE_HW_VER_300))
SDE_ERROR("invalid sspp type %d, xin id %d\n",
sspp->type, sspp->xin_id);
set_bit(SDE_SSPP_CURSOR, &sspp->features);
@@ -1846,7 +1846,7 @@ static int _sde_sspp_setup_dmas(struct device_node *np,
DMA_DGM_INVERSE_PMA, 0)) {
set_bit(SDE_SSPP_DGM_INVERSE_PMA,
&sspp->features);
if (sde_cfg->hwversion >= SDE_HW_VER_810)
if (sde_cfg->hw_rev >= SDE_HW_VER_810)
sblk->unmult_offset[j] = SDE_DGM_UNMULT_2 + j*0x1000;
else
sblk->unmult_offset[j] = SDE_DGM_UNMULT + j*0x1000;
@@ -2121,8 +2121,7 @@ static int sde_ctl_parse_dt(struct device_node *np,
set_bit(SDE_CTL_ACTIVE_CFG, &ctl->features);
if (SDE_UIDLE_MAJOR(sde_cfg->uidle_cfg.uidle_rev))
set_bit(SDE_CTL_UIDLE, &ctl->features);
if (SDE_HW_MAJOR(sde_cfg->hwversion) >=
SDE_HW_MAJOR(SDE_HW_VER_700))
if (SDE_HW_MAJOR(sde_cfg->hw_rev) >= SDE_HW_MAJOR(SDE_HW_VER_700))
set_bit(SDE_CTL_UNIFIED_DSPP_FLUSH, &ctl->features);
}
@@ -2444,16 +2443,13 @@ static int sde_intf_parse_dt(struct device_node *np,
set_bit(SDE_INTF_TE, &intf->features);
}
if (SDE_HW_MAJOR(sde_cfg->hwversion) >=
SDE_HW_MAJOR(SDE_HW_VER_500))
if (SDE_HW_MAJOR(sde_cfg->hw_rev) >= SDE_HW_MAJOR(SDE_HW_VER_500))
set_bit(SDE_INTF_STATUS, &intf->features);
if (SDE_HW_MAJOR(sde_cfg->hwversion) >=
SDE_HW_MAJOR(SDE_HW_VER_700))
if (SDE_HW_MAJOR(sde_cfg->hw_rev) >= SDE_HW_MAJOR(SDE_HW_VER_700))
set_bit(SDE_INTF_TE_ALIGN_VSYNC, &intf->features);
if (SDE_HW_MAJOR(sde_cfg->hwversion) >=
SDE_HW_MAJOR(SDE_HW_VER_810)) {
if (SDE_HW_MAJOR(sde_cfg->hw_rev) >= SDE_HW_MAJOR(SDE_HW_VER_810)) {
set_bit(SDE_INTF_WD_TIMER, &intf->features);
set_bit(SDE_INTF_RESET_COUNTER, &intf->features);
set_bit(SDE_INTF_VSYNC_TIMESTAMP, &intf->features);
@@ -2500,7 +2496,7 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
if (rc)
goto end;
major_version = SDE_HW_MAJOR(sde_cfg->hwversion);
major_version = SDE_HW_MAJOR(sde_cfg->hw_rev);
for (i = 0; i < off_count; i++) {
wb = sde_cfg->wb + i;
sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
@@ -2526,8 +2522,7 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
goto end;
}
if (IS_SDE_MAJOR_MINOR_SAME((sde_cfg->hwversion),
SDE_HW_VER_170))
if (IS_SDE_MAJOR_MINOR_SAME((sde_cfg->hw_rev), SDE_HW_VER_170))
wb->vbif_idx = VBIF_NRT;
else
wb->vbif_idx = VBIF_RT;
@@ -3805,7 +3800,7 @@ static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
if (rc)
goto end;
major_version = SDE_HW_MAJOR(sde_cfg->hwversion);
major_version = SDE_HW_MAJOR(sde_cfg->hw_rev);
for (i = 0; i < off_count; i++) {
pp = sde_cfg->pingpong + i;
sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
@@ -3927,7 +3922,7 @@ static void _sde_top_parse_dt_helper(struct sde_mdss_cfg *cfg,
PROP_VALUE_ACCESS(props->values, MIXER_BLEND, 0) :
DEFAULT_SDE_MIXER_BLENDSTAGES;
cfg->ubwc_version = props->exists[UBWC_VERSION] ?
cfg->ubwc_rev = props->exists[UBWC_VERSION] ?
SDE_HW_UBWC_VER(PROP_VALUE_ACCESS(props->values,
UBWC_VERSION, 0)) : DEFAULT_SDE_UBWC_NONE;
@@ -3948,8 +3943,7 @@ static void _sde_top_parse_dt_helper(struct sde_mdss_cfg *cfg,
PROP_VALUE_ACCESS(props->values, MACROTILE_MODE, 0) :
DEFAULT_SDE_UBWC_MACROTILE_MODE;
cfg->ubwc_bw_calc_version =
PROP_VALUE_ACCESS(props->values, UBWC_BW_CALC_VERSION, 0);
cfg->ubwc_bw_calc_rev = PROP_VALUE_ACCESS(props->values, UBWC_BW_CALC_VERSION, 0);
cfg->mdp[0].ubwc_static = props->exists[UBWC_STATIC] ?
PROP_VALUE_ACCESS(props->values, UBWC_STATIC, 0) :
@@ -3984,8 +3978,7 @@ static void _sde_top_parse_dt_helper(struct sde_mdss_cfg *cfg,
PIPE_ORDER_VERSION, 0);
if (PROP_VALUE_ACCESS(props->values, BASE_LAYER, 0))
set_bit(SDE_FEATURE_BASE_LAYER, cfg->features);
cfg->qseed_hw_version = PROP_VALUE_ACCESS(props->values,
QSEED_HW_VERSION, 0);
cfg->qseed_hw_rev = PROP_VALUE_ACCESS(props->values, QSEED_HW_VERSION, 0);
cfg->trusted_vm_env = PROP_VALUE_ACCESS(props->values, TRUSTED_VM_ENV, 0);
cfg->max_trusted_vm_displays = PROP_VALUE_ACCESS(props->values,
MAX_TRUSTED_VM_DISPLAYS, 0);
@@ -4041,7 +4034,7 @@ static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)
_sde_top_parse_dt_helper(cfg, props);
major_version = SDE_HW_MAJOR(cfg->hwversion);
major_version = SDE_HW_MAJOR(cfg->hw_rev);
if (major_version < SDE_HW_MAJOR(SDE_HW_VER_500))
set_bit(SDE_MDP_VSYNC_SEL, &cfg->mdp[0].features);
else if (major_version < SDE_HW_MAJOR(SDE_HW_VER_810))
@@ -5238,10 +5231,9 @@ static int sde_hw_ver_parse_dt(struct drm_device *dev, struct device_node *np,
goto end;
if (prop_exists[SDE_HW_VERSION])
cfg->hwversion = PROP_VALUE_ACCESS(prop_value,
SDE_HW_VERSION, 0);
cfg->hw_rev = PROP_VALUE_ACCESS(prop_value, SDE_HW_VERSION, 0);
else
cfg->hwversion = sde_kms_get_hw_version(dev);
cfg->hw_rev = sde_kms_get_hw_version(dev);
end:
kfree(prop_value);
@@ -5270,7 +5262,7 @@ struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev)
if (rc)
goto end;
rc = _sde_hardware_pre_caps(sde_cfg, sde_cfg->hwversion);
rc = _sde_hardware_pre_caps(sde_cfg, sde_cfg->hw_rev);
if (rc)
goto end;
@@ -5366,7 +5358,7 @@ struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev)
if (rc)
goto end;
rc = _sde_hardware_post_caps(sde_cfg, sde_cfg->hwversion);
rc = _sde_hardware_post_caps(sde_cfg, sde_cfg->hw_rev);
if (rc)
goto end;

18
msm/sde/sde_hw_catalog.h
View File

@@ -1557,11 +1557,11 @@ struct sde_perf_cfg {
* this HW version. Contains number of instances,
* register offsets, capabilities of all the MDSS HW sub-blocks.
*
* @hwversion MDSS HW version
* @ubwc_version UBWC feature version (0x0 for not supported)
* @ubwc_bw_calc_version indicates how UBWC BW has to be calculated
* @hw_rev MDSS HW revision
* @ubwc_rev UBWC feature version (0x0 for not supported)
* @ubwc_bw_calc_rev indicates how UBWC BW has to be calculated
* @qseed_sw_lib_rev qseed SW library version
* @qseed_hw_version qseed HW block version
* @qseed_hw_rev qseed HW block version
* @smart_dma_rev smartDMA block version
* @ctl_rev control path block version
* @ts_prefill_rev prefill traffic shaper feature revision
@@ -1651,12 +1651,12 @@ struct sde_perf_cfg {
* @inline_rot_restricted_formats restricted formats for inline rotation
*/
struct sde_mdss_cfg {
/* Versions */
u32 hwversion;
u32 ubwc_version;
u32 ubwc_bw_calc_version;
/* Block Revisions */
u32 hw_rev;
u32 ubwc_rev;
u32 ubwc_bw_calc_rev;
u32 qseed_sw_lib_rev;
u32 qseed_hw_version;
u32 qseed_hw_rev;
u32 smart_dma_rev;
u32 ctl_rev;
u32 ts_prefill_rev;

4
msm/sde/sde_hw_cdm.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
#include "sde_hw_mdss.h"
@@ -77,7 +77,7 @@ static struct sde_cdm_cfg *_cdm_offset(enum sde_cdm cdm,
b->base_off = addr;
b->blk_off = m->cdm[i].base;
b->length = m->cdm[i].len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_CDM;
return &m->cdm[i];
}

2
msm/sde/sde_hw_ctl.c
View File

@@ -283,7 +283,7 @@ static struct sde_ctl_cfg *_ctl_offset(enum sde_ctl ctl,
b->base_off = addr;
b->blk_off = m->ctl[i].base;
b->length = m->ctl[i].len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_CTL;
return &m->ctl[i];
}

8
msm/sde/sde_hw_ds.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
#include "sde_hw_ds.h"
@@ -71,7 +71,7 @@ static struct sde_ds_cfg *_ds_offset(enum sde_ds ds,
b->base_off = addr;
b->blk_off = m->ds[i].top->base;
b->length = m->ds[i].top->len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_DS;
return &m->ds[i];
}
@@ -112,8 +112,8 @@ struct sde_hw_ds *sde_hw_ds_init(enum sde_ds idx,
hw_ds->scl = cfg;
_setup_ds_ops(&hw_ds->ops, hw_ds->scl->features);
if (m->qseed_hw_version)
hw_ds->scl->version = m->qseed_hw_version;
if (m->qseed_hw_rev)
hw_ds->scl->version = m->qseed_hw_rev;
rc = sde_hw_blk_init(&hw_ds->base, SDE_HW_BLK_DS, idx, &sde_hw_ops);
if (rc) {

4
msm/sde/sde_hw_dsc.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
#include "sde_hw_mdss.h"
@@ -193,7 +193,7 @@ static struct sde_dsc_cfg *_dsc_offset(enum sde_dsc dsc,
b->base_off = addr;
b->blk_off = m->dsc[i].base;
b->length = m->dsc[i].len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_DSC;
return &m->dsc[i];
}

4
msm/sde/sde_hw_dspp.c
View File

@@ -31,7 +31,7 @@ static struct sde_dspp_cfg *_dspp_offset(enum sde_dspp dspp,
b->base_off = addr;
b->blk_off = m->dspp[i].base;
b->length = m->dspp[i].len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_DSPP;
return &m->dspp[i];
}
@@ -407,7 +407,7 @@ struct sde_hw_dspp *sde_hw_dspp_init(enum sde_dspp idx,
c->hw_top.base_off = addr;
c->hw_top.blk_off = m->dspp_top.base;
c->hw_top.length = m->dspp_top.len;
c->hw_top.hwversion = m->hwversion;
c->hw_top.hw_rev = m->hw_rev;
c->hw_top.log_mask = SDE_DBG_MASK_DSPP;
/* Assign ops */

2
msm/sde/sde_hw_interrupts.c
View File

@@ -900,7 +900,7 @@ static struct sde_mdss_base_cfg *__intr_offset(struct sde_mdss_cfg *m,
hw->base_off = addr;
hw->blk_off = m->mdss[0].base;
hw->hwversion = m->hwversion;
hw->hw_rev = m->hw_rev;
return &m->mdss[0];
}

9
msm/sde/sde_hw_intf.c
View File

@@ -103,7 +103,7 @@ static struct sde_intf_cfg *_intf_offset(enum sde_intf intf,
b->base_off = addr;
b->blk_off = m->intf[i].base;
b->length = m->intf[i].len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_INTF;
return &m->intf[i];
}
@@ -202,11 +202,8 @@ static u32 sde_hw_intf_get_avr_status(struct sde_hw_intf *ctx)
static inline void _check_and_set_comp_bit(struct sde_hw_intf *ctx,
bool dsc_4hs_merge, bool compression_en, u32 *intf_cfg2)
{
if (((SDE_HW_MAJOR(ctx->mdss->hwversion) >=
SDE_HW_MAJOR(SDE_HW_VER_700)) &&
compression_en) ||
(IS_SDE_MAJOR_SAME(ctx->mdss->hwversion,
SDE_HW_VER_600) && dsc_4hs_merge))
if (((SDE_HW_MAJOR(ctx->mdss->hw_rev) >= SDE_HW_MAJOR(SDE_HW_VER_700)) && compression_en)
|| (IS_SDE_MAJOR_SAME(ctx->mdss->hw_rev, SDE_HW_VER_600) && dsc_4hs_merge))
(*intf_cfg2) |= BIT(12);
else if (!compression_en)
(*intf_cfg2) &= ~BIT(12);

2
msm/sde/sde_hw_lm.c
View File

@@ -45,7 +45,7 @@ static struct sde_lm_cfg *_lm_offset(enum sde_lm mixer,
b->base_off = addr;
b->blk_off = m->mixer[i].base;
b->length = m->mixer[i].len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_LM;
return &m->mixer[i];
}

4
msm/sde/sde_hw_pingpong.c
View File

@@ -52,7 +52,7 @@ static struct sde_merge_3d_cfg *_merge_3d_offset(enum sde_merge_3d idx,
b->base_off = addr;
b->blk_off = m->merge_3d[i].base;
b->length = m->merge_3d[i].len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_PINGPONG;
return &m->merge_3d[i];
}
@@ -146,7 +146,7 @@ static struct sde_pingpong_cfg *_pingpong_offset(enum sde_pingpong pp,
b->base_off = addr;
b->blk_off = m->pingpong[i].base;
b->length = m->pingpong[i].len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_PINGPONG;
return &m->pingpong[i];
}

4
msm/sde/sde_hw_qdss.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
*/
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
@@ -26,7 +26,7 @@ static struct sde_qdss_cfg *_qdss_offset(enum sde_qdss qdss,
b->base_off = addr;
b->blk_off = m->qdss[i].base;
b->length = m->qdss[i].len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_QDSS;
return &m->qdss[i];
}

8
msm/sde/sde_hw_reg_dma_v1.c
View File

@@ -31,7 +31,7 @@
break; \
(hw).base_off = (reg_dma)->addr; \
(hw).blk_off = (reg_dma)->caps->reg_dma_blks[(i)].base; \
(hw).hwversion = (reg_dma)->caps->version; \
(hw).hw_rev = (reg_dma)->caps->version; \
(hw).log_mask = SDE_DBG_MASK_REGDMA; \
} while (0)
@@ -677,7 +677,7 @@ static int write_kick_off_v1(struct sde_reg_dma_kickoff_cfg *cfg)
else if (cfg->dma_type == REG_DMA_TYPE_SB)
SET_UP_REG_DMA_REG(hw, reg_dma, REG_DMA_TYPE_SB);
if (hw.hwversion == 0) {
if (hw.hw_rev == 0) {
DRM_ERROR("DMA type %d is unsupported\n", cfg->dma_type);
return -EOPNOTSUPP;
}
@@ -964,7 +964,7 @@ int reset_v1(struct sde_hw_ctl *ctl)
for (k = 0; k < REG_DMA_TYPE_MAX; k++) {
memset(&hw, 0, sizeof(hw));
SET_UP_REG_DMA_REG(hw, reg_dma, k);
if (hw.hwversion == 0)
if (hw.hw_rev == 0)
continue;
SDE_REG_WRITE(&hw, reg_dma_opmode_offset, BIT(0));
@@ -1263,7 +1263,7 @@ static void dump_regs_v1(void)
for (k = 0; k < REG_DMA_TYPE_MAX; k++) {
memset(&hw, 0, sizeof(hw));
SET_UP_REG_DMA_REG(hw, reg_dma, k);
if (hw.hwversion == 0)
if (hw.hw_rev == 0)
continue;
for (i = 0; i < reg_dma_register_count; i++) {

17
msm/sde/sde_hw_sspp.c
View File

@@ -320,20 +320,19 @@ static void sde_hw_sspp_setup_ubwc(struct sde_hw_pipe *ctx, struct sde_hw_blk_re
else
ubwc_ctrl_off = SSPP_UBWC_STATIC_CTRL_REC1;
if (IS_UBWC_40_SUPPORTED(ctx->catalog->ubwc_version)) {
SDE_REG_WRITE(c, ubwc_ctrl_off,
SDE_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
} else if (IS_UBWC_30_SUPPORTED(ctx->catalog->ubwc_version)) {
if (IS_UBWC_40_SUPPORTED(ctx->catalog->ubwc_rev)) {
SDE_REG_WRITE(c, ubwc_ctrl_off, SDE_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
} else if (IS_UBWC_30_SUPPORTED(ctx->catalog->ubwc_rev)) {
color_en_mask = const_color_en ? BIT(30) : 0;
SDE_REG_WRITE(c, ubwc_ctrl_off,
color_en_mask | (ctx->mdp->ubwc_swizzle) |
(ctx->mdp->highest_bank_bit << 4));
} else if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_version)) {
} else if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_rev)) {
alpha_en_mask = const_alpha_en ? BIT(31) : 0;
SDE_REG_WRITE(c, ubwc_ctrl_off,
alpha_en_mask | (ctx->mdp->ubwc_swizzle) |
(ctx->mdp->highest_bank_bit << 4));
} else if (IS_UBWC_10_SUPPORTED(ctx->catalog->ubwc_version)) {
} else if (IS_UBWC_10_SUPPORTED(ctx->catalog->ubwc_rev)) {
alpha_en_mask = const_alpha_en ? BIT(31) : 0;
SDE_REG_WRITE(c, ubwc_ctrl_off,
alpha_en_mask | (ctx->mdp->ubwc_swizzle & 0x1) |
@@ -1490,7 +1489,7 @@ static struct sde_sspp_cfg *_sspp_offset(enum sde_sspp sspp,
b->base_off = addr;
b->blk_off = catalog->sspp[i].base;
b->length = catalog->sspp[i].len;
b->hwversion = catalog->hwversion;
b->hw_rev = catalog->hw_rev;
b->log_mask = SDE_DBG_MASK_SSPP;
/* Only shallow copy is needed */
@@ -1541,9 +1540,9 @@ struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx,
_setup_layer_ops(hw_pipe, hw_pipe->cap->features,
hw_pipe->cap->perf_features, is_virtual_pipe);
if (catalog->qseed_hw_version)
if (catalog->qseed_hw_rev)
sde_init_scaler_blk(&hw_pipe->cap->sblk->scaler_blk,
catalog->qseed_hw_version);
catalog->qseed_hw_rev);
rc = sde_hw_blk_init(&hw_pipe->base, SDE_HW_BLK_SSPP, idx, &sde_hw_ops);
if (rc) {

22
msm/sde/sde_hw_top.c
View File

@@ -312,7 +312,7 @@ static void sde_hw_setup_vsync_source_v1(struct sde_hw_mdp *mdp,
void sde_hw_reset_ubwc(struct sde_hw_mdp *mdp, struct sde_mdss_cfg *m)
{
struct sde_hw_blk_reg_map c;
u32 ubwc_version;
u32 ubwc_rev;
if (!mdp || !m)
return;
@@ -320,9 +320,9 @@ void sde_hw_reset_ubwc(struct sde_hw_mdp *mdp, struct sde_mdss_cfg *m)
/* force blk offset to zero to access beginning of register region */
c = mdp->hw;
c.blk_off = 0x0;
ubwc_version = SDE_REG_READ(&c, UBWC_DEC_HW_VERSION);
ubwc_rev = SDE_REG_READ(&c, UBWC_DEC_HW_VERSION);
if (IS_UBWC_40_SUPPORTED(ubwc_version)) {
if (IS_UBWC_40_SUPPORTED(ubwc_rev)) {
u32 ver = 2;
u32 mode = 1;
u32 reg = (m->mdp[0].ubwc_swizzle & 0x7) |
@@ -330,7 +330,7 @@ void sde_hw_reset_ubwc(struct sde_hw_mdp *mdp, struct sde_mdss_cfg *m)
((m->mdp[0].highest_bank_bit & 0x7) << 4) |
((m->macrotile_mode & 0x1) << 12);
if (IS_UBWC_30_SUPPORTED(m->ubwc_version)) {
if (IS_UBWC_30_SUPPORTED(m->ubwc_rev)) {
ver = 1;
mode = 0;
}
@@ -338,22 +338,22 @@ void sde_hw_reset_ubwc(struct sde_hw_mdp *mdp, struct sde_mdss_cfg *m)
SDE_REG_WRITE(&c, UBWC_STATIC, reg);
SDE_REG_WRITE(&c, UBWC_CTRL_2, ver);
SDE_REG_WRITE(&c, UBWC_PREDICTION_MODE, mode);
} else if (IS_UBWC_20_SUPPORTED(ubwc_version)) {
} else if (IS_UBWC_20_SUPPORTED(ubwc_rev)) {
SDE_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static);
} else if (IS_UBWC_30_SUPPORTED(ubwc_version)) {
} else if (IS_UBWC_30_SUPPORTED(ubwc_rev)) {
u32 reg = m->mdp[0].ubwc_static |
(m->mdp[0].ubwc_swizzle & 0x1) |
((m->mdp[0].highest_bank_bit & 0x3) << 4) |
((m->macrotile_mode & 0x1) << 12);
if (IS_UBWC_30_SUPPORTED(m->ubwc_version))
if (IS_UBWC_30_SUPPORTED(m->ubwc_rev))
reg |= BIT(10);
if (IS_UBWC_10_SUPPORTED(m->ubwc_version))
if (IS_UBWC_10_SUPPORTED(m->ubwc_rev))
reg |= BIT(8);
SDE_REG_WRITE(&c, UBWC_STATIC, reg);
} else {
SDE_ERROR("Unsupported UBWC version 0x%08x\n", ubwc_version);
SDE_ERROR("Unsupported UBWC version 0x%08x\n", ubwc_rev);
}
}
@@ -393,7 +393,7 @@ struct sde_hw_sid *sde_hw_sid_init(void __iomem *addr,
c->hw.base_off = addr;
c->hw.blk_off = 0;
c->hw.length = sid_len;
c->hw.hwversion = m->hwversion;
c->hw.hw_rev = m->hw_rev;
c->hw.log_mask = SDE_DBG_MASK_SID;
return c;
@@ -549,7 +549,7 @@ static const struct sde_mdp_cfg *_top_offset(enum sde_mdp mdp,
b->base_off = addr;
b->blk_off = m->mdp[i].base;
b->length = m->mdp[i].len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_TOP;
return &m->mdp[i];
}

6
msm/sde/sde_hw_uidle.c
View File

@@ -49,10 +49,10 @@ static const struct sde_uidle_cfg *_top_offset(enum sde_uidle uidle,
b->base_off = addr;
b->blk_off = m->uidle_cfg.base;
b->length = m->uidle_cfg.len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_UIDLE;
SDE_DEBUG("base:0x%p blk_off:0x%x length:%d hwversion:0x%x\n",
b->base_off, b->blk_off, b->length, b->hwversion);
SDE_DEBUG("base:0x%p blk_off:0x%x length:%d hw_rev:0x%x\n",
b->base_off, b->blk_off, b->length, b->hw_rev);
return &m->uidle_cfg;
}

4
msm/sde/sde_hw_util.h
View File

@@ -27,14 +27,14 @@ struct sde_format_extended;
* @blk_off: pipe offset relative to mdss offset
* @length length of register block offset
* @xin_id xin id
* @hwversion mdss hw version number
* @hw_rev mdss hw revision
*/
struct sde_hw_blk_reg_map {
void __iomem *base_off;
u32 blk_off;
u32 length;
u32 xin_id;
u32 hwversion;
u32 hw_rev;
u32 log_mask;
};

4
msm/sde/sde_hw_vbif.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/iopoll.h>
@@ -279,7 +279,7 @@ static const struct sde_vbif_cfg *_top_offset(enum sde_vbif vbif,
b->base_off = addr;
b->blk_off = m->vbif[i].base;
b->length = m->vbif[i].len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_VBIF;
return &m->vbif[i];
}

2
msm/sde/sde_hw_vdc.c
View File

@@ -368,7 +368,7 @@ static struct sde_vdc_cfg *_vdc_offset(enum sde_vdc vdc,
b->base_off = addr;
b->blk_off = m->vdc[i].base;
b->length = m->vdc[i].len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_VDC;
return &m->vdc[i];
}

12
msm/sde/sde_hw_wb.c
View File

@@ -68,7 +68,7 @@ static struct sde_wb_cfg *_wb_offset(enum sde_wb wb,
b->base_off = addr;
b->blk_off = m->wb[i].base;
b->length = m->wb[i].len;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_WB;
return &m->wb[i];
}
@@ -89,7 +89,7 @@ static void _sde_hw_cwb_ctrl_init(struct sde_mdss_cfg *m,
b->base_off = addr;
b->blk_off = m->cwb_blk_off;
b->length = 0x20;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_WB;
for (i = 0; i < m->pingpong_count; i++) {
@@ -114,7 +114,7 @@ static void _sde_hw_dcwb_ctrl_init(struct sde_mdss_cfg *m,
b->base_off = addr;
b->blk_off = m->cwb_blk_off;
b->length = 0x20;
b->hwversion = m->hwversion;
b->hw_rev = m->hw_rev;
b->log_mask = SDE_DBG_MASK_WB;
for (i = 0; i < m->dcwb_count; i++) {
@@ -146,7 +146,7 @@ static void _sde_hw_dcwb_pp_ctrl_init(struct sde_mdss_cfg *m,
hw_wb->dcwb_pp_hw[dcwb_pp_count].hw.base_off = addr;
hw_wb->dcwb_pp_hw[dcwb_pp_count].hw.blk_off = pp_blk->base;
hw_wb->dcwb_pp_hw[dcwb_pp_count].hw.length = pp_blk->len;
hw_wb->dcwb_pp_hw[dcwb_pp_count].hw.hwversion = m->hwversion;
hw_wb->dcwb_pp_hw[dcwb_pp_count].hw.hw_rev = m->hw_rev;
hw_wb->dcwb_pp_hw[dcwb_pp_count].hw.log_mask = SDE_DBG_MASK_WB;
} else {
DRM_ERROR("Invalid dcwb pp count %d more than %d",
@@ -228,11 +228,11 @@ static void sde_hw_wb_setup_format(struct sde_hw_wb *ctx,
write_config |= (ctx->mdp->highest_bank_bit << 8);
if (fmt->base.pixel_format == DRM_FORMAT_RGB565)
write_config |= 0x8;
if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_version))
if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_rev))
SDE_REG_WRITE(c, WB_UBWC_STATIC_CTRL,
(ctx->mdp->ubwc_swizzle << 0) |
(ctx->mdp->highest_bank_bit << 4));
if (IS_UBWC_10_SUPPORTED(ctx->catalog->ubwc_version))
if (IS_UBWC_10_SUPPORTED(ctx->catalog->ubwc_rev))
SDE_REG_WRITE(c, WB_UBWC_STATIC_CTRL,
(ctx->mdp->ubwc_swizzle << 0) |
BIT(8) |

2
msm/sde/sde_kms.c
View File

@@ -4624,7 +4624,7 @@ static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
sde_kms->catalog = NULL;
goto power_error;
}
sde_kms->core_rev = sde_kms->catalog->hwversion;
sde_kms->core_rev = sde_kms->catalog->hw_rev;
pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);

7
msm/sde/sde_plane.c
View File

@@ -2611,7 +2611,7 @@ static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
dst.x, dst.y, dst.w, dst.h);
ret = -EINVAL;
} else if (SDE_FORMAT_IS_UBWC(fmt) &&
!psde->catalog->ubwc_version) {
!psde->catalog->ubwc_rev) {
SDE_ERROR_PLANE(psde, "ubwc not supported\n");
ret = -EINVAL;
}
@@ -3685,9 +3685,8 @@ static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
sde_kms_info_stop(info);
}
if (psde->pipe_hw && catalog->qseed_hw_version)
sde_kms_info_add_keyint(info, "scaler_step_ver",
catalog->qseed_hw_version);
if (psde->pipe_hw && catalog->qseed_hw_rev)
sde_kms_info_add_keyint(info, "scaler_step_ver", catalog->qseed_hw_rev);
sde_kms_info_add_keyint(info, "max_linewidth",
psde->pipe_sblk->maxlinewidth);

2
msm/sde_dbg.c
View File

@@ -2312,7 +2312,7 @@ static void _sde_dbg_debugfs_destroy(void)
{
}
void sde_dbg_init_dbg_buses(u32 hwversion)
void sde_dbg_init_dbg_buses(u32 hw_rev)
{
static struct sde_dbg_base *dbg = &sde_dbg_base;

4
msm/sde_dbg.h
View File

@@ -368,9 +368,9 @@ ssize_t sde_evtlog_dump_to_buffer(struct sde_dbg_evtlog *evtlog,
/**
* sde_dbg_init_dbg_buses - initialize debug bus dumping support for the chipset
* @hwversion: Chipset revision
* @hw_rev: Chipset revision
*/
void sde_dbg_init_dbg_buses(u32 hwversion);
void sde_dbg_init_dbg_buses(u32 hw_rev);
/**
* sde_dbg_init - initialize global sde debug facilities: evtlog, regdump