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msm: camera: cpas: Fix TCSR register programming

Program TCSR_CAMERA_HF_SF_ARES_GLITCH_MASK to ignore
erroneous signals.

CRs-Fixed: 2545751
Change-Id: Ie638136d364372b7a8309af1d9656a8c8b7772fc
Signed-off-by: Trishansh Bhardwaj <[email protected]>
Trishansh Bhardwaj 5 年 前
コミット
a62a432522

+ 1 - 1
drivers/cam_cpas/cam_cpas_hw.c

@@ -44,7 +44,7 @@ int cam_cpas_util_reg_update(struct cam_hw_info *cpas_hw,
 		value = reg_info->value;
 	}
 
-	CAM_DBG(CAM_CPAS, "Base[%d] Offset[0x%8x] Value[0x%8x]",
+	CAM_DBG(CAM_CPAS, "Base[%d] Offset[0x%08x] Value[0x%08x]",
 		reg_base, reg_info->offset, value);
 
 	cam_io_w_mb(value, soc_info->reg_map[reg_base_index].mem_base +

+ 11 - 0
drivers/cam_cpas/cpas_top/cam_cpastop_hw.c

@@ -7,6 +7,8 @@
 #include <linux/timer.h>
 #include <linux/slab.h>
 
+#include <soc/qcom/scm.h>
+
 #include "cam_cpas_hw_intf.h"
 #include "cam_cpas_hw.h"
 #include "cam_cpastop_hw.h"
@@ -513,6 +515,10 @@ done:
 static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw)
 {
 	int i;
+	struct cam_cpas_hw_errata_wa_list *errata_wa_list =
+		camnoc_info->errata_wa_list;
+	struct cam_cpas_hw_errata_wa *errata_wa =
+		&errata_wa_list->tcsr_camera_hf_sf_ares_glitch;
 
 	cam_cpastop_reset_irq(cpas_hw);
 	for (i = 0; i < camnoc_info->specific_size; i++) {
@@ -534,6 +540,11 @@ static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw)
 		}
 	}
 
+	if (errata_wa->enable) {
+		scm_io_write(errata_wa->data.reg_info.offset,
+			errata_wa->data.reg_info.value);
+	}
+
 	return 0;
 }
 

+ 3 - 1
drivers/cam_cpas/cpas_top/cam_cpastop_hw.h

@@ -208,10 +208,12 @@ struct cam_cpas_hw_errata_wa {
  *
  * @camnoc_flush_slave_pending_trans: Errata workaround info for flushing
  *         camnoc slave pending transactions before turning off CPAS_TOP gdsc
- *
+ * @tcsr_camera_hf_sf_ares_glitch: Errata workaround info from ignoring
+ *         erroneous signals at camera start
  */
 struct cam_cpas_hw_errata_wa_list {
 	struct cam_cpas_hw_errata_wa camnoc_flush_slave_pending_trans;
+	struct cam_cpas_hw_errata_wa tcsr_camera_hf_sf_ares_glitch;
 };
 
 /**

+ 11 - 0
drivers/cam_cpas/cpas_top/cpastop_v175_130.h

@@ -747,6 +747,17 @@ static struct cam_cpas_hw_errata_wa_list cam175_cpas130_errata_wa_list = {
 			.value = 0, /* expected to be 0 */
 		},
 	},
+	/* TZ owned register */
+	.tcsr_camera_hf_sf_ares_glitch = {
+		.enable = true,
+		.data.reg_info = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			/* TCSR_CAMERA_HF_SF_ARES_GLITCH_MASK */
+			.offset = 0x01FCA08C,
+			.value = 0x4, /* set bit[2] to 1 */
+		},
+	},
 };
 
 static struct cam_camnoc_info cam175_cpas130_camnoc_info = {