qcacmn: Hal changes for Umac post reset at host

Hal layer changes to handle Umac post reset
and post reset complete events from firmware.

Change-Id: Ib25427930aab25650731c87b38e2ef7e47ae98d9
CRs-Fixed: 3267222

hal/wifi3.0/be/hal_be_api.h

@@ -33,9 +33,10 @@ RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET))
  *
  * @hal_soc: Opaque HAL SOC handle
  * @reo_params: parameters needed by HAL for REO config
+ * @qref_reset: reset qref
  */
 void hal_reo_setup_generic_be(struct hal_soc *soc,
-			      void *reoparams);
+			      void *reoparams, int qref_reset);
 
 /**
  * hal_rx_msdu_ext_desc_info_get_ptr_be() - Get the msdu extension

hal/wifi3.0/be/hal_be_generic_api.c

@@ -23,6 +23,7 @@
 #include "hal_be_reo.h"
 #include "hal_tx.h"	//HAL_SET_FLD
 #include "hal_be_rx.h"	//HAL_RX_BUF_RBM_GET
+#include "rx_reo_queue_1k.h"
 
 /*
  * The 4 bits REO destination ring value is defined as: 0: TCL
@@ -68,7 +69,8 @@ hal_tx_init_data_ring_be(hal_soc_handle_t hal_soc_hdl,
 {
 }
 
-void hal_reo_setup_generic_be(struct hal_soc *soc, void *reoparams)
+void hal_reo_setup_generic_be(struct hal_soc *soc, void *reoparams,
+			      int qref_reset)
 {
 	uint32_t reg_val;
 	struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
@@ -780,7 +782,7 @@ hal_rx_wbm_rel_buf_paddr_get_be(hal_ring_desc_t rx_desc,
  * hal_unregister_reo_send_cmd_be() - Unregister Reo send command callback.
  * @hal_soc_hdl: HAL soc handle
  *
- * Return: status
+ * Return: None
  */
 static
 void hal_unregister_reo_send_cmd_be(struct hal_soc *hal_soc)
@@ -792,13 +794,109 @@ void hal_unregister_reo_send_cmd_be(struct hal_soc *hal_soc)
  * hal_register_reo_send_cmd_be() - Register Reo send command callback.
  * @hal_soc_hdl: HAL soc handle
  *
- * Return: status
+ * Return: None
  */
 static
 void hal_register_reo_send_cmd_be(struct hal_soc *hal_soc)
 {
 	hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_be;
 }
+
+/**
+ * hal_reset_rx_reo_tid_q_be() - reset the reo tid queue.
+ * @hal_soc_hdl: HAL soc handle
+ * @hw_qdesc_vaddr:start address of the tid queue
+ * @size:size of address pointed by hw_qdesc_vaddr
+ *
+ * Return: None
+ */
+static void
+hal_reset_rx_reo_tid_q_be(struct hal_soc *hal_soc, void *hw_qdesc_vaddr,
+			  uint32_t size)
+{
+	struct rx_reo_queue *hw_qdesc = (struct rx_reo_queue *)hw_qdesc_vaddr;
+	int i;
+
+	if (!hw_qdesc)
+		return;
+
+	hw_qdesc->svld = 0;
+	hw_qdesc->ssn = 0;
+	hw_qdesc->current_index = 0;
+	hw_qdesc->pn_valid = 0;
+	hw_qdesc->pn_31_0 = 0;
+	hw_qdesc->pn_63_32 = 0;
+	hw_qdesc->pn_95_64 = 0;
+	hw_qdesc->pn_127_96 = 0;
+	hw_qdesc->last_rx_enqueue_timestamp = 0;
+	hw_qdesc->last_rx_dequeue_timestamp = 0;
+	hw_qdesc->ptr_to_next_aging_queue_39_32 = 0;
+	hw_qdesc->ptr_to_next_aging_queue_31_0 = 0;
+	hw_qdesc->ptr_to_previous_aging_queue_31_0 = 0;
+	hw_qdesc->ptr_to_previous_aging_queue_39_32 = 0;
+	hw_qdesc->rx_bitmap_31_0 = 0;
+	hw_qdesc->rx_bitmap_63_32 = 0;
+	hw_qdesc->rx_bitmap_95_64 = 0;
+	hw_qdesc->rx_bitmap_127_96 = 0;
+	hw_qdesc->rx_bitmap_159_128 = 0;
+	hw_qdesc->rx_bitmap_191_160 = 0;
+	hw_qdesc->rx_bitmap_223_192 = 0;
+	hw_qdesc->rx_bitmap_255_224 = 0;
+	hw_qdesc->rx_bitmap_287_256 = 0;
+	hw_qdesc->current_msdu_count = 0;
+	hw_qdesc->current_mpdu_count = 0;
+	hw_qdesc->last_sn_reg_index = 0;
+
+	if (size > sizeof(struct rx_reo_queue)) {
+		struct rx_reo_queue_ext *ext_desc;
+		struct rx_reo_queue_1k *kdesc;
+
+		i = ((size - sizeof(struct rx_reo_queue)) /
+				sizeof(struct rx_reo_queue_ext));
+
+		if (i > 10) {
+			i = 10;
+			kdesc = (struct rx_reo_queue_1k *)
+				(hw_qdesc_vaddr + sizeof(struct rx_reo_queue) +
+				 (10 * sizeof(struct rx_reo_queue_ext)));
+
+			kdesc->rx_bitmap_319_288 = 0;
+			kdesc->rx_bitmap_351_320 = 0;
+			kdesc->rx_bitmap_383_352 = 0;
+			kdesc->rx_bitmap_415_384 = 0;
+			kdesc->rx_bitmap_447_416 = 0;
+			kdesc->rx_bitmap_479_448 = 0;
+			kdesc->rx_bitmap_511_480 = 0;
+			kdesc->rx_bitmap_543_512 = 0;
+			kdesc->rx_bitmap_575_544 = 0;
+			kdesc->rx_bitmap_607_576 = 0;
+			kdesc->rx_bitmap_639_608 = 0;
+			kdesc->rx_bitmap_671_640 = 0;
+			kdesc->rx_bitmap_703_672 = 0;
+			kdesc->rx_bitmap_735_704 = 0;
+			kdesc->rx_bitmap_767_736 = 0;
+			kdesc->rx_bitmap_799_768 = 0;
+			kdesc->rx_bitmap_831_800 = 0;
+			kdesc->rx_bitmap_863_832 = 0;
+			kdesc->rx_bitmap_895_864 = 0;
+			kdesc->rx_bitmap_927_896 = 0;
+			kdesc->rx_bitmap_959_928 = 0;
+			kdesc->rx_bitmap_991_960 = 0;
+			kdesc->rx_bitmap_1023_992 = 0;
+		}
+
+		ext_desc = (struct rx_reo_queue_ext *)
+			(hw_qdesc_vaddr + (sizeof(struct rx_reo_queue)));
+
+		while (i > 0) {
+			qdf_mem_zero(&ext_desc->mpdu_link_pointer_0,
+				     (15 * sizeof(struct rx_mpdu_link_ptr)));
+
+			ext_desc++;
+			i--;
+		}
+	}
+}
 #endif
 
 /**
@@ -858,5 +956,6 @@ void hal_hw_txrx_default_ops_attach_be(struct hal_soc *hal_soc)
 	hal_soc->ops->hal_unregister_reo_send_cmd =
 					hal_unregister_reo_send_cmd_be;
 	hal_soc->ops->hal_register_reo_send_cmd = hal_register_reo_send_cmd_be;
+	hal_soc->ops->hal_reset_rx_reo_tid_q = hal_reset_rx_reo_tid_q_be;
 #endif
 }

hal/wifi3.0/be/hal_be_generic_api.h

@@ -2639,17 +2639,21 @@ static void hal_reo_shared_qaddr_setup_be(hal_soc_handle_t hal_soc_hdl)
  * write start addr of MLO and Non MLO table in HW
  *
  * @hal_soc: HAL Soc handle
+ * @qref_reset: reset qref LUT
  *
  * Return: None
  */
-static void hal_reo_shared_qaddr_init_be(hal_soc_handle_t hal_soc_hdl)
+static void hal_reo_shared_qaddr_init_be(hal_soc_handle_t hal_soc_hdl,
+					 int qref_reset)
 {
 	struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
 
-	qdf_mem_zero(hal->reo_qref.mlo_reo_qref_table_vaddr,
+	if (qref_reset) {
-		     REO_QUEUE_REF_ML_TABLE_SIZE);
+		qdf_mem_zero(hal->reo_qref.mlo_reo_qref_table_vaddr,
-	qdf_mem_zero(hal->reo_qref.non_mlo_reo_qref_table_vaddr,
+			     REO_QUEUE_REF_ML_TABLE_SIZE);
-		     REO_QUEUE_REF_NON_ML_TABLE_SIZE);
+		qdf_mem_zero(hal->reo_qref.non_mlo_reo_qref_table_vaddr,
+			     REO_QUEUE_REF_NON_ML_TABLE_SIZE);
+	}
 	/* LUT_BASE0 and BASE1 registers expect upper 32bits of LUT base address
 	 * and lower 8 bits to be 0. Shift the physical address by 8 to plug
 	 * upper 32bits only

hal/wifi3.0/hal_api.h

@@ -1082,6 +1082,7 @@ bool hal_srng_is_near_full_irq_supported(hal_soc_handle_t hal_soc,
  *		same type (staring from 0)
  * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings
  * @ring_params: SRNG ring params in hal_srng_params structure.
+ * @idle_check: Check if ring is idle
 
  * Callers are expected to allocate contiguous ring memory of size
  * 'num_entries * entry_size' bytes and pass the physical and virtual base
@@ -1093,7 +1094,7 @@ bool hal_srng_is_near_full_irq_supported(hal_soc_handle_t hal_soc,
  *		 NULL on failure (if given ring is not available)
  */
 extern void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
-	int mac_id, struct hal_srng_params *ring_params);
+	int mac_id, struct hal_srng_params *ring_params, bool idle_check);
 
 /* Remapping ids of REO rings */
 #define REO_REMAP_TCL 0
@@ -2664,11 +2665,12 @@ uint32_t hal_get_target_type(hal_soc_handle_t hal_soc_hdl);
  * destination ring HW
  * @hal_soc: HAL SOC handle
  * @srng: SRNG ring pointer
+ * @idle_check: Check if ring is idle
  */
 static inline void hal_srng_dst_hw_init(struct hal_soc *hal,
-	struct hal_srng *srng)
+					struct hal_srng *srng, bool idle_check)
 {
-	hal->ops->hal_srng_dst_hw_init(hal, srng);
+	hal->ops->hal_srng_dst_hw_init(hal, srng, idle_check);
 }
 
 /**
@@ -2676,11 +2678,25 @@ static inline void hal_srng_dst_hw_init(struct hal_soc *hal,
  * source ring HW
  * @hal_soc: HAL SOC handle
  * @srng: SRNG ring pointer
+ * @idle_check: Check if ring is idle
  */
 static inline void hal_srng_src_hw_init(struct hal_soc *hal,
-	struct hal_srng *srng)
+					struct hal_srng *srng, bool idle_check)
 {
-	hal->ops->hal_srng_src_hw_init(hal, srng);
+	hal->ops->hal_srng_src_hw_init(hal, srng, idle_check);
+}
+
+/**
+ * hal_srng_hw_disable - Private function to disable SRNG
+ * source ring HW
+ * @hal_soc: HAL SOC handle
+ * @srng: SRNG ring pointer
+ */
+static inline
+void hal_srng_hw_disable(struct hal_soc *hal_soc, struct hal_srng *srng)
+{
+	if (hal_soc->ops->hal_srng_hw_disable)
+		hal_soc->ops->hal_srng_hw_disable(hal_soc, srng);
 }
 
 /**
@@ -2710,13 +2726,14 @@ void hal_get_hw_hptp(hal_soc_handle_t hal_soc_hdl,
  *
  * @hal_soc: Opaque HAL SOC handle
  * @reo_params: parameters needed by HAL for REO config
+ * @qref_reset: reset qref
  */
 static inline void hal_reo_setup(hal_soc_handle_t hal_soc_hdl,
-				 void *reoparams)
+				 void *reoparams, int qref_reset)
 {
 	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
 
-	hal_soc->ops->hal_reo_setup(hal_soc, reoparams);
+	hal_soc->ops->hal_reo_setup(hal_soc, reoparams, qref_reset);
 }
 
 static inline

hal/wifi3.0/hal_generic_api.h

@@ -21,6 +21,9 @@
 
 #include <hal_rx.h>
 
+#define SRNG_ENABLE_BIT 0x40
+#define SRNG_IDLE_STATE_BIT 0x80
+
 /**
  * hal_get_radiotap_he_gi_ltf() - Convert HE ltf and GI value
  * from stats enum to radiotap enum
@@ -177,19 +180,80 @@ static void hal_wbm_idle_lsb_write_confirm(struct hal_srng *srng)
 }
 #endif
 
+#ifdef DP_UMAC_HW_RESET_SUPPORT
 /**
- * hal_srng_src_hw_init - Private function to initialize SRNG
+ * hal_srng_src_hw_write_cons_prefetch_timer() - Write cons prefetch timer reg
+ * @srng: srng handle
+ * @value: value to set
+ *
+ * Return: None
+ */
+static inline
+void hal_srng_src_hw_write_cons_prefetch_timer(struct hal_srng *srng,
+					       uint32_t value)
+{
+	SRNG_SRC_REG_WRITE(srng, CONSUMER_PREFETCH_TIMER, value);
+}
+
+/**
+ * hal_srng_hw_disable_generic - Private function to disable SRNG
  * source ring HW
  * @hal_soc: HAL SOC handle
  * @srng: SRNG ring pointer
  */
 static inline
+void hal_srng_hw_disable_generic(struct hal_soc *hal, struct hal_srng *srng)
+{
+	uint32_t reg_val = 0;
+
+	if (srng->ring_dir == HAL_SRNG_DST_RING) {
+		reg_val = SRNG_DST_REG_READ(srng, MISC) & ~(SRNG_ENABLE_BIT);
+		SRNG_DST_REG_WRITE(srng, MISC, reg_val);
+	} else {
+		reg_val = SRNG_SRC_REG_READ(srng, MISC) & ~(SRNG_ENABLE_BIT);
+		SRNG_SRC_REG_WRITE(srng, MISC, reg_val);
+		srng->prefetch_timer =
+			SRNG_SRC_REG_READ(srng, CONSUMER_PREFETCH_TIMER);
+		hal_srng_src_hw_write_cons_prefetch_timer(srng, 0);
+	}
+}
+#else
+static inline
+void hal_srng_hw_disable_generic(struct hal_soc *hal, struct hal_srng *srng)
+{
+}
+
+static inline
+void hal_srng_src_hw_write_cons_prefetch_timer(struct hal_srng *srng,
+					       uint32_t value)
+{
+}
+#endif
+/**
+ * hal_srng_src_hw_init - Private function to initialize SRNG
+ * source ring HW
+ * @hal_soc: HAL SOC handle
+ * @srng: SRNG ring pointer
+ * @idle_check: Check if ring is idle
+ */
+static inline
 void hal_srng_src_hw_init_generic(struct hal_soc *hal,
-				  struct hal_srng *srng)
+				  struct hal_srng *srng, bool idle_check)
 {
 	uint32_t reg_val = 0;
 	uint64_t tp_addr = 0;
 
+	if (idle_check) {
+		reg_val = SRNG_SRC_REG_READ(srng, MISC);
+		if (!(reg_val & SRNG_IDLE_STATE_BIT)) {
+			hal_err("ring_id %d not in idle state", srng->ring_id);
+			qdf_assert_always(0);
+		}
+
+		hal_srng_src_hw_write_cons_prefetch_timer(srng,
+							  srng->prefetch_timer);
+	}
+
 	hal_debug("hw_init srng %d", srng->ring_id);
 
 	if (srng->flags & HAL_SRNG_MSI_INTR) {
@@ -288,7 +352,7 @@ void hal_srng_src_hw_init_generic(struct hal_soc *hal,
 	 * (when SRNG_ENABLE field for the MISC register is available in fw_api)
 	 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC)
 	 */
-	reg_val |= 0x40;
+	reg_val |= SRNG_ENABLE_BIT;
 
 	SRNG_SRC_REG_WRITE(srng, MISC, reg_val);
 }
@@ -357,14 +421,23 @@ static inline void hal_srng_dst_near_full_int_setup(struct hal_srng *srng)
  * destination ring HW
  * @hal_soc: HAL SOC handle
  * @srng: SRNG ring pointer
+ * @idle_check: Check if ring is idle
  */
 static inline
 void hal_srng_dst_hw_init_generic(struct hal_soc *hal,
-				  struct hal_srng *srng)
+				  struct hal_srng *srng, bool idle_check)
 {
 	uint32_t reg_val = 0;
 	uint64_t hp_addr = 0;
 
+	if (idle_check) {
+		reg_val = SRNG_DST_REG_READ(srng, MISC);
+		if (!(reg_val & SRNG_IDLE_STATE_BIT)) {
+			hal_err("ring_id %d not in idle state", srng->ring_id);
+			qdf_assert_always(0);
+		}
+	}
+
 	hal_debug("hw_init srng %d", srng->ring_id);
 
 	if (srng->flags & HAL_SRNG_MSI_INTR) {
@@ -492,6 +565,10 @@ static inline void hal_srng_hw_reg_offset_init_generic(struct hal_soc *hal_soc)
 					REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0);
 	hw_reg_offset[SRC_CONSUMER_INT_SETUP_IX1] =
 					REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1);
+#ifdef DP_UMAC_HW_RESET_SUPPORT
+	hw_reg_offset[SRC_CONSUMER_PREFETCH_TIMER] =
+				REG_OFFSET(SRC, CONSUMER_PREFETCH_TIMER);
+#endif
 }
 
 #endif /* HAL_GENERIC_API_H_ */

hal/wifi3.0/hal_internal.h

@@ -385,6 +385,9 @@ enum SRNG_REGISTERS {
 	SRC_BASE_MSB,
 	SRC_CONSUMER_INT_SETUP_IX0,
 	SRC_CONSUMER_INT_SETUP_IX1,
+#ifdef DP_UMAC_HW_RESET_SUPPORT
+	SRC_CONSUMER_PREFETCH_TIMER,
+#endif
 	SRNG_REGISTER_MAX,
 };
 
@@ -818,14 +821,18 @@ struct hal_rx_pkt_capture_flags {
 struct hal_hw_txrx_ops {
 	/* init and setup */
 	void (*hal_srng_dst_hw_init)(struct hal_soc *hal,
-				     struct hal_srng *srng);
+				     struct hal_srng *srng, bool idle_check);
 	void (*hal_srng_src_hw_init)(struct hal_soc *hal,
-				     struct hal_srng *srng);
+				     struct hal_srng *srng, bool idle_check);
+
+	void (*hal_srng_hw_disable)(struct hal_soc *hal,
+				    struct hal_srng *srng);
 	void (*hal_get_hw_hptp)(struct hal_soc *hal,
 				hal_ring_handle_t hal_ring_hdl,
 				uint32_t *headp, uint32_t *tailp,
 				uint8_t ring_type);
-	void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams);
+	void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams,
+			      int qref_reset);
 	void (*hal_setup_link_idle_list)(
 				struct hal_soc *hal_soc,
 				qdf_dma_addr_t scatter_bufs_base_paddr[],
@@ -1077,6 +1084,8 @@ struct hal_hw_txrx_ops {
 #ifdef DP_UMAC_HW_RESET_SUPPORT
 	void (*hal_unregister_reo_send_cmd)(struct hal_soc *hal_soc);
 	void (*hal_register_reo_send_cmd)(struct hal_soc *hal_soc);
+	void (*hal_reset_rx_reo_tid_q)(struct hal_soc *hal_soc,
+				       void *hw_qdesc_vaddr, uint32_t size);
 #endif
 	uint32_t (*hal_rx_tlv_sgi_get)(uint8_t *buf);
 	uint32_t (*hal_rx_tlv_get_freq)(uint8_t *buf);
@@ -1159,7 +1168,8 @@ struct hal_hw_txrx_ops {
 						   uint8_t *num_users);
 #endif /* QCA_MONITOR_2_0_SUPPORT */
 	void (*hal_reo_shared_qaddr_setup)(hal_soc_handle_t hal_soc_hdl);
-	void (*hal_reo_shared_qaddr_init)(hal_soc_handle_t hal_soc_hdl);
+	void (*hal_reo_shared_qaddr_init)(hal_soc_handle_t hal_soc_hdl,
+					  int qref_reset);
 	void (*hal_reo_shared_qaddr_detach)(hal_soc_handle_t hal_soc_hdl);
 	void (*hal_reo_shared_qaddr_write)(hal_soc_handle_t hal_soc_hdl,
 					   uint16_t peer_id,

hal/wifi3.0/hal_reo.h

@@ -635,6 +635,18 @@ hal_unregister_reo_send_cmd(hal_soc_handle_t hal_soc_hdl)
 	if (hal_soc->ops->hal_unregister_reo_send_cmd)
 		return hal_soc->ops->hal_unregister_reo_send_cmd(hal_soc);
 }
+
+static inline void
+hal_reset_rx_reo_tid_queue(hal_soc_handle_t hal_soc_hdl, void *hw_qdesc_vaddr,
+			   uint32_t size)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
+
+	if (hal_soc->ops->hal_reset_rx_reo_tid_q)
+		hal_soc->ops->hal_reset_rx_reo_tid_q(hal_soc, hw_qdesc_vaddr,
+						     size);
+}
+
 #endif
 
 static inline QDF_STATUS

hal/wifi3.0/hal_rx.h

@@ -2941,18 +2941,20 @@ hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl,
 /**
  * hal_reo_shared_qaddr_init(): Initialize reo qref LUT
  * @hal_soc: Hal soc pointer
+ * @qref_reset: reset qref LUT
  *
  * Write MLO and Non MLO table start addr to HW reg
  *
  * Return: void
  */
 static inline void
-hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl)
+hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl, int qref_reset)
 {
 	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
 
 	if (hal_soc->ops->hal_reo_shared_qaddr_init)
-		return hal_soc->ops->hal_reo_shared_qaddr_init(hal_soc_hdl);
+		return hal_soc->ops->hal_reo_shared_qaddr_init(hal_soc_hdl,
+							       qref_reset);
 }
 
 /**
@@ -2982,7 +2984,7 @@ hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl,
 			   int tid,
 			   qdf_dma_addr_t hw_qdesc_paddr) {}
 static inline void
-hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl) {}
+hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl, int qref_reset) {}
 
 static inline void
 hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl) {}

hal/wifi3.0/hal_srng.c

@@ -1375,14 +1375,15 @@ qdf_export_symbol(hal_srng_dst_init_hp);
  * hal_srng_hw_init - Private function to initialize SRNG HW
  * @hal_soc: HAL SOC handle
  * @srng: SRNG ring pointer
+ * @idle_check: Check if ring is idle
  */
 static inline void hal_srng_hw_init(struct hal_soc *hal,
-	struct hal_srng *srng)
+	struct hal_srng *srng, bool idle_check)
 {
 	if (srng->ring_dir == HAL_SRNG_SRC_RING)
-		hal_srng_src_hw_init(hal, srng);
+		hal_srng_src_hw_init(hal, srng, idle_check);
 	else
-		hal_srng_dst_hw_init(hal, srng);
+		hal_srng_dst_hw_init(hal, srng, idle_check);
 }
 
 #if defined(CONFIG_SHADOW_V2) || defined(CONFIG_SHADOW_V3)
@@ -1539,7 +1540,8 @@ static inline void hal_srng_update_high_wm_thresholds(struct hal_srng *srng)
  * from 0)
  * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings
  * @ring_params: SRNG ring params in hal_srng_params structure.
-
+ * @idle_check: Check if ring is idle
+ *
  * Callers are expected to allocate contiguous ring memory of size
  * 'num_entries * entry_size' bytes and pass the physical and virtual base
  * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in
@@ -1551,7 +1553,7 @@ static inline void hal_srng_update_high_wm_thresholds(struct hal_srng *srng)
  *		 NULL on failure (if given ring is not available)
  */
 void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
-	int mac_id, struct hal_srng_params *ring_params)
+	int mac_id, struct hal_srng_params *ring_params, bool idle_check)
 {
 	int ring_id;
 	struct hal_soc *hal = (struct hal_soc *)hal_soc;
@@ -1590,7 +1592,8 @@ void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
 	srng->intr_timer_thres_us = ring_params->intr_timer_thres_us;
 	srng->intr_batch_cntr_thres_entries =
 		ring_params->intr_batch_cntr_thres_entries;
-	srng->prefetch_timer = ring_params->prefetch_timer;
+	if (!idle_check)
+		srng->prefetch_timer = ring_params->prefetch_timer;
 	srng->hal_soc = hal_soc;
 	hal_srng_set_msi2_params(srng, ring_params);
 	hal_srng_update_high_wm_thresholds(srng);
@@ -1634,6 +1637,11 @@ void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
 			&(hal->shadow_rdptr_mem_vaddr[ring_id]);
 		srng->u.src_ring.low_threshold =
 			ring_params->low_threshold * srng->entry_size;
+
+		if (srng->u.src_ring.tp_addr)
+			qdf_mem_zero(srng->u.src_ring.tp_addr,
+				     sizeof(*hal->shadow_rdptr_mem_vaddr));
+
 		if (ring_config->lmac_ring) {
 			/* For LMAC rings, head pointer updates will be done
 			 * through FW by writing to a shared memory location
@@ -1642,6 +1650,11 @@ void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
 				&(hal->shadow_wrptr_mem_vaddr[ring_id -
 					HAL_SRNG_LMAC1_ID_START]);
 			srng->flags |= HAL_SRNG_LMAC_RING;
+
+			if (srng->u.src_ring.hp_addr)
+				qdf_mem_zero(srng->u.src_ring.hp_addr,
+					sizeof(*hal->shadow_wrptr_mem_vaddr));
+
 		} else if (ignore_shadow || (srng->u.src_ring.hp_addr == 0)) {
 			srng->u.src_ring.hp_addr =
 				hal_get_window_address(hal,
@@ -1672,6 +1685,11 @@ void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
 		srng->u.dst_ring.tp = 0;
 		srng->u.dst_ring.hp_addr =
 			&(hal->shadow_rdptr_mem_vaddr[ring_id]);
+
+		if (srng->u.dst_ring.hp_addr)
+			qdf_mem_zero(srng->u.dst_ring.hp_addr,
+				     sizeof(*hal->shadow_rdptr_mem_vaddr));
+
 		if (ring_config->lmac_ring) {
 			/* For LMAC rings, tail pointer updates will be done
 			 * through FW by writing to a shared memory location
@@ -1680,6 +1698,11 @@ void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
 				&(hal->shadow_wrptr_mem_vaddr[ring_id -
 				HAL_SRNG_LMAC1_ID_START]);
 			srng->flags |= HAL_SRNG_LMAC_RING;
+
+			if (srng->u.dst_ring.tp_addr)
+				qdf_mem_zero(srng->u.dst_ring.tp_addr,
+					sizeof(*hal->shadow_wrptr_mem_vaddr));
+
 		} else if (ignore_shadow || srng->u.dst_ring.tp_addr == 0) {
 			srng->u.dst_ring.tp_addr =
 				hal_get_window_address(hal,
@@ -1699,7 +1722,7 @@ void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
 	}
 
 	if (!(ring_config->lmac_ring)) {
-		hal_srng_hw_init(hal, srng);
+		hal_srng_hw_init(hal, srng, idle_check);
 
 		if (ring_type == CE_DST) {
 			srng->u.dst_ring.max_buffer_length = ring_params->max_buffer_length;
@@ -1727,6 +1750,7 @@ void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
 	struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
 	SRNG_LOCK_DESTROY(&srng->lock);
 	srng->initialized = 0;
+	hal_srng_hw_disable(hal_soc, srng);
 }
 qdf_export_symbol(hal_srng_cleanup);
 

hal/wifi3.0/li/hal_li_generic_api.h

@@ -2195,9 +2195,11 @@ static inline void hal_setup_reo_swap(struct hal_soc *soc)
  *
  * @hal_soc: Opaque HAL SOC handle
  * @reo_params: parameters needed by HAL for REO config
+ * @qref_reset: reset qref
  */
 static
-void hal_reo_setup_generic_li(struct hal_soc *soc, void *reoparams)
+void hal_reo_setup_generic_li(struct hal_soc *soc, void *reoparams,
+			      int qref_reset)
 {
 	uint32_t reg_val;
 	struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;

hal/wifi3.0/qcn9224/hal_9224.h

@@ -1649,7 +1649,8 @@ static uint8_t hal_tx_get_num_tcl_banks_9224(void)
 	return HAL_NUM_TCL_BANKS_9224;
 }
 
-static void hal_reo_setup_9224(struct hal_soc *soc, void *reoparams)
+static void hal_reo_setup_9224(struct hal_soc *soc, void *reoparams,
+			       int qref_reset)
 {
 	uint32_t reg_val;
 	struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
@@ -1734,7 +1735,7 @@ static void hal_reo_setup_9224(struct hal_soc *soc, void *reoparams)
 	 * GLOBAL_LINK_DESC_COUNT_CTRL
 	 */
 
-	hal_reo_shared_qaddr_init((hal_soc_handle_t)soc);
+	hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset);
 }
 
 static uint16_t hal_get_rx_max_ba_window_qcn9224(int tid)
@@ -1812,6 +1813,7 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
 	/* init and setup */
 	hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
 	hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
+	hal_soc->ops->hal_srng_hw_disable = hal_srng_hw_disable_generic;
 	hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
 	hal_soc->ops->hal_get_window_address = hal_get_window_address_9224;
 	hal_soc->ops->hal_cmem_write = hal_cmem_write_9224;