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qcacmn: Hal changes for Umac post reset at host

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Hal layer changes to handle Umac post reset
and post reset complete events from firmware.

Change-Id: Ib25427930aab25650731c87b38e2ef7e47ae98d9
CRs-Fixed: 3267222
This commit is contained in:
Pavankumar Nandeshwar
2022-08-12 10:40:33 -07:00
committed by Madan Koyyalamudi
parent 67de6bcbfd
commit a615488cf4
11 changed files with 287 additions and 37 deletions
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85
hal/wifi3.0/hal_generic_api.h
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@@ -21,6 +21,9 @@
#include <hal_rx.h>
#define SRNG_ENABLE_BIT 0x40
#define SRNG_IDLE_STATE_BIT 0x80
/**
* hal_get_radiotap_he_gi_ltf() - Convert HE ltf and GI value
* from stats enum to radiotap enum
@@ -177,19 +180,80 @@ static void hal_wbm_idle_lsb_write_confirm(struct hal_srng *srng)
}
#endif
#ifdef DP_UMAC_HW_RESET_SUPPORT
/**
* hal_srng_src_hw_init - Private function to initialize SRNG
* hal_srng_src_hw_write_cons_prefetch_timer() - Write cons prefetch timer reg
* @srng: srng handle
* @value: value to set
*
* Return: None
*/
static inline
void hal_srng_src_hw_write_cons_prefetch_timer(struct hal_srng *srng,
uint32_t value)
{
SRNG_SRC_REG_WRITE(srng, CONSUMER_PREFETCH_TIMER, value);
}
/**
* hal_srng_hw_disable_generic - Private function to disable SRNG
* source ring HW
* @hal_soc: HAL SOC handle
* @srng: SRNG ring pointer
*/
static inline
void hal_srng_hw_disable_generic(struct hal_soc *hal, struct hal_srng *srng)
{
uint32_t reg_val = 0;
if (srng->ring_dir == HAL_SRNG_DST_RING) {
reg_val = SRNG_DST_REG_READ(srng, MISC) & ~(SRNG_ENABLE_BIT);
SRNG_DST_REG_WRITE(srng, MISC, reg_val);
} else {
reg_val = SRNG_SRC_REG_READ(srng, MISC) & ~(SRNG_ENABLE_BIT);
SRNG_SRC_REG_WRITE(srng, MISC, reg_val);
srng->prefetch_timer =
SRNG_SRC_REG_READ(srng, CONSUMER_PREFETCH_TIMER);
hal_srng_src_hw_write_cons_prefetch_timer(srng, 0);
}
}
#else
static inline
void hal_srng_hw_disable_generic(struct hal_soc *hal, struct hal_srng *srng)
{
}
static inline
void hal_srng_src_hw_write_cons_prefetch_timer(struct hal_srng *srng,
uint32_t value)
{
}
#endif
/**
* hal_srng_src_hw_init - Private function to initialize SRNG
* source ring HW
* @hal_soc: HAL SOC handle
* @srng: SRNG ring pointer
* @idle_check: Check if ring is idle
*/
static inline
void hal_srng_src_hw_init_generic(struct hal_soc *hal,
struct hal_srng *srng)
struct hal_srng *srng, bool idle_check)
{
uint32_t reg_val = 0;
uint64_t tp_addr = 0;
if (idle_check) {
reg_val = SRNG_SRC_REG_READ(srng, MISC);
if (!(reg_val & SRNG_IDLE_STATE_BIT)) {
hal_err("ring_id %d not in idle state", srng->ring_id);
qdf_assert_always(0);
}
hal_srng_src_hw_write_cons_prefetch_timer(srng,
srng->prefetch_timer);
}
hal_debug("hw_init srng %d", srng->ring_id);
if (srng->flags & HAL_SRNG_MSI_INTR) {
@@ -288,7 +352,7 @@ void hal_srng_src_hw_init_generic(struct hal_soc *hal,
* (when SRNG_ENABLE field for the MISC register is available in fw_api)
* (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC)
*/
reg_val |= 0x40;
reg_val |= SRNG_ENABLE_BIT;
SRNG_SRC_REG_WRITE(srng, MISC, reg_val);
}
@@ -357,14 +421,23 @@ static inline void hal_srng_dst_near_full_int_setup(struct hal_srng *srng)
* destination ring HW
* @hal_soc: HAL SOC handle
* @srng: SRNG ring pointer
* @idle_check: Check if ring is idle
*/
static inline
void hal_srng_dst_hw_init_generic(struct hal_soc *hal,
struct hal_srng *srng)
struct hal_srng *srng, bool idle_check)
{
uint32_t reg_val = 0;
uint64_t hp_addr = 0;
if (idle_check) {
reg_val = SRNG_DST_REG_READ(srng, MISC);
if (!(reg_val & SRNG_IDLE_STATE_BIT)) {
hal_err("ring_id %d not in idle state", srng->ring_id);
qdf_assert_always(0);
}
}
hal_debug("hw_init srng %d", srng->ring_id);
if (srng->flags & HAL_SRNG_MSI_INTR) {
@@ -492,6 +565,10 @@ static inline void hal_srng_hw_reg_offset_init_generic(struct hal_soc *hal_soc)
REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0);
hw_reg_offset[SRC_CONSUMER_INT_SETUP_IX1] =
REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1);
#ifdef DP_UMAC_HW_RESET_SUPPORT
hw_reg_offset[SRC_CONSUMER_PREFETCH_TIMER] =
REG_OFFSET(SRC, CONSUMER_PREFETCH_TIMER);
#endif
}
#endif /* HAL_GENERIC_API_H_ */