disp: msm: sde: Add support for PCC position field

A new position control register field has been added to the
DSPP PCC on Lahaina. This field controls whether PCC is invoked
before or after GAMUT mapping.

Introduce new PCC control logic to set the PCC position based on
the new PCC_BEFORE flag. Older versions of the PCC control function
now clear all flags to ensure backwards compatibility.

Change-Id: I0a33604111b755e0a0ccf1864a57b17cc9071e3f
Signed-off-by: Christopher Braga <[email protected]>

msm/sde/sde_color_processing.c

@@ -2368,6 +2368,7 @@ static void dspp_pcc_install_property(struct drm_crtc *crtc)
 	switch (version) {
 	case 1:
 	case 4:
+	case 5:
 		sde_cp_crtc_install_blob_property(crtc, feature_name,
 			SDE_CP_CRTC_DSPP_PCC, sizeof(struct drm_msm_pcc));
 		break;

msm/sde/sde_hw_dspp.c

@@ -70,6 +70,13 @@ static void dspp_pcc(struct sde_hw_dspp *c)
 			c->ops.setup_pcc = reg_dmav1_setup_dspp_pccv4;
 		else
 			c->ops.setup_pcc = sde_setup_dspp_pccv4;
+	} else if (c->cap->sblk->pcc.version ==
+			(SDE_COLOR_PROCESS_VER(0x5, 0x0))) {
+		ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_PCC, c->idx);
+		if (!ret)
+			c->ops.setup_pcc = reg_dmav1_setup_dspp_pccv5;
+		else
+			c->ops.setup_pcc = NULL;
 	}
 }
 

msm/sde/sde_hw_reg_dma_v1_color_proc.c

@@ -1226,7 +1226,7 @@ exit:
 	return rc;
 }
 
-static void _dspp_pccv4_off(struct sde_hw_dspp *ctx, void *cfg)
+static void _dspp_pcc_common_off(struct sde_hw_dspp *ctx, void *cfg)
 {
 	struct sde_reg_dma_kickoff_cfg kick_off;
 	struct sde_hw_cp_cfg *hw_cfg = cfg;
@@ -1274,7 +1274,7 @@ static void _dspp_pccv4_off(struct sde_hw_dspp *ctx, void *cfg)
 		DRM_ERROR("failed to kick off ret %d\n", rc);
 }
 
-void reg_dmav1_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg)
+void reg_dmav1_setup_dspp_pcc_common(struct sde_hw_dspp *ctx, void *cfg)
 {
 	struct sde_hw_reg_dma_ops *dma_ops;
 	struct sde_reg_dma_kickoff_cfg kick_off;
@@ -1293,7 +1293,7 @@ void reg_dmav1_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg)
 
 	if (!hw_cfg->payload) {
 		DRM_DEBUG_DRIVER("disable pcc feature\n");
-		_dspp_pccv4_off(ctx, cfg);
+		_dspp_pcc_common_off(ctx, cfg);
 		return;
 	}
 
@@ -1374,7 +1374,11 @@ void reg_dmav1_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg)
 		goto exit;
 	}
 
+
 	reg = PCC_EN;
+	if (pcc_cfg->flags & PCC_BEFORE)
+		reg |= BIT(16);
+
 	REG_DMA_SETUP_OPS(dma_write_cfg,
 		ctx->cap->sblk->pcc.base,
 		&reg, sizeof(reg), REG_SINGLE_WRITE, 0, 0, 0);
@@ -1392,6 +1396,31 @@ void reg_dmav1_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg)
 
 exit:
 	kfree(data);
+
+}
+
+void reg_dmav1_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg)
+{
+	struct drm_msm_pcc *pcc_cfg;
+	struct sde_hw_cp_cfg *hw_cfg = cfg;
+
+	if (hw_cfg->payload) {
+		if (hw_cfg->len != sizeof(struct drm_msm_pcc)) {
+			DRM_ERROR("invalid size of payload len %d exp %zd\n",
+					hw_cfg->len,
+					sizeof(struct drm_msm_pcc));
+			return;
+		}
+		//Flags unsupported for PCCv4
+		pcc_cfg = hw_cfg->payload;
+		pcc_cfg->flags = 0;
+	}
+	reg_dmav1_setup_dspp_pcc_common(ctx, cfg);
+}
+
+void reg_dmav1_setup_dspp_pccv5(struct sde_hw_dspp *ctx, void *cfg)
+{
+	reg_dmav1_setup_dspp_pcc_common(ctx, cfg);
 }
 
 void reg_dmav1_setup_dspp_pa_hsicv17(struct sde_hw_dspp *ctx, void *cfg)

msm/sde/sde_hw_reg_dma_v1_color_proc.h

@@ -68,6 +68,14 @@ void reg_dmav1_setup_dspp_igcv31(struct sde_hw_dspp *ctx, void *cfg);
  */
 void reg_dmav1_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg);
 
+
+/**
+ * reg_dmav1_setup_dspp_pccv5() - pcc v5 implementation using reg dma v1.
+ * @ctx: dspp ctx info
+ * @cfg: pointer to struct sde_hw_cp_cfg
+ */
+void reg_dmav1_setup_dspp_pccv5(struct sde_hw_dspp *ctx, void *cfg);
+
 /**
  * reg_dmav1_setup_dspp_pa_hsicv17() - pa hsic v17 impl using reg dma v1.
  * @ctx: dspp ctx info