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@@ -459,9 +459,9 @@ static int cam_sfe_bus_start_rm(struct cam_isp_resource_node *rm_res)
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rm_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING;
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rm_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING;
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CAM_DBG(CAM_SFE,
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CAM_DBG(CAM_SFE,
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- "Start SFE:%d RM:%d offset:0x%X en_cfg:0x%X width:%d height:%d",
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+ "Start SFE:%d RM:%d offset:0x%X width:%d height:%d",
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rm_data->common_data->core_index, rm_data->index,
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rm_data->common_data->core_index, rm_data->index,
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- (uint32_t) rm_data->hw_regs->cfg, rm_data->en_cfg,
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+ (uint32_t) rm_data->hw_regs->cfg,
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rm_data->width, rm_data->height);
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rm_data->width, rm_data->height);
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CAM_DBG(CAM_SFE, "RM:%d pk_fmt:%d stride:%d", rm_data->index,
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CAM_DBG(CAM_SFE, "RM:%d pk_fmt:%d stride:%d", rm_data->index,
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rm_data->unpacker_cfg, rm_data->stride);
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rm_data->unpacker_cfg, rm_data->stride);
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@@ -1392,6 +1392,84 @@ skip_cache_cfg:
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return 0;
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return 0;
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}
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}
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+static int cam_sfe_bus_rd_update_rm_core_cfg(
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+ void *priv, void *cmd_args, uint32_t arg_size)
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+{
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+ struct cam_sfe_bus_rd_priv *bus_priv;
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+ struct cam_isp_hw_get_cmd_update *cmd_update;
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+ struct cam_sfe_bus_rd_data *sfe_bus_rd_data = NULL;
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+ struct cam_sfe_bus_rd_rm_resource_data *rm_data = NULL;
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+ struct cam_cdm_utils_ops *cdm_util_ops;
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+ bool enable_disable = false;
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+ uint32_t *reg_val_pair;
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+ uint32_t num_regval_pairs = 0, i, j, size = 0;
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+
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+ bus_priv = (struct cam_sfe_bus_rd_priv *) priv;
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+ cmd_update = (struct cam_isp_hw_get_cmd_update *) cmd_args;
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+ enable_disable = *(bool *)cmd_update->data;
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+
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+ sfe_bus_rd_data = (struct cam_sfe_bus_rd_data *)
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+ cmd_update->res->res_priv;
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+
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+ if (!sfe_bus_rd_data) {
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+ CAM_ERR(CAM_SFE, "Invalid SFE rd data: %pK",
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+ sfe_bus_rd_data);
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+ return -EINVAL;
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+ }
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+
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+ cdm_util_ops = sfe_bus_rd_data->cdm_util_ops;
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+ if (!cdm_util_ops) {
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+ CAM_ERR(CAM_SFE, "Invalid cdm ops: %pK",
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+ cdm_util_ops);
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+ return -EINVAL;
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+ }
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+
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+ reg_val_pair = &sfe_bus_rd_data->common_data->io_buf_update[0];
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+ for (i = 0, j = 0; i < sfe_bus_rd_data->num_rm; i++) {
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+ if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) {
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+ CAM_ERR(CAM_SFE,
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+ "reg_val_pair %d exceeds the array limit %lu",
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+ j, MAX_REG_VAL_PAIR_SIZE);
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+ return -ENOMEM;
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+ }
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+
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+ rm_data = sfe_bus_rd_data->rm_res[i]->res_priv;
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+ CAM_SFE_ADD_REG_VAL_PAIR(reg_val_pair, j,
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+ rm_data->hw_regs->cfg, enable_disable);
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+ CAM_DBG(CAM_SFE, "SFE:%d RM:%d cfg:0x%x",
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+ rm_data->common_data->core_index,
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+ rm_data->index, reg_val_pair[j-1]);
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+ }
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+
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+ num_regval_pairs = j / 2;
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+ if (num_regval_pairs) {
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+ size = cdm_util_ops->cdm_required_size_reg_random(
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+ num_regval_pairs);
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+
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+ /* cdm util returns dwords, need to convert to bytes */
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+ if ((size * 4) > cmd_update->cmd.size) {
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+ CAM_ERR(CAM_SFE,
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+ "Failed! Buf size:%d insufficient, expected size:%d",
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+ cmd_update->cmd.size, size);
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+ return -ENOMEM;
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+ }
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+
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+ cdm_util_ops->cdm_write_regrandom(
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+ cmd_update->cmd.cmd_buf_addr, num_regval_pairs,
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+ reg_val_pair);
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+
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+ /* cdm util returns dwords, need to convert to bytes */
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+ cmd_update->cmd.used_bytes = size * 4;
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+ } else {
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+ cmd_update->cmd.used_bytes = 0;
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+ CAM_DBG(CAM_SFE,
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+ "No reg val pairs. num_rms: %u",
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+ sfe_bus_rd_data->num_rm);
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+ }
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+
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+ return 0;
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+}
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+
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static int cam_sfe_bus_init_hw(void *hw_priv,
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static int cam_sfe_bus_init_hw(void *hw_priv,
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void *init_hw_args, uint32_t arg_size)
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void *init_hw_args, uint32_t arg_size)
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{
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{
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@@ -1495,6 +1573,9 @@ static int cam_sfe_bus_rd_process_cmd(
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case CAM_ISP_HW_SFE_SYS_CACHE_RM_CONFIG:
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case CAM_ISP_HW_SFE_SYS_CACHE_RM_CONFIG:
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rc = cam_sfe_bus_rd_cache_config(priv, cmd_args, arg_size);
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rc = cam_sfe_bus_rd_cache_config(priv, cmd_args, arg_size);
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break;
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break;
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+ case CAM_ISP_HW_CMD_RM_ENABLE_DISABLE:
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+ rc = cam_sfe_bus_rd_update_rm_core_cfg(priv, cmd_args, arg_size);
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+ break;
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default:
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default:
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CAM_ERR_RATE_LIMIT(CAM_SFE,
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CAM_ERR_RATE_LIMIT(CAM_SFE,
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"Invalid SFE BUS RD command type: %d",
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"Invalid SFE BUS RD command type: %d",
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