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@@ -146,7 +146,7 @@ enum hal_rx_ret_buf_manager {
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*/
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#define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \
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((*(((unsigned int *) buff_addr_info) + \
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- (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) |= \
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+ (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \
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(paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \
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BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK)
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@@ -156,7 +156,7 @@ enum hal_rx_ret_buf_manager {
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*/
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#define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \
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((*(((unsigned int *) buff_addr_info) + \
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- (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) |= \
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+ (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \
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(paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \
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BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK)
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@@ -164,6 +164,10 @@ enum hal_rx_ret_buf_manager {
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* macro to set the cookie into the rxdma ring entry
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*/
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#define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \
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+ ((*(((unsigned int *) buff_addr_info) + \
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+ (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \
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+ ~((cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \
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+ BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK)); \
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((*(((unsigned int *) buff_addr_info) + \
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(BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
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(cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \
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@@ -173,6 +177,10 @@ enum hal_rx_ret_buf_manager {
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* macro to set the manager into the rxdma ring entry
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*/
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#define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \
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+ ((*(((unsigned int *) buff_addr_info) + \
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+ (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \
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+ ~((manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \
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+ BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK)); \
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((*(((unsigned int *) buff_addr_info) + \
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(BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \
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(manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \
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