disp: msm: sde: program INTF VSYNC src_en bits for vsync TS

From MSSS 10.x, the src_en bits needs to be set appropriately for
vid/cmd mode for getting the vsync timestamp. Program it based
on the new feature flag SDE_INTF_VSYNC_TS_SRC_EN.

Change-Id: Ia9c59d66afb436f082c7ebe6bf28e3953fde27a5
Signed-off-by: Veera Sundaram Sankaran <[email protected]>

msm/sde/sde_hw_catalog.c

@@ -2507,6 +2507,7 @@ static int sde_intf_parse_dt(struct device_node *np,
 			set_bit(SDE_INTF_TE_SINGLE_UPDATE, &intf->features);
 			set_bit(SDE_INTF_WD_LTJ_CTL, &intf->features);
 			set_bit(SDE_INTF_TE_DEASSERT_DETECT, &intf->features);
+			set_bit(SDE_INTF_VSYNC_TS_SRC_EN, &intf->features);
 		}
 	}
 

msm/sde/sde_hw_catalog.h

@@ -633,6 +633,7 @@ enum {
  * @SDE_INTF_WD_JITTER          INTF block has WD timer jitter support
  * @SDE_INTF_WD_LTJ_CTL         INTF block has WD long term jitter control support
  * @SDE_INTF_TE_DEASSERT_DETECT INTF block has TE Deassert detect support
+ * @SDE_INTF_VSYNC_TS_SRC_EN    INTF block has VSYNC timestamp source selection support
  * @SDE_INTF_MAX
  */
 enum {
@@ -651,6 +652,7 @@ enum {
 	SDE_INTF_WD_JITTER,
 	SDE_INTF_WD_LTJ_CTL,
 	SDE_INTF_TE_DEASSERT_DETECT,
+	SDE_INTF_VSYNC_TS_SRC_EN,
 	SDE_INTF_MAX
 };
 

msm/sde/sde_hw_intf.c

@@ -433,17 +433,22 @@ static void sde_hw_intf_setup_timing_engine(struct sde_hw_intf *ctx,
 	SDE_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl);
 }
 
-static void sde_hw_intf_enable_timing_engine(
-		struct sde_hw_intf *intf,
-		u8 enable)
+static void sde_hw_intf_enable_timing_engine(struct sde_hw_intf *intf, u8 enable)
 {
 	struct sde_hw_blk_reg_map *c = &intf->hw;
+	u32 val;
 
 	/* Note: Display interface select is handled in top block hw layer */
 	SDE_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0);
 
-	if (enable && (intf->cap->features & (BIT(SDE_INTF_PANEL_VSYNC_TS) | BIT(SDE_INTF_MDP_VSYNC_TS))))
-		SDE_REG_WRITE(c, INTF_VSYNC_TIMESTAMP_CTRL, BIT(0));
+	if (enable && (intf->cap->features
+			& (BIT(SDE_INTF_PANEL_VSYNC_TS) | BIT(SDE_INTF_MDP_VSYNC_TS)))) {
+		val = BIT(0);
+		if (intf->cap->features & SDE_INTF_VSYNC_TS_SRC_EN)
+			val |= BIT(4);
+
+		SDE_REG_WRITE(c, INTF_VSYNC_TIMESTAMP_CTRL, val);
+	}
 }
 
 static void sde_hw_intf_setup_prg_fetch(
@@ -843,8 +848,14 @@ static int sde_hw_intf_enable_te(struct sde_hw_intf *intf, bool enable)
 
 	SDE_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, val);
 
-	if (enable && (intf->cap->features & (BIT(SDE_INTF_PANEL_VSYNC_TS) | BIT(SDE_INTF_MDP_VSYNC_TS))))
-		SDE_REG_WRITE(c, INTF_VSYNC_TIMESTAMP_CTRL, BIT(0));
+	if (enable && (intf->cap->features &
+				(BIT(SDE_INTF_PANEL_VSYNC_TS) | BIT(SDE_INTF_MDP_VSYNC_TS)))) {
+		val = BIT(0);
+		if (intf->cap->features & SDE_INTF_VSYNC_TS_SRC_EN)
+			val |= BIT(5);
+
+		SDE_REG_WRITE(c, INTF_VSYNC_TIMESTAMP_CTRL, val);
+	}
 
 	return 0;
 }