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disp: pll: remove unsupported dividers for DSI pixel clock

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Remove dividers that are not recommended for DSI DPHY mode
when setting up the clock tree for the DSI pixel clock.

Change-Id: I2563a35ece541c1f5b46c72af7bd2cc79e72a90e
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
This commit is contained in:
Aravind Venkateswaran
2019-06-10 14:56:20 -07:00
parent 6ec69969e2
commit a545123901
1 changed files with 15 additions and 23 deletions
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38
pll/dsi_pll_7nm.c
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@@ -1746,9 +1746,9 @@ static struct regmap_bus mdss_mux_regmap_bus = {
* +-----------------------------+--------+ * +-----------------------------+--------+
* | | | * | | |
* +-------v-------+ | | * +-------v-------+ | |
* | bitclk_src | | | * | bitclk_src |
* | DIV(1..15) | | | * | DIV(1..15) | Not supported for DPHY
* +-------+-------+ | | * +-------+-------+
* | | | * | | |
* +----------+---------+ | | * +----------+---------+ | |
* Shadow Path | | | | | * Shadow Path | | | | |
@@ -2132,15 +2132,13 @@ static struct clk_regmap_mux dsi1pll_byteclk_mux = {
static struct clk_regmap_mux dsi0pll_pclk_src_mux = { static struct clk_regmap_mux dsi0pll_pclk_src_mux = {
.reg = PHY_CMN_CLK_CFG1, .reg = PHY_CMN_CLK_CFG1,
.shift = 0, .shift = 0,
.width = 2, .width = 1,
.clkr = { .clkr = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "dsi0pll_pclk_src_mux", .name = "dsi0pll_pclk_src_mux",
.parent_names = (const char *[]){"dsi0pll_bitclk_src", .parent_names = (const char *[]){"dsi0pll_bitclk_src",
"dsi0pll_post_bit_div", "dsi0pll_post_bit_div"},
"dsi0pll_pll_out_div", .num_parents = 2,
"dsi0pll_post_vco_div"},
.num_parents = 4,
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
}, },
}, },
@@ -2149,16 +2147,14 @@ static struct clk_regmap_mux dsi0pll_pclk_src_mux = {
static struct clk_regmap_mux dsi0pll_shadow_pclk_src_mux = { static struct clk_regmap_mux dsi0pll_shadow_pclk_src_mux = {
.reg = PHY_CMN_CLK_CFG1, .reg = PHY_CMN_CLK_CFG1,
.shift = 0, .shift = 0,
.width = 2, .width = 1,
.clkr = { .clkr = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "dsi0pll_shadow_pclk_src_mux", .name = "dsi0pll_shadow_pclk_src_mux",
.parent_names = (const char *[]){ .parent_names = (const char *[]){
"dsi0pll_shadow_bitclk_src", "dsi0pll_shadow_bitclk_src",
"dsi0pll_shadow_post_bit_div", "dsi0pll_shadow_post_bit_div"},
"dsi0pll_shadow_pll_out_div", .num_parents = 2,
"dsi0pll_shadow_post_vco_div"},
.num_parents = 4,
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
}, },
}, },
@@ -2167,15 +2163,13 @@ static struct clk_regmap_mux dsi0pll_shadow_pclk_src_mux = {
static struct clk_regmap_mux dsi1pll_pclk_src_mux = { static struct clk_regmap_mux dsi1pll_pclk_src_mux = {
.reg = PHY_CMN_CLK_CFG1, .reg = PHY_CMN_CLK_CFG1,
.shift = 0, .shift = 0,
.width = 2, .width = 1,
.clkr = { .clkr = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "dsi1pll_pclk_src_mux", .name = "dsi1pll_pclk_src_mux",
.parent_names = (const char *[]){"dsi1pll_bitclk_src", .parent_names = (const char *[]){"dsi1pll_bitclk_src",
"dsi1pll_post_bit_div", "dsi1pll_post_bit_div"},
"dsi1pll_pll_out_div", .num_parents = 2,
"dsi1pll_post_vco_div"},
.num_parents = 4,
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
}, },
}, },
@@ -2184,16 +2178,14 @@ static struct clk_regmap_mux dsi1pll_pclk_src_mux = {
static struct clk_regmap_mux dsi1pll_shadow_pclk_src_mux = { static struct clk_regmap_mux dsi1pll_shadow_pclk_src_mux = {
.reg = PHY_CMN_CLK_CFG1, .reg = PHY_CMN_CLK_CFG1,
.shift = 0, .shift = 0,
.width = 2, .width = 1,
.clkr = { .clkr = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "dsi1pll_shadow_pclk_src_mux", .name = "dsi1pll_shadow_pclk_src_mux",
.parent_names = (const char *[]){ .parent_names = (const char *[]){
"dsi1pll_shadow_bitclk_src", "dsi1pll_shadow_bitclk_src",
"dsi1pll_shadow_post_bit_div", "dsi1pll_shadow_post_bit_div"},
"dsi1pll_shadow_pll_out_div", .num_parents = 2,
"dsi1pll_shadow_post_vco_div"},
.num_parents = 4,
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
}, },
}, },