soc: swr-mstr: Reset swr only during init or ssr

Reset swr only during init or ssr-pdr scenarios.
Do not reset swr during clock stop, which would
result in bad state of master and cause error
interrupts.

Change-Id: I88e071921409a5b5797aeedb8e7cb57cb5d5bb9a
Signed-off-by: Ramprasad Katkam <katkam@codeaurora.org>

asoc/codecs/bolero/tx-macro.c

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/module.h>
@@ -127,6 +127,7 @@ struct tx_macro_priv {
 	bool dec_active[NUM_DECIMATORS];
 	int tx_mclk_users;
 	int swr_clk_users;
+	bool reset_swr;
 	struct clk *tx_core_clk;
 	struct clk *tx_npl_clk;
 	struct mutex mclk_lock;
@@ -317,6 +318,8 @@ static int tx_macro_event_handler(struct snd_soc_component *component,
 			SWR_DEVICE_DOWN, NULL);
 		break;
 	case BOLERO_MACRO_EVT_SSR_UP:
+		/* reset swr after ssr/pdr */
+		tx_priv->reset_swr = true;
 		swrm_wcd_notify(
 			tx_priv->swr_ctrl_data[0].tx_swr_pdev,
 			SWR_DEVICE_SSR_UP, NULL);
@@ -1426,9 +1429,18 @@ static int tx_macro_swrm_clock(void *handle, bool enable)
 					__func__);
 				goto exit;
 			}
+			if (tx_priv->reset_swr)
+				regmap_update_bits(regmap,
+					BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
+					0x02, 0x02);
 			regmap_update_bits(regmap,
 				BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
 				0x01, 0x01);
+			if (tx_priv->reset_swr)
+				regmap_update_bits(regmap,
+					BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
+					0x02, 0x00);
+			tx_priv->reset_swr = false;
 			regmap_update_bits(regmap,
 				BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
 				0x1C, 0x0C);
@@ -1799,7 +1811,7 @@ static int tx_macro_probe(struct platform_device *pdev)
 		sample_rate, tx_priv) == TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED)
 			return -EINVAL;
 	}
-
+	tx_priv->reset_swr = true;
 	INIT_WORK(&tx_priv->tx_macro_add_child_devices_work,
 		  tx_macro_add_child_devices);
 	tx_priv->swr_plat_data.handle = (void *) tx_priv;