qcacld-3.0: Modify the HE cap MCS for 160Mhz

Currently the driver intersects the 2g and 5g
capability and stores them in the HE cap variable
of the same PHY.
In the HW where a single PHY supports both 2g and
5g and with max BW support of 160Mhz, the intersection
of 160Mhz and 80+80Mhz MCS will lead to zero as 2g will
not support 160 and 80+80 BW. Hence the MCS map will be
0 for them indicating that the STA would support only
till MCS 7 and not above that which would lead to a
lower coding rate and lower QAM thus resulting in
a lower throughput.

Fix is to not intersect the MCS capability of 2g and 5g
and copy MCS directly from the target capability.

Change-Id: Ice5c426db43516b5dff5379926086b40d69f3d96
CRs-Fixed: 2732512

core/wma/src/wma_he.c

@@ -521,22 +521,14 @@ static void wma_derive_ext_he_cap(tDot11fIEhe_cap *he_cap,
 	mcs_2 = new_cap->tx_he_mcs_map_lt_80;
 	he_cap->tx_he_mcs_map_lt_80 = HE_INTERSECT_MCS(mcs_1, mcs_2);
 	if (is_5g_cap) {
-		mcs_1 = *((uint16_t *)he_cap->rx_he_mcs_map_160);
-		mcs_2 = *((uint16_t *)new_cap->rx_he_mcs_map_160);
 		*((uint16_t *)he_cap->rx_he_mcs_map_160) =
-			HE_INTERSECT_MCS(mcs_1, mcs_2);
-		mcs_1 = *((uint16_t *)he_cap->tx_he_mcs_map_160);
-		mcs_2 = *((uint16_t *)new_cap->tx_he_mcs_map_160);
+			*((uint16_t *)new_cap->rx_he_mcs_map_160);
 		*((uint16_t *)he_cap->tx_he_mcs_map_160) =
-			HE_INTERSECT_MCS(mcs_1, mcs_2);
-		mcs_1 = *((uint16_t *)he_cap->rx_he_mcs_map_80_80);
-		mcs_2 = *((uint16_t *)new_cap->rx_he_mcs_map_80_80);
+			*((uint16_t *)new_cap->tx_he_mcs_map_160);
 		*((uint16_t *)he_cap->rx_he_mcs_map_80_80) =
-			HE_INTERSECT_MCS(mcs_1, mcs_2);
-		mcs_1 = *((uint16_t *)he_cap->tx_he_mcs_map_80_80);
-		mcs_2 = *((uint16_t *)new_cap->tx_he_mcs_map_80_80);
+			*((uint16_t *)new_cap->rx_he_mcs_map_80_80);
 		*((uint16_t *)he_cap->tx_he_mcs_map_80_80) =
-			HE_INTERSECT_MCS(mcs_1, mcs_2);
+			*((uint16_t *)new_cap->tx_he_mcs_map_80_80);
 	}
 }