qcacmn: Add delayed reg write support for wcn6450
Current HAL delayed reg write is tied to SRNG notions, hence implement delayed reg write logic in HIF since WCN6450 does not use SRNG interface. New feature flag FEATURE_HIF_DELAYED_REG_WRITE is introduced to disable/enable this support. Change-Id: Id7087ad53cd5879cf49ee0e84dd727de61137541 CRs-Fixed: 3519702
This commit is contained in:
Venkateswara Naralasetty
committed by
Rahul Choudhary
Rahul Choudhary
parent
219a541da6
commit
a3a5a72bbd
@@ -55,6 +55,8 @@
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#include <linux/cpumask.h>
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#include <pld_common.h>
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#include "ce_internal.h"
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#include <qdf_tracepoint.h>
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void hif_dump(struct hif_opaque_softc *hif_ctx, uint8_t cmd_id, bool start)
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{
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@@ -1392,6 +1394,11 @@ static inline int hif_get_num_pending_work(struct hif_softc *scn)
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{
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return hal_get_reg_write_pending_work(scn->hal_soc);
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}
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#elif defined(FEATURE_HIF_DELAYED_REG_WRITE)
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static inline int hif_get_num_pending_work(struct hif_softc *scn)
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{
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return qdf_atomic_read(&scn->active_work_cnt);
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}
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#else
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static inline int hif_get_num_pending_work(struct hif_softc *scn)
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@@ -1527,6 +1534,354 @@ uint8_t hif_get_ep_vote_access(struct hif_opaque_softc *hif_ctx,
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}
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#endif
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#ifdef FEATURE_HIF_DELAYED_REG_WRITE
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#ifdef MEMORY_DEBUG
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#define HIF_REG_WRITE_QUEUE_LEN 128
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#else
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#define HIF_REG_WRITE_QUEUE_LEN 32
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#endif
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/**
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* hif_print_reg_write_stats() - Print hif delayed reg write stats
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* @hif_ctx: hif opaque handle
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*
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* Return: None
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*/
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void hif_print_reg_write_stats(struct hif_opaque_softc *hif_ctx)
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{
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struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx);
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struct CE_state *ce_state;
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uint32_t *hist;
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int i;
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hist = scn->wstats.sched_delay;
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hif_debug("wstats: enq %u deq %u coal %u direct %u q_depth %u max_q %u sched-delay hist %u %u %u %u",
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qdf_atomic_read(&scn->wstats.enqueues),
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scn->wstats.dequeues,
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qdf_atomic_read(&scn->wstats.coalesces),
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qdf_atomic_read(&scn->wstats.direct),
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qdf_atomic_read(&scn->wstats.q_depth),
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scn->wstats.max_q_depth,
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hist[HIF_REG_WRITE_SCHED_DELAY_SUB_100us],
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hist[HIF_REG_WRITE_SCHED_DELAY_SUB_1000us],
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hist[HIF_REG_WRITE_SCHED_DELAY_SUB_5000us],
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hist[HIF_REG_WRITE_SCHED_DELAY_GT_5000us]);
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for (i = 0; i < scn->ce_count; i++) {
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ce_state = scn->ce_id_to_state[i];
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if (!ce_state)
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continue;
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hif_debug("ce%d: enq %u deq %u coal %u direct %u",
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i, ce_state->wstats.enqueues,
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ce_state->wstats.dequeues,
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ce_state->wstats.coalesces,
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ce_state->wstats.direct);
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}
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}
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/**
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* hif_is_reg_write_tput_level_high() - throughput level for delayed reg writes
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* @scn: hif_softc pointer
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*
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* Return: true if throughput is high, else false.
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*/
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static inline bool hif_is_reg_write_tput_level_high(struct hif_softc *scn)
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{
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int bw_level = hif_get_bandwidth_level(GET_HIF_OPAQUE_HDL(scn));
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return (bw_level >= PLD_BUS_WIDTH_MEDIUM) ? true : false;
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}
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/**
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* hif_reg_write_fill_sched_delay_hist() - fill reg write delay histogram
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* @scn: hif_softc pointer
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* @delay_us: delay in us
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*
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* Return: None
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*/
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static inline void hif_reg_write_fill_sched_delay_hist(struct hif_softc *scn,
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uint64_t delay_us)
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{
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uint32_t *hist;
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hist = scn->wstats.sched_delay;
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if (delay_us < 100)
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hist[HIF_REG_WRITE_SCHED_DELAY_SUB_100us]++;
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else if (delay_us < 1000)
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hist[HIF_REG_WRITE_SCHED_DELAY_SUB_1000us]++;
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else if (delay_us < 5000)
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hist[HIF_REG_WRITE_SCHED_DELAY_SUB_5000us]++;
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else
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hist[HIF_REG_WRITE_SCHED_DELAY_GT_5000us]++;
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}
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/**
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* hif_process_reg_write_q_elem() - process a register write queue element
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* @scn: hif_softc pointer
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* @q_elem: pointer to hal register write queue element
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*
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* Return: The value which was written to the address
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*/
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static int32_t
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hif_process_reg_write_q_elem(struct hif_softc *scn,
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struct hif_reg_write_q_elem *q_elem)
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{
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struct CE_state *ce_state = q_elem->ce_state;
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uint32_t write_val = -1;
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qdf_spin_lock_bh(&ce_state->ce_index_lock);
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ce_state->reg_write_in_progress = false;
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ce_state->wstats.dequeues++;
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if (ce_state->src_ring) {
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q_elem->dequeue_val = ce_state->src_ring->write_index;
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hal_write32_mb(scn->hal_soc, ce_state->ce_wrt_idx_offset,
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ce_state->src_ring->write_index);
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write_val = ce_state->src_ring->write_index;
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} else if (ce_state->dest_ring) {
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q_elem->dequeue_val = ce_state->dest_ring->write_index;
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hal_write32_mb(scn->hal_soc, ce_state->ce_wrt_idx_offset,
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ce_state->dest_ring->write_index);
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write_val = ce_state->dest_ring->write_index;
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} else {
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hif_debug("invalid reg write received");
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qdf_assert(0);
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}
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q_elem->valid = 0;
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ce_state->last_dequeue_time = q_elem->dequeue_time;
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qdf_spin_unlock_bh(&ce_state->ce_index_lock);
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return write_val;
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}
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/**
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* hif_reg_write_work() - Worker to process delayed writes
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* @arg: hif_softc pointer
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*
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* Return: None
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*/
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static void hif_reg_write_work(void *arg)
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{
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struct hif_softc *scn = arg;
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struct hif_reg_write_q_elem *q_elem;
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uint32_t offset;
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uint64_t delta_us;
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int32_t q_depth, write_val;
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uint32_t num_processed = 0;
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int32_t ring_id;
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q_elem = &scn->reg_write_queue[scn->read_idx];
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q_elem->work_scheduled_time = qdf_get_log_timestamp();
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q_elem->cpu_id = qdf_get_cpu();
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/* Make sure q_elem consistent in the memory for multi-cores */
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qdf_rmb();
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if (!q_elem->valid)
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return;
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q_depth = qdf_atomic_read(&scn->wstats.q_depth);
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if (q_depth > scn->wstats.max_q_depth)
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scn->wstats.max_q_depth = q_depth;
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if (hif_prevent_link_low_power_states(GET_HIF_OPAQUE_HDL(scn))) {
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scn->wstats.prevent_l1_fails++;
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return;
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}
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while (true) {
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qdf_rmb();
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if (!q_elem->valid)
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break;
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q_elem->dequeue_time = qdf_get_log_timestamp();
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ring_id = q_elem->ce_state->id;
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offset = q_elem->offset;
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delta_us = qdf_log_timestamp_to_usecs(q_elem->dequeue_time -
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q_elem->enqueue_time);
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hif_reg_write_fill_sched_delay_hist(scn, delta_us);
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scn->wstats.dequeues++;
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qdf_atomic_dec(&scn->wstats.q_depth);
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write_val = hif_process_reg_write_q_elem(scn, q_elem);
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hif_debug("read_idx %u ce_id %d offset 0x%x dequeue_val %d",
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scn->read_idx, ring_id, offset, write_val);
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qdf_trace_dp_del_reg_write(ring_id, q_elem->enqueue_val,
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q_elem->dequeue_val,
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q_elem->enqueue_time,
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q_elem->dequeue_time);
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num_processed++;
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scn->read_idx = (scn->read_idx + 1) &
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(HIF_REG_WRITE_QUEUE_LEN - 1);
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q_elem = &scn->reg_write_queue[scn->read_idx];
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}
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hif_allow_link_low_power_states(GET_HIF_OPAQUE_HDL(scn));
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/*
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* Decrement active_work_cnt by the number of elements dequeued after
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* hif_allow_link_low_power_states.
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* This makes sure that hif_try_complete_tasks will wait till we make
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* the bus access in hif_allow_link_low_power_states. This will avoid
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* race condition between delayed register worker and bus suspend
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* (system suspend or runtime suspend).
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*
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* The following decrement should be done at the end!
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*/
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qdf_atomic_sub(num_processed, &scn->active_work_cnt);
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}
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/**
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* hif_delayed_reg_write_deinit() - De-Initialize delayed reg write processing
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* @scn: hif_softc pointer
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*
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* De-initialize main data structures to process register writes in a delayed
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* workqueue.
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*
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* Return: None
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*/
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static void hif_delayed_reg_write_deinit(struct hif_softc *scn)
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{
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qdf_flush_work(&scn->reg_write_work);
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qdf_disable_work(&scn->reg_write_work);
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qdf_flush_workqueue(0, scn->reg_write_wq);
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qdf_destroy_workqueue(0, scn->reg_write_wq);
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qdf_mem_free(scn->reg_write_queue);
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}
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/**
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* hif_delayed_reg_write_init() - Initialization function for delayed reg writes
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* @scn: hif_softc pointer
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*
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* Initialize main data structures to process register writes in a delayed
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* workqueue.
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*/
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static QDF_STATUS hif_delayed_reg_write_init(struct hif_softc *scn)
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{
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qdf_atomic_init(&scn->active_work_cnt);
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scn->reg_write_wq =
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qdf_alloc_high_prior_ordered_workqueue("hif_register_write_wq");
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qdf_create_work(0, &scn->reg_write_work, hif_reg_write_work, scn);
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scn->reg_write_queue = qdf_mem_malloc(HIF_REG_WRITE_QUEUE_LEN *
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sizeof(*scn->reg_write_queue));
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if (!scn->reg_write_queue) {
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hif_err("unable to allocate memory for delayed reg write");
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QDF_BUG(0);
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return QDF_STATUS_E_NOMEM;
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}
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/* Initial value of indices */
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scn->read_idx = 0;
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qdf_atomic_set(&scn->write_idx, -1);
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return QDF_STATUS_SUCCESS;
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}
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static void hif_reg_write_enqueue(struct hif_softc *scn,
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struct CE_state *ce_state,
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uint32_t value)
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{
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struct hif_reg_write_q_elem *q_elem;
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uint32_t write_idx;
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if (ce_state->reg_write_in_progress) {
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hif_debug("Already in progress ce_id %d offset 0x%x value %u",
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ce_state->id, ce_state->ce_wrt_idx_offset, value);
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qdf_atomic_inc(&scn->wstats.coalesces);
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ce_state->wstats.coalesces++;
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return;
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}
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write_idx = qdf_atomic_inc_return(&scn->write_idx);
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write_idx = write_idx & (HIF_REG_WRITE_QUEUE_LEN - 1);
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q_elem = &scn->reg_write_queue[write_idx];
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if (q_elem->valid) {
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hif_err("queue full");
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QDF_BUG(0);
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return;
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}
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qdf_atomic_inc(&scn->wstats.enqueues);
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ce_state->wstats.enqueues++;
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qdf_atomic_inc(&scn->wstats.q_depth);
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q_elem->ce_state = ce_state;
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q_elem->offset = ce_state->ce_wrt_idx_offset;
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q_elem->enqueue_val = value;
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q_elem->enqueue_time = qdf_get_log_timestamp();
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/*
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* Before the valid flag is set to true, all the other
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* fields in the q_elem needs to be updated in memory.
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* Else there is a chance that the dequeuing worker thread
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* might read stale entries and process incorrect srng.
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*/
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qdf_wmb();
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q_elem->valid = true;
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/*
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* After all other fields in the q_elem has been updated
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* in memory successfully, the valid flag needs to be updated
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* in memory in time too.
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* Else there is a chance that the dequeuing worker thread
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* might read stale valid flag and the work will be bypassed
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* for this round. And if there is no other work scheduled
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* later, this hal register writing won't be updated any more.
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*/
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qdf_wmb();
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ce_state->reg_write_in_progress = true;
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qdf_atomic_inc(&scn->active_work_cnt);
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hif_debug("write_idx %u ce_id %d offset 0x%x value %u",
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write_idx, ce_state->id, ce_state->ce_wrt_idx_offset, value);
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qdf_queue_work(scn->qdf_dev, scn->reg_write_wq,
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&scn->reg_write_work);
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}
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void hif_delayed_reg_write(struct hif_softc *scn, uint32_t ctrl_addr,
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uint32_t val)
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{
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struct CE_state *ce_state;
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int ce_id = COPY_ENGINE_ID(ctrl_addr);
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ce_state = scn->ce_id_to_state[ce_id];
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if (!ce_state->htt_tx_data && !ce_state->htt_rx_data) {
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hif_reg_write_enqueue(scn, ce_state, val);
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return;
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}
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if (hif_is_reg_write_tput_level_high(scn) ||
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(PLD_MHI_STATE_L0 == pld_get_mhi_state(scn->qdf_dev->dev))) {
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hal_write32_mb(scn->hal_soc, ce_state->ce_wrt_idx_offset, val);
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qdf_atomic_inc(&scn->wstats.direct);
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ce_state->wstats.direct++;
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} else {
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hif_reg_write_enqueue(scn, ce_state, val);
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}
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}
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#else
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static inline QDF_STATUS hif_delayed_reg_write_init(struct hif_softc *scn)
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{
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return QDF_STATUS_SUCCESS;
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}
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static inline void hif_delayed_reg_write_deinit(struct hif_softc *scn)
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{
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}
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#endif
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#if defined(QCA_WIFI_WCN6450)
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static QDF_STATUS hif_hal_attach(struct hif_softc *scn)
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{
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@@ -1644,6 +1999,11 @@ QDF_STATUS hif_enable(struct hif_opaque_softc *hif_ctx, struct device *dev,
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goto disable_bus;
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}
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if (hif_delayed_reg_write_init(scn) != QDF_STATUS_SUCCESS) {
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hif_err("unable to initialize delayed reg write");
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goto hal_detach;
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}
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if (hif_bus_configure(scn)) {
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hif_err("Target probe failed");
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status = QDF_STATUS_E_FAILURE;
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@@ -1682,6 +2042,7 @@ void hif_disable(struct hif_opaque_softc *hif_ctx, enum hif_disable_type type)
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if (!scn)
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return;
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hif_delayed_reg_write_deinit(scn);
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hif_set_enable_detection(hif_ctx, false);
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hif_latency_detect_timer_stop(hif_ctx);
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