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Merge "msm: camera: cpas: Add qosgen shaping config" into camera-kernel.lnx.4.0

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这个提交包含在：
Camera Software Integration
2020-08-28 13:08:20 -07:00
提交者 Gerrit - the friendly Code Review server
父节点 3af2f6333f 86c892ec3a
当前提交 a2c86345c2
共修改 3 个文件，包含 519 行新增和 1 行删除
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6
drivers/cam_cpas/cpas_top/cam_cpastop_hw.h
查看文件

@@ -160,6 +160,9 @@ enum cam_camnoc_port_type {
* @danger_lut: Danger LUT mapping for this connection
* @safe_lut: Safe LUT mapping for this connection
* @ubwc_ctl: UBWC control settings for this connection
* @qosgen_mainctl: qosgen shaping control configuration for this connection
* @qosgen_shaping_low: qosgen shaping low configuration for this connection
* @qosgen_shaping_high: qosgen shaping high configuration for this connection
*
*/
struct cam_camnoc_specific {
@@ -172,6 +175,9 @@ struct cam_camnoc_specific {
struct cam_cpas_reg safe_lut;
struct cam_cpas_reg ubwc_ctl;
struct cam_cpas_reg flag_out_set0_low;
struct cam_cpas_reg qosgen_mainctl;
struct cam_cpas_reg qosgen_shaping_low;
struct cam_cpas_reg qosgen_shaping_high;
};
/**

258
drivers/cam_cpas/cpas_top/cpastop_v580_100.h
查看文件

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
*/
#ifndef _CPASTOP_V580_100_H_
@@ -263,6 +263,27 @@ static struct cam_camnoc_specific
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x408, /* CDM_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x420, /* CDM_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x424, /* CDM_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_LINEAR,
@@ -308,6 +329,27 @@ static struct cam_camnoc_specific
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE08, /* IFE_LINEAR_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE20, /* IFE_LINEAR_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE24, /* IFE_LINEAR_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_RDI_RD,
@@ -353,6 +395,27 @@ static struct cam_camnoc_specific
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xF08, /* IFE_RDI_RD_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xF20, /* IFE_RDI_RD_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xF24, /* IFE_RDI_RD_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_RDI_WR,
@@ -398,6 +461,27 @@ static struct cam_camnoc_specific
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1808, /* IFE_RDI_WR_0_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1820, /* IFE_RDI_WR_0_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1824, /* IFE_RDI_WR_0_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_RDI_WR_1,
@@ -443,6 +527,27 @@ static struct cam_camnoc_specific
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7C08, /* IFE_RDI_WR_1_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7C20, /* IFE_RDI_WR_1_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7C24, /* IFE_RDI_WR_1_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_UBWC_STATS,
@@ -493,6 +598,29 @@ static struct cam_camnoc_specific
.offset = 0x1B88, /* IFE_UBWC_STATS_0_ENCCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1908, /* IFE_UBWC_STATS_0_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1920,
/* IFE_UBWC_STATS_0_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1924,
/* IFE_UBWC_STATS_0_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_UBWC_STATS_1,
@@ -543,6 +671,29 @@ static struct cam_camnoc_specific
.offset = 0x7788, /* IFE_UBWC_STATS_1_ENCCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7C88, /* IFE_UBWC_STATS_1_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7CA0,
/* IFE_UBWC_STATS_1_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7CA4,
/* IFE_UBWC_STATS_1_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IPE0_RD,
@@ -594,6 +745,27 @@ static struct cam_camnoc_specific
.offset = 0x1F08, /* IPE0_RD_DECCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2208, /* IPE0_RD_QOSGEN_MAINCTL */
.value = 0x2,
},
.qosgen_shaping_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2220, /* IPE0_RD_QOSGEN_SHAPING_LOW */
.value = 0x13131313,
},
.qosgen_shaping_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2224, /* IPE0_RD_QOSGEN_SHAPING_HIGH */
.value = 0x13131313,
},
},
{
.port_type = CAM_CAMNOC_IPE1_BPS_RD,
@@ -645,6 +817,27 @@ static struct cam_camnoc_specific
.offset = 0x2508, /* IPE1_BPS_RD_DECCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2308, /* IPE1_BPS_RD_QOSGEN_MAINCTL */
.value = 0x2,
},
.qosgen_shaping_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2320, /* IPE1_BPS_RD_QOSGEN_SHAPING_LOW */
.value = 0x24242424,
},
.qosgen_shaping_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2324, /* IPE1_BPS_RD_QOSGEN_SHAPING_HIGH */
.value = 0x24242424,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_WR,
@@ -696,6 +889,27 @@ static struct cam_camnoc_specific
.offset = 0x2988, /* IPE_BPS_WR_ENCCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2C08, /* IPE_BPS_WR_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2C20, /* IPE_BPS_WR_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2C24, /* IPE_BPS_WR_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
@@ -738,6 +952,27 @@ static struct cam_camnoc_specific
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2D08, /* JPEG_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2D20, /* JPEG_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2D24, /* JPEG_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_ICP,
@@ -749,6 +984,27 @@ static struct cam_camnoc_specific
.offset = 0x3888,
.value = 0x100000,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3488, /* ICP_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34A0, /* ICP_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34A4, /* ICP_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
};

256
drivers/cam_cpas/cpas_top/cpastop_v580_custom.h
查看文件

@@ -263,6 +263,27 @@ static struct cam_camnoc_specific
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x408, /* CDM_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x420, /* CDM_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x424, /* CDM_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_LINEAR,
@@ -308,6 +329,27 @@ static struct cam_camnoc_specific
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE08, /* IFE_LINEAR_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE20, /* IFE_LINEAR_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xE24, /* IFE_LINEAR_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_RDI_RD,
@@ -353,6 +395,27 @@ static struct cam_camnoc_specific
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xF08, /* IFE_RDI_RD_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xF20, /* IFE_RDI_RD_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0xF24, /* IFE_RDI_RD_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_RDI_WR,
@@ -398,6 +461,27 @@ static struct cam_camnoc_specific
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1808, /* IFE_RDI_WR_0_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1820, /* IFE_RDI_WR_0_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1824, /* IFE_RDI_WR_0_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_RDI_WR_1,
@@ -443,6 +527,27 @@ static struct cam_camnoc_specific
*/
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7C08, /* IFE_RDI_WR_1_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7C20, /* IFE_RDI_WR_1_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7C24, /* IFE_RDI_WR_1_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_UBWC_STATS,
@@ -493,6 +598,29 @@ static struct cam_camnoc_specific
.offset = 0x1B88, /* IFE_UBWC_STATS_0_ENCCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1908, /* IFE_UBWC_STATS_0_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1920,
/* IFE_UBWC_STATS_0_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x1924,
/* IFE_UBWC_STATS_0_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IFE_UBWC_STATS_1,
@@ -543,6 +671,29 @@ static struct cam_camnoc_specific
.offset = 0x7788, /* IFE_UBWC_STATS_1_ENCCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7C88, /* IFE_UBWC_STATS_1_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7CA0,
/* IFE_UBWC_STATS_1_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x7CA4,
/* IFE_UBWC_STATS_1_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_IPE0_RD,
@@ -594,6 +745,27 @@ static struct cam_camnoc_specific
.offset = 0x1F08, /* IPE0_RD_DECCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2208, /* IPE0_RD_QOSGEN_MAINCTL */
.value = 0x2,
},
.qosgen_shaping_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2220, /* IPE0_RD_QOSGEN_SHAPING_LOW */
.value = 0x13131313,
},
.qosgen_shaping_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2224, /* IPE0_RD_QOSGEN_SHAPING_HIGH */
.value = 0x13131313,
},
},
{
.port_type = CAM_CAMNOC_IPE1_BPS_RD,
@@ -645,6 +817,27 @@ static struct cam_camnoc_specific
.offset = 0x2508, /* IPE1_BPS_RD_DECCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2308, /* IPE1_BPS_RD_QOSGEN_MAINCTL */
.value = 0x2,
},
.qosgen_shaping_low = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2320, /* IPE1_BPS_RD_QOSGEN_SHAPING_LOW */
.value = 0x24242424,
},
.qosgen_shaping_high = {
.enable = true,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2324, /* IPE1_BPS_RD_QOSGEN_SHAPING_HIGH */
.value = 0x24242424,
},
},
{
.port_type = CAM_CAMNOC_IPE_BPS_WR,
@@ -696,6 +889,27 @@ static struct cam_camnoc_specific
.offset = 0x2988, /* IPE_BPS_WR_ENCCTL_LOW */
.value = 1,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2C08, /* IPE_BPS_WR_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2C20, /* IPE_BPS_WR_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2C24, /* IPE_BPS_WR_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_JPEG,
@@ -738,6 +952,27 @@ static struct cam_camnoc_specific
.ubwc_ctl = {
.enable = false,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2D08, /* JPEG_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2D20, /* JPEG_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x2D24, /* JPEG_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
{
.port_type = CAM_CAMNOC_ICP,
@@ -749,6 +984,27 @@ static struct cam_camnoc_specific
.offset = 0x3888,
.value = 0x100000,
},
.qosgen_mainctl = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x3488, /* ICP_QOSGEN_MAINCTL */
.value = 0x0,
},
.qosgen_shaping_low = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34A0, /* ICP_QOSGEN_SHAPING_LOW */
.value = 0x0,
},
.qosgen_shaping_high = {
.enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE,
.masked_value = 0,
.offset = 0x34A4, /* ICP_QOSGEN_SHAPING_HIGH */
.value = 0x0,
},
},
};